Add DMA module

Author: JalonWong

Cargo.toml

@@ -49,11 +49,12 @@
     cortex-m = "0.7"
     cortex-m-rt = "0.7"
     critical-section = "1.2"
+    embedded-dma = "0.2"
     embedded-hal = "1.0"
     embedded-hal-nb = "1.0"
     embedded-io = "0.6"
     fugit = "0.3"
-    fugit-timer = "0.1.3"
+    fugit-timer = "0.1"
     nb = "1.1"
     rtic-monotonic = { version = "1.0", optional = true }
     rtrb = { version = "0.3", default-features = false }

examples/f103c8/src/main.rs

@@ -93,6 +93,9 @@ fn main() -> ! {
         &all_it::USART1_CB,
     );
 
+    let dma1 = dp.DMA1.split(&mut mcu.rcc);
+    let dma_rx = dma1.5;
+
     // LED --------------------------------------
 
     let mut led = gpiob

scripts/base.py

@@ -8,3 +8,22 @@ def red(s: str) -> str:
 
 def blue(s: str) -> str:
     return f"\033[1;34m{s}\033[0m"
+
+
+class Write:
+    def __init__(self, file_name: str, dry_run: bool = False) -> None:
+        if dry_run:
+            self.f = None
+        else:
+            self.f = open(file_name, "w", encoding="utf-8")
+
+    def write(self, content: str) -> None:
+        if self.f:
+            self.f.write(content)
+        else:
+            print(content, end="")
+
+    def close(self) -> None:
+        if self.f:
+            self.f.close()
+            self.f = None

scripts/generate_dma_table.py

@@ -0,0 +1,87 @@
+import csv
+import os
+import pprint
+import subprocess
+
+from base import Write
+
+SCRIPT = os.path.relpath(__file__, os.getcwd()).replace("\\", "/")
+
+
+def match_filter(filter: str, name: str) -> bool:
+    if filter == "UART":
+        return name.startswith("UART") or name.startswith("USART")
+    return name.startswith(filter)
+
+
+FUNC_TABLE = {
+    "TX": "Tx",
+    "RX": "Rx",
+}
+
+
+TEMPLATE = """
+impl DmaBind{func}<pac::{peri}> for {dma}::{ch} {{}}"""
+
+
+def write_item(dma: str, ch: str, func: str, w: Write) -> None:
+    ch = ch.replace("ch", "C")
+    (peri, func) = func.split("_", 1)
+    func = FUNC_TABLE.get(func, "")
+    w.write(TEMPLATE.format(func=func, peri=peri, dma=dma, ch=ch))
+
+
+def write_table(d: dict, filter: str, w: Write) -> None:
+    for dma, ch_table in sorted(d.items()):
+        for ch, func_list in sorted(ch_table.items()):
+            for func in sorted(func_list):
+                if match_filter(filter, func):
+                    write_item(dma, ch, func, w)
+
+
+def parse_dma_info(row: list[str], ret_d: dict) -> None:
+    dma = row[0]
+    channel = row[1]
+    func_list: list[str] = []
+    for func in row[2:]:
+        if func:
+            func_list.append(func)
+
+    p = ret_d.setdefault(dma, {})
+    p[channel] = func_list
+
+
+def csv_to_code(csv_file: str, show: bool = False) -> None:
+    print(csv_file)
+    d: dict = {}
+    with open(csv_file, newline="", encoding="utf-8") as f:
+        reader = csv.reader(f, delimiter=",", quotechar='"')
+        for row in reader:
+            if row[0]:
+                parse_dma_info(row, d)
+
+    if show:
+        pprint.pprint(d)
+
+    target_file = "src/dma.rs"
+    with open(target_file, "r", encoding="utf-8") as f:
+        code = f.read()
+        i = code.find("// table") + len("// table")
+        before = code[:i]
+        code = code[i:]
+
+    w = Write(target_file)
+    w.write(before)
+    w.write("\n// Do NOT manually modify the code.\n")
+    w.write(
+        f"// It's generated by {SCRIPT} from {csv_file}\n",
+    )
+
+    write_table(d, "UART", w)
+
+    w.close()
+    subprocess.run(["rustfmt", target_file])
+
+
+if __name__ == "__main__":
+    csv_to_code("scripts/table/stm32f1_dma_table.csv")

scripts/generate_remap_table.py

@@ -2,7 +2,8 @@
 import os
 import pprint
 import subprocess
-from io import TextIOWrapper
+
+from base import Write
 
 DRY_RUN = False
 SCRIPT = os.path.relpath(__file__, os.getcwd()).replace("\\", "/")
@@ -34,25 +35,6 @@
 }
 
 
-class Write:
-    def __init__(self, file_name: str) -> None:
-        if DRY_RUN:
-            self.f = None
-        else:
-            self.f = open(file_name, "w", encoding="utf-8")
-
-    def write(self, content: str) -> None:
-        if self.f:
-            self.f.write(content)
-        else:
-            print(content, end="")
-
-    def close(self) -> None:
-        if self.f:
-            self.f.close()
-            self.f = None
-
-
 def match_filter(filter: str, name: str) -> bool:
     if filter == "UART":
         return name.startswith("UART") or name.startswith("USART")
@@ -149,7 +131,7 @@ def write_table(d: dict, filter: str, csv_file: str, target_file: str) -> None:
         before = code[:i]
         code = code[i:]
 
-    w = Write(target_file)
+    w = Write(target_file, DRY_RUN)
     w.write(before)
     w.write("\n// Do NOT manually modify the code.\n")
     w.write(

src/common/dma/mod.rs

@@ -0,0 +1,32 @@
+pub trait DmaChannel {
+    fn start(&mut self);
+    fn stop(&mut self);
+
+    fn set_peripheral_address<T: Sized>(
+        &mut self,
+        address: usize,
+        mem_to_periph: bool,
+        increase: bool,
+        circular: bool,
+    );
+    fn set_memory_address(&mut self, address: usize, increase: bool);
+    fn set_transfer_length(&mut self, len: usize);
+    fn set_memory_buf_for_peripheral<T: Sized>(&mut self, buf: &[T]) {
+        self.set_memory_address(buf.as_ptr() as usize, true);
+        self.set_transfer_length(buf.len());
+    }
+
+    fn set_memory_to_memory<T: Sized>(&mut self, src_addr: usize, dst_addr: usize, len: usize);
+
+    fn get_left_len(&self) -> usize;
+    fn in_progress(&self) -> bool;
+
+    fn set_interrupt(&mut self, event: DmaEvent, enable: bool);
+    fn is_interrupted(&mut self, event: DmaEvent) -> bool;
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DmaEvent {
+    TransferComplete,
+    HalfTransfer,
+}

src/common/mod.rs

@@ -1,3 +1,4 @@
+pub mod dma;
 pub mod ringbuf;
 pub mod simplest_heap;
 pub mod timer;

src/common/uart/mod.rs

@@ -1,107 +1,20 @@
-use crate::ringbuf::{Consumer, Producer, RingBuffer};
-use embedded_hal_nb as e_nb;
-use embedded_io as e_io;
-
+mod uart_dma_ringbuf_rx;
+pub use uart_dma_ringbuf_rx::*;
 mod uart_it;
+pub use uart_it::*;
 mod uart_poll;
+pub use uart_poll::*;
+
+use embedded_hal_nb as e_nb;
+use embedded_io as e_io;
 
 pub use core::convert::Infallible;
-pub use uart_it::*;
-pub use uart_poll::*;
 
 // pub mod uart_dma_tx;
 // pub use uart_dma_tx::*;
-// pub mod uart_dma_ringbuf_rx;
-// pub use uart_dma_ringbuf_rx::*;
 // pub mod uart_dma_ringbuf_tx;
 // pub use uart_dma_ringbuf_tx::*;
 
-/// UART Transmitter
-pub struct Tx<U> {
-    uart: [U; 2],
-}
-
-impl<U: UartPeriph> Tx<U> {
-    pub(crate) fn new(uart: [U; 2]) -> Self {
-        Self { uart }
-    }
-
-    // pub fn get_interrupt_handler(&self) -> UartInterrupt<U> {
-    //     UartInterrupt::new(unsafe { self.uart.steal_mut() })
-    // }
-
-    pub fn into_poll(self, retry_times: u32, flush_retry_times: u32) -> UartPollTx<U> {
-        let [uart, _] = self.uart;
-        UartPollTx::<U>::new(uart, retry_times, flush_retry_times)
-    }
-
-    pub fn into_interrupt(
-        self,
-        buf_size: usize,
-        transmit_retry_times: u32,
-        flush_retry_times: u32,
-    ) -> (UartInterruptTx<U>, UartInterruptTxHandler<U>) {
-        let (w, r) = RingBuffer::<u8>::new(buf_size);
-        let [u1, u2] = self.uart;
-        (
-            UartInterruptTx::new(u1, w, transmit_retry_times, flush_retry_times),
-            UartInterruptTxHandler::new(u2, r),
-        )
-    }
-
-    // pub fn into_dma<CH>(self, dma_ch: CH) -> UartDmaTx<U, CH>
-    // where
-    //     CH: BindDmaTx<U>,
-    // {
-    //     UartDmaTx::<U, CH>::new(self.uart, dma_ch)
-    // }
-
-    // pub fn into_dma_ringbuf<CH>(self, dma_ch: CH, buf_size: usize) -> UartDmaBufTx<U, CH>
-    // where
-    //     CH: BindDmaTx<U>,
-    // {
-    //     UartDmaBufTx::<U, CH>::new(self.uart, dma_ch, buf_size)
-    // }
-}
-
-// ------------------------------------------------------------------------------------------------
-
-/// UART Receiver
-pub struct Rx<U: UartPeriph> {
-    uart: [U; 2],
-}
-
-impl<U: UartPeriph> Rx<U> {
-    pub(crate) fn new(uart: [U; 2]) -> Self {
-        Self { uart }
-    }
-
-    pub fn into_poll(self, retry_times: u32, continue_retry_times: u32) -> UartPollRx<U> {
-        let [uart, _] = self.uart;
-        UartPollRx::<U>::new(uart, retry_times, continue_retry_times)
-    }
-
-    pub fn into_interrupt(
-        self,
-        buf_size: usize,
-        retry_times: u32,
-    ) -> (UartInterruptRx<U>, UartInterruptRxHandler<U>) {
-        let (w, r) = RingBuffer::<u8>::new(buf_size);
-        let [u1, u2] = self.uart;
-        (
-            UartInterruptRx::new(u1, r, retry_times),
-            UartInterruptRxHandler::new(u2, w),
-        )
-    }
-
-    // pub fn into_dma_circle<CH>(self, dma_ch: CH, buf_size: usize) -> UartDmaBufRx<U, CH>
-    // where
-    //     CH: BindDmaRx<U>,
-    // {
-    //     UartDmaBufRx::<U, CH>::new(self.uart, dma_ch, buf_size)
-    // }
-}
-
 // ------------------------------------------------------------------------------------------------
 
 // UART idle interrupt handler