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JalonWongJalonWong
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Simplify remap parameters
1 parent 2dd83f9 commit 0c57c88

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8 files changed

+235
-66
lines changed

8 files changed

+235
-66
lines changed

‎.github/workflows/release.yml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,9 @@ jobs:
3838
- uses: dtolnay/rust-toolchain@stable
3939
with:
4040
targets: thumbv7m-none-eabi
41-
- name: Dry run
42-
if: github.ref_type != 'tag'
43-
run: cargo publish --features=stm32f103,xG --dry-run
41+
# - name: Dry run
42+
# if: github.ref_type != 'tag'
43+
# run: cargo publish --features=stm32f103,xG --dry-run
4444
- uses: rust-lang/crates-io-auth-action@v1
4545
if: github.ref_type == 'tag'
4646
id: auth

‎examples/f103c8/src/main.rs‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -77,10 +77,10 @@ fn main() -> ! {
7777

7878
// UART -------------------------------------
7979

80-
// let pin_tx = Some(gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh));
81-
// let pin_rx = Some(gpioa.pa10.into_pull_up_input(&mut gpioa.crh));
82-
let pin_tx = Some(gpiob.pb6.into_alternate_push_pull(&mut gpiob.crl));
83-
let pin_rx = Some(gpiob.pb7.into_pull_up_input(&mut gpiob.crl));
80+
// let pin_tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
81+
// let pin_rx = gpioa.pa10.into_pull_up_input(&mut gpioa.crh);
82+
let pin_tx = gpiob.pb6.into_alternate_push_pull(&mut gpiob.crl);
83+
let pin_rx = gpiob.pb7.into_pull_up_input(&mut gpiob.crl);
8484
// let pin_rx = hal::afio::NONE_PIN;
8585

8686
let config = uart::Config::default();
@@ -122,7 +122,7 @@ fn main() -> ! {
122122
let mut tim1 = dp.TIM1.constrain(&mut mcu);
123123
tim1.set_count_direction(CountDirection::Up); // Optional
124124
let (mut bt, Some(mut ch1), _) =
125-
tim1.into_pwm2::<RemapDefault<_>>((Some(c1), NONE_PIN), 20.kHz(), true, &mut mcu)
125+
tim1.into_pwm2::<RemapDefault<_>>((c1, NONE_PIN), 20.kHz(), true, &mut mcu)
126126
else {
127127
panic!()
128128
};

‎scripts/generate_remap_table.py‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,15 @@ def write_reg_operation(d: dict, filter: str, w: Write) -> None:
7878
w.write(REG_TEMPLATE.format(mode=mode, peri=peri, op=op))
7979

8080

81+
BINDER_BODY = """ {{
82+
#[inline(always)]
83+
fn is_pin(&self) -> bool {{
84+
{v}
85+
}}
86+
}}
87+
"""
88+
89+
8190
def write_binder_type(d: dict, filter: str, w: Write) -> None:
8291
w.write("\n// Binder types ------------------\n\n")
8392
func_list: list[str] = []
@@ -90,8 +99,8 @@ def write_binder_type(d: dict, filter: str, w: Write) -> None:
9099
func_list = sorted(list(set(func_list)))
91100
for func in func_list:
92101
name = func_pin_name(filter, func)
93-
w.write(f"pub trait {name}<REMAP> {{}}")
94-
w.write(f"impl<T> {name}<T> for NonePin {{}}")
102+
w.write(f"pub trait {name}<REMAP>" + BINDER_BODY.format(v="true"))
103+
w.write(f"impl<T> {name}<T> for NonePin" + BINDER_BODY.format(v="false"))
95104
w.write("\n")
96105

97106

‎src/afio/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ pub struct RemapPartial1<REG>(PhantomData<REG>);
7070
pub struct RemapPartial2<REG>(PhantomData<REG>);
7171
pub struct RemapFull<REG>(PhantomData<REG>);
7272
pub struct NonePin {}
73-
pub const NONE_PIN: Option<NonePin> = None::<NonePin>;
73+
pub const NONE_PIN: NonePin = NonePin {};
7474

7575
/// AF remap and debug I/O configuration register (MAPR)
7676
///

‎src/afio/timer_remap.rs‎

Lines changed: 108 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -8,24 +8,114 @@ use crate::{gpio::*, pac::*};
88

99
// Binder types ------------------
1010

11-
pub trait TimBkinPin<REMAP> {}
12-
impl<T> TimBkinPin<T> for NonePin {}
13-
pub trait TimCh1Pin<REMAP> {}
14-
impl<T> TimCh1Pin<T> for NonePin {}
15-
pub trait TimCh1nPin<REMAP> {}
16-
impl<T> TimCh1nPin<T> for NonePin {}
17-
pub trait TimCh2Pin<REMAP> {}
18-
impl<T> TimCh2Pin<T> for NonePin {}
19-
pub trait TimCh2nPin<REMAP> {}
20-
impl<T> TimCh2nPin<T> for NonePin {}
21-
pub trait TimCh3Pin<REMAP> {}
22-
impl<T> TimCh3Pin<T> for NonePin {}
23-
pub trait TimCh3nPin<REMAP> {}
24-
impl<T> TimCh3nPin<T> for NonePin {}
25-
pub trait TimCh4Pin<REMAP> {}
26-
impl<T> TimCh4Pin<T> for NonePin {}
27-
pub trait TimEtrPin<REMAP> {}
28-
impl<T> TimEtrPin<T> for NonePin {}
11+
pub trait TimBkinPin<REMAP> {
12+
#[inline(always)]
13+
fn is_pin(&self) -> bool {
14+
true
15+
}
16+
}
17+
impl<T> TimBkinPin<T> for NonePin {
18+
#[inline(always)]
19+
fn is_pin(&self) -> bool {
20+
false
21+
}
22+
}
23+
pub trait TimCh1Pin<REMAP> {
24+
#[inline(always)]
25+
fn is_pin(&self) -> bool {
26+
true
27+
}
28+
}
29+
impl<T> TimCh1Pin<T> for NonePin {
30+
#[inline(always)]
31+
fn is_pin(&self) -> bool {
32+
false
33+
}
34+
}
35+
pub trait TimCh1nPin<REMAP> {
36+
#[inline(always)]
37+
fn is_pin(&self) -> bool {
38+
true
39+
}
40+
}
41+
impl<T> TimCh1nPin<T> for NonePin {
42+
#[inline(always)]
43+
fn is_pin(&self) -> bool {
44+
false
45+
}
46+
}
47+
pub trait TimCh2Pin<REMAP> {
48+
#[inline(always)]
49+
fn is_pin(&self) -> bool {
50+
true
51+
}
52+
}
53+
impl<T> TimCh2Pin<T> for NonePin {
54+
#[inline(always)]
55+
fn is_pin(&self) -> bool {
56+
false
57+
}
58+
}
59+
pub trait TimCh2nPin<REMAP> {
60+
#[inline(always)]
61+
fn is_pin(&self) -> bool {
62+
true
63+
}
64+
}
65+
impl<T> TimCh2nPin<T> for NonePin {
66+
#[inline(always)]
67+
fn is_pin(&self) -> bool {
68+
false
69+
}
70+
}
71+
pub trait TimCh3Pin<REMAP> {
72+
#[inline(always)]
73+
fn is_pin(&self) -> bool {
74+
true
75+
}
76+
}
77+
impl<T> TimCh3Pin<T> for NonePin {
78+
#[inline(always)]
79+
fn is_pin(&self) -> bool {
80+
false
81+
}
82+
}
83+
pub trait TimCh3nPin<REMAP> {
84+
#[inline(always)]
85+
fn is_pin(&self) -> bool {
86+
true
87+
}
88+
}
89+
impl<T> TimCh3nPin<T> for NonePin {
90+
#[inline(always)]
91+
fn is_pin(&self) -> bool {
92+
false
93+
}
94+
}
95+
pub trait TimCh4Pin<REMAP> {
96+
#[inline(always)]
97+
fn is_pin(&self) -> bool {
98+
true
99+
}
100+
}
101+
impl<T> TimCh4Pin<T> for NonePin {
102+
#[inline(always)]
103+
fn is_pin(&self) -> bool {
104+
false
105+
}
106+
}
107+
pub trait TimEtrPin<REMAP> {
108+
#[inline(always)]
109+
fn is_pin(&self) -> bool {
110+
true
111+
}
112+
}
113+
impl<T> TimEtrPin<T> for NonePin {
114+
#[inline(always)]
115+
fn is_pin(&self) -> bool {
116+
false
117+
}
118+
}
29119

30120
// Bind pins ---------------------
31121

‎src/afio/uart_remap.rs‎

Lines changed: 60 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11,16 +11,66 @@ use crate::{
1111

1212
// Binder types ------------------
1313

14-
pub trait UartCkPin<REMAP> {}
15-
impl<T> UartCkPin<T> for NonePin {}
16-
pub trait UartCtsPin<REMAP> {}
17-
impl<T> UartCtsPin<T> for NonePin {}
18-
pub trait UartRtsPin<REMAP> {}
19-
impl<T> UartRtsPin<T> for NonePin {}
20-
pub trait UartRxPin<REMAP> {}
21-
impl<T> UartRxPin<T> for NonePin {}
22-
pub trait UartTxPin<REMAP> {}
23-
impl<T> UartTxPin<T> for NonePin {}
14+
pub trait UartCkPin<REMAP> {
15+
#[inline(always)]
16+
fn is_pin(&self) -> bool {
17+
true
18+
}
19+
}
20+
impl<T> UartCkPin<T> for NonePin {
21+
#[inline(always)]
22+
fn is_pin(&self) -> bool {
23+
false
24+
}
25+
}
26+
pub trait UartCtsPin<REMAP> {
27+
#[inline(always)]
28+
fn is_pin(&self) -> bool {
29+
true
30+
}
31+
}
32+
impl<T> UartCtsPin<T> for NonePin {
33+
#[inline(always)]
34+
fn is_pin(&self) -> bool {
35+
false
36+
}
37+
}
38+
pub trait UartRtsPin<REMAP> {
39+
#[inline(always)]
40+
fn is_pin(&self) -> bool {
41+
true
42+
}
43+
}
44+
impl<T> UartRtsPin<T> for NonePin {
45+
#[inline(always)]
46+
fn is_pin(&self) -> bool {
47+
false
48+
}
49+
}
50+
pub trait UartRxPin<REMAP> {
51+
#[inline(always)]
52+
fn is_pin(&self) -> bool {
53+
true
54+
}
55+
}
56+
impl<T> UartRxPin<T> for NonePin {
57+
#[inline(always)]
58+
fn is_pin(&self) -> bool {
59+
false
60+
}
61+
}
62+
pub trait UartTxPin<REMAP> {
63+
#[inline(always)]
64+
fn is_pin(&self) -> bool {
65+
true
66+
}
67+
}
68+
impl<T> UartTxPin<T> for NonePin {
69+
#[inline(always)]
70+
fn is_pin(&self) -> bool {
71+
false
72+
}
73+
}
2474

2575
// Bind pins ---------------------
2676

‎src/timer/mod.rs‎

Lines changed: 35 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ impl<'a, TIM: Instance + TimerWithPwm1Ch + Steal + 'a> Timer<TIM> {
176176
impl<'a, TIM: Instance + TimerWithPwm2Ch + Steal + 'a> Timer<TIM> {
177177
pub fn into_pwm2<REMAP: RemapMode<TIM>>(
178178
mut self,
179-
pins: (Option<impl TimCh1Pin<REMAP>>, Option<impl TimCh2Pin<REMAP>>),
179+
pins: (impl TimCh1Pin<REMAP>, impl TimCh2Pin<REMAP>),
180180
update_freq: Hertz,
181181
preload: bool,
182182
mcu: &mut Mcu,
@@ -189,12 +189,16 @@ impl<'a, TIM: Instance + TimerWithPwm2Ch + Steal + 'a> Timer<TIM> {
189189
self.tim.enable_preload(preload);
190190
self.tim.config_freq(self.clk, update_freq);
191191

192-
let c1 = pins
193-
.0
194-
.map(|_| PwmChannel1::new(unsafe { self.tim.steal() }));
195-
let c2 = pins
196-
.1
197-
.map(|_| PwmChannel2::new(unsafe { self.tim.steal() }));
192+
let c1 = if pins.0.is_pin() {
193+
Some(PwmChannel1::new(unsafe { self.tim.steal() }))
194+
} else {
195+
None
196+
};
197+
let c2 = if pins.1.is_pin() {
198+
Some(PwmChannel2::new(unsafe { self.tim.steal() }))
199+
} else {
200+
None
201+
};
198202
let t = PwmTimer::new(self.tim, self.clk);
199203
(t, c1, c2)
200204
}
@@ -204,10 +208,10 @@ impl<'a, TIM: Instance + TimerWithPwm4Ch + Steal + 'a> Timer<TIM> {
204208
pub fn into_pwm4<REMAP: RemapMode<TIM>>(
205209
mut self,
206210
pins: (
207-
Option<impl TimCh1Pin<REMAP>>,
208-
Option<impl TimCh2Pin<REMAP>>,
209-
Option<impl TimCh3Pin<REMAP>>,
210-
Option<impl TimCh4Pin<REMAP>>,
211+
impl TimCh1Pin<REMAP>,
212+
impl TimCh2Pin<REMAP>,
213+
impl TimCh3Pin<REMAP>,
214+
impl TimCh4Pin<REMAP>,
211215
),
212216
update_freq: Hertz,
213217
preload: bool,
@@ -223,18 +227,26 @@ impl<'a, TIM: Instance + TimerWithPwm4Ch + Steal + 'a> Timer<TIM> {
223227
self.tim.enable_preload(preload);
224228
self.tim.config_freq(self.clk, update_freq);
225229

226-
let c1 = pins
227-
.0
228-
.map(|_| PwmChannel1::new(unsafe { self.tim.steal() }));
229-
let c2 = pins
230-
.1
231-
.map(|_| PwmChannel2::new(unsafe { self.tim.steal() }));
232-
let c3 = pins
233-
.2
234-
.map(|_| PwmChannel3::new(unsafe { self.tim.steal() }));
235-
let c4 = pins
236-
.3
237-
.map(|_| PwmChannel4::new(unsafe { self.tim.steal() }));
230+
let c1 = if pins.0.is_pin() {
231+
Some(PwmChannel1::new(unsafe { self.tim.steal() }))
232+
} else {
233+
None
234+
};
235+
let c2 = if pins.1.is_pin() {
236+
Some(PwmChannel2::new(unsafe { self.tim.steal() }))
237+
} else {
238+
None
239+
};
240+
let c3 = if pins.2.is_pin() {
241+
Some(PwmChannel3::new(unsafe { self.tim.steal() }))
242+
} else {
243+
None
244+
};
245+
let c4 = if pins.3.is_pin() {
246+
Some(PwmChannel4::new(unsafe { self.tim.steal() }))
247+
} else {
248+
None
249+
};
238250
let t = PwmTimer::new(self.tim, self.clk);
239251
(t, c1, c2, c3, c4)
240252
}

‎src/uart/mod.rs‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,17 +35,25 @@ pub struct Uart<U> {
3535
impl<U: UartPeriphExt> Uart<U> {
3636
pub fn into_tx_rx<REMAP: RemapMode<U>>(
3737
mut self,
38-
pins: (Option<impl UartTxPin<REMAP>>, Option<impl UartRxPin<REMAP>>),
38+
pins: (impl UartTxPin<REMAP>, impl UartRxPin<REMAP>),
3939
config: Config,
4040
mcu: &mut Mcu,
4141
) -> (Option<Tx<U>>, Option<Rx<U>>) {
4242
REMAP::remap(&mut mcu.afio);
4343
self.uart.config(config, mcu);
44-
self.uart.enable_comm(pins.0.is_some(), pins.1.is_some());
44+
self.uart.enable_comm(pins.0.is_pin(), pins.1.is_pin());
4545
unsafe {
4646
(
47-
pins.0.map(|_| Tx::new(self.uart.steal())),
48-
pins.1.map(|_| Rx::new(self.uart.steal())),
47+
if pins.0.is_pin() {
48+
Some(Tx::new(self.uart.steal()))
49+
} else {
50+
None
51+
},
52+
if pins.1.is_pin() {
53+
Some(Rx::new(self.uart.steal()))
54+
} else {
55+
None
56+
},
4957
)
5058
}
5159
}

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