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top.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.07 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "top.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "top"
Output Format : NGC
Target Device : xc6slx16-3-csg324
---- Source Options
Top Module Name : top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "D:\mips_mini\mips_mini.v" into library work
Parsing module <dmem>.
Parsing module <imem>.
Parsing module <alu>.
Parsing module <regfile>.
Parsing module <adder>.
Parsing module <sl2>.
Parsing module <signext>.
Parsing module <flopr>.
Parsing module <flopenr>.
Parsing module <mux2>.
Parsing module <mux4>.
Parsing module <mips>.
Parsing module <controller>.
Parsing module <maindec>.
Parsing module <aludec>.
Parsing module <datapath>.
Parsing module <rategen>.
Parsing module <top>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <top>.
Elaborating module <rategen>.
Elaborating module <mips>.
Elaborating module <controller>.
Elaborating module <maindec>.
Elaborating module <aludec>.
Elaborating module <datapath>.
Elaborating module <flopr(WIDTH=16)>.
Elaborating module <adder>.
Elaborating module <sl2>.
Elaborating module <mux2(WIDTH=16)>.
Elaborating module <regfile>.
WARNING:HDLCompiler:413 - "D:\mips_mini\mips_mini.v" Line 121: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "D:\mips_mini\mips_mini.v" Line 122: Result of 32-bit expression is truncated to fit in 16-bit target.
Elaborating module <mux4(WIDTH=3)>.
Elaborating module <mux4(WIDTH=16)>.
Elaborating module <signext>.
Elaborating module <alu>.
Elaborating module <imem>.
Elaborating module <dmem>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <top>.
Related source file is "D:\mips_mini\mips_mini.v".
Summary:
no macro.
Unit <top> synthesized.
Synthesizing Unit <rategen>.
Related source file is "D:\mips_mini\mips_mini.v".
Found 32-bit register for signal <Q>.
Found 32-bit adder for signal <Q[31]_GND_2_o_add_1_OUT> created at line 354.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
Unit <rategen> synthesized.
Synthesizing Unit <mips>.
Related source file is "D:\mips_mini\mips_mini.v".
Summary:
no macro.
Unit <mips> synthesized.
Synthesizing Unit <controller>.
Related source file is "D:\mips_mini\mips_mini.v".
Summary:
no macro.
Unit <controller> synthesized.
Synthesizing Unit <maindec>.
Related source file is "D:\mips_mini\mips_mini.v".
Found 8x11-bit Read Only RAM for signal <controls>
Summary:
inferred 1 RAM(s).
Unit <maindec> synthesized.
Synthesizing Unit <aludec>.
Related source file is "D:\mips_mini\mips_mini.v".
Summary:
no macro.
Unit <aludec> synthesized.
Synthesizing Unit <datapath>.
Related source file is "D:\mips_mini\mips_mini.v".
WARNING:Xst:647 - Input <instr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <datapath> synthesized.
Synthesizing Unit <flopr>.
Related source file is "D:\mips_mini\mips_mini.v".
WIDTH = 16
Found 16-bit register for signal <q>.
Summary:
inferred 16 D-type flip-flop(s).
Unit <flopr> synthesized.
Synthesizing Unit <adder>.
Related source file is "D:\mips_mini\mips_mini.v".
Found 16-bit adder for signal <y> created at line 129.
Summary:
inferred 1 Adder/Subtractor(s).
Unit <adder> synthesized.
Synthesizing Unit <sl2>.
Related source file is "D:\mips_mini\mips_mini.v".
WARNING:Xst:647 - Input <a<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <sl2> synthesized.
Synthesizing Unit <mux2>.
Related source file is "D:\mips_mini\mips_mini.v".
WIDTH = 16
Summary:
inferred 1 Multiplexer(s).
Unit <mux2> synthesized.
Synthesizing Unit <regfile>.
Related source file is "D:\mips_mini\mips_mini.v".
WARNING:Xst:3015 - Contents of array <rf> may be accessed with an index that does not cover the full array size or with a negative index. The RAM size is reduced to the index upper access or for only positive index values.
Found 8x16-bit dual-port RAM <Mram_rf> for signal <rf>.
Summary:
inferred 2 RAM(s).
inferred 2 Multiplexer(s).
Unit <regfile> synthesized.
Synthesizing Unit <mux4_1>.
Related source file is "D:\mips_mini\mips_mini.v".
WIDTH = 3
Summary:
no macro.
Unit <mux4_1> synthesized.
Synthesizing Unit <mux4_2>.
Related source file is "D:\mips_mini\mips_mini.v".
WIDTH = 16
Summary:
no macro.
Unit <mux4_2> synthesized.
Synthesizing Unit <signext>.
Related source file is "D:\mips_mini\mips_mini.v".
Summary:
no macro.
Unit <signext> synthesized.
Synthesizing Unit <alu>.
Related source file is "D:\mips_mini\mips_mini.v".
Found 16-bit subtractor for signal <a[15]_b[15]_sub_2_OUT> created at line 93.
Found 16-bit adder for signal <a[15]_b[15]_add_6_OUT> created at line 99.
Found 16-bit 7-to-1 multiplexer for signal <result> created at line 91.
Found 16-bit comparator greater for signal <a[15]_b[15]_LessThan_5_o> created at line 96
Summary:
inferred 2 Adder/Subtractor(s).
inferred 1 Comparator(s).
inferred 1 Multiplexer(s).
Unit <alu> synthesized.
Synthesizing Unit <imem>.
Related source file is "D:\mips_mini\mips_mini.v".
WARNING:Xst:647 - Input <a<5:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'RAM', unconnected in block 'imem', is tied to its initial value.
WARNING:Xst:3035 - Index value(s) does not match array range for signal <RAM>, simulation mismatch.
Found 11x16-bit single-port Read Only RAM <Mram_RAM> for signal <RAM>.
Summary:
inferred 1 RAM(s).
Unit <imem> synthesized.
Synthesizing Unit <dmem>.
Related source file is "D:\mips_mini\mips_mini.v".
WARNING:Xst:647 - Input <a<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <a<15:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 64x16-bit single-port RAM <Mram_RAM> for signal <RAM>.
Summary:
inferred 1 RAM(s).
Unit <dmem> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 5
11x16-bit single-port Read Only RAM : 1
64x16-bit single-port RAM : 1
8x11-bit single-port Read Only RAM : 1
8x16-bit dual-port RAM : 2
# Adders/Subtractors : 5
16-bit adder : 3
16-bit subtractor : 1
32-bit adder : 1
# Registers : 2
16-bit register : 1
32-bit register : 1
# Comparators : 1
16-bit comparator greater : 1
# Multiplexers : 6
16-bit 2-to-1 multiplexer : 3
16-bit 7-to-1 multiplexer : 1
32-bit 2-to-1 multiplexer : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <dmem>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_RAM> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 16-bit | |
| clkA | connected to signal <clk> | rise |
| weA | connected to signal <we> | high |
| addrA | connected to signal <a> | |
| diA | connected to signal <wd> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <dmem> synthesized (advanced).
Synthesizing (advanced) Unit <imem>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_RAM> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 11-word x 16-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <a> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <imem> synthesized (advanced).
Synthesizing (advanced) Unit <maindec>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_controls> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 11-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <op> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <controls> | |
-----------------------------------------------------------------------
Unit <maindec> synthesized (advanced).
Synthesizing (advanced) Unit <rategen>.
The following registers are absorbed into counter <Q>: 1 register on signal <Q>.
Unit <rategen> synthesized (advanced).
Synthesizing (advanced) Unit <regfile>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_rf> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 16-bit | |
| clkA | connected to signal <clk> | rise |
| weA | connected to signal <we3> | high |
| addrA | connected to signal <wa3> | |
| diA | connected to signal <wd3> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 8-word x 16-bit | |
| addrB | connected to signal <ra1> | |
| doB | connected to internal node | |
-----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_rf1> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 16-bit | |
| clkA | connected to signal <clk> | rise |
| weA | connected to signal <we3> | high |
| addrA | connected to signal <wa3> | |
| diA | connected to signal <wd3> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 8-word x 16-bit | |
| addrB | connected to signal <ra2> | |
| doB | connected to internal node | |
-----------------------------------------------------------------------
Unit <regfile> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 5
11x16-bit single-port distributed Read Only RAM : 1
64x16-bit single-port distributed RAM : 1
8x11-bit single-port distributed Read Only RAM : 1
8x16-bit dual-port distributed RAM : 2
# Adders/Subtractors : 4
16-bit adder : 3
16-bit subtractor : 1
# Counters : 1
32-bit up counter : 1
# Registers : 16
Flip-Flops : 16
# Comparators : 1
16-bit comparator greater : 1
# Multiplexers : 6
16-bit 2-to-1 multiplexer : 3
16-bit 7-to-1 multiplexer : 1
32-bit 2-to-1 multiplexer : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <flopr> ...
Optimizing unit <top> ...
Optimizing unit <datapath> ...
Optimizing unit <alu> ...
Optimizing unit <regfile> ...
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mips/dp/pcreg/q_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <dmem/Mram_RAM16> of sequential type is unconnected in block <top>.
WARNING:Xst:1710 - FF/Latch <rg/Q_27> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rg/Q_28> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rg/Q_29> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rg/Q_30> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rg/Q_31> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 1.
FlipFlop mips/dp/pcreg/q_1 has been replicated 3 time(s)
FlipFlop mips/dp/pcreg/q_2 has been replicated 2 time(s)
FlipFlop mips/dp/pcreg/q_3 has been replicated 2 time(s)
FlipFlop mips/dp/pcreg/q_4 has been replicated 3 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 41
Flip-Flops : 41
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : top.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 220
# GND : 1
# INV : 2
# LUT1 : 29
# LUT2 : 28
# LUT3 : 4
# LUT4 : 6
# LUT5 : 36
# LUT6 : 22
# MUXCY : 44
# VCC : 1
# XORCY : 47
# FlipFlops/Latches : 41
# FD : 27
# FDC : 14
# RAMS : 12
# RAM16X1D : 8
# RAM32M : 4
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 42
# IBUF : 1
# OBUF : 41
Device utilization summary:
---------------------------
Selected Device : 6slx16csg324-3
Slice Logic Utilization:
Number of Slice Registers: 41 out of 18224 0%
Number of Slice LUTs: 159 out of 9112 1%
Number used as Logic: 127 out of 9112 1%
Number used as Memory: 32 out of 2176 1%
Number used as RAM: 32
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 162
Number with an unused Flip Flop: 121 out of 162 74%
Number with an unused LUT: 3 out of 162 1%
Number of fully used LUT-FF pairs: 38 out of 162 23%
Number of unique control sets: 2
IO Utilization:
Number of IOs: 43
Number of bonded IOBs: 43 out of 232 18%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+---------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+---------------------------+-------+
cy(rg/cy<31>6:O) | BUFG(*)(mips/dp/pcreg/q_4)| 26 |
clk | BUFGP | 27 |
-----------------------------------+---------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 4.082ns (Maximum Frequency: 244.948MHz)
Minimum input arrival time before clock: 4.059ns
Maximum output required time after clock: 7.251ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'cy'
Clock period: 4.082ns (frequency: 244.948MHz)
Total number of paths / destination ports: 3601 / 106
-------------------------------------------------------------------------
Delay: 4.082ns (Levels of Logic = 7)
Source: mips/dp/pcreg/q_3_2 (FF)
Destination: mips/dp/rf/Mram_rf134 (RAM)
Source Clock: cy rising
Destination Clock: cy rising
Data Path: mips/dp/pcreg/q_3_2 to mips/dp/rf/Mram_rf134
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 17 0.447 1.028 mips/dp/pcreg/q_3_2 (mips/dp/pcreg/q_3_2)
LUT4:I3->O 13 0.205 0.932 imem/Mram_RAM81 (imem/Mram_RAM8)
RAM16X1D:DPRA1->DPO 2 0.205 0.617 mips/dp/rf/Mram_rf131 (mips/dp/rf/GND_12_o_read_port_6_OUT<12>)
LUT6:I5->O 1 0.205 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_lut<12> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_lut<12>)
MUXCY:S->O 1 0.172 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<12> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<12>)
MUXCY:CI->O 1 0.019 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<13> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<13>)
MUXCY:CI->O 0 0.019 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<14> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<14>)
XORCY:CI->O 3 0.180 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_xor<15> (dataadr_15_OBUF)
RAM16X1D:D 0.053 mips/dp/rf/Mram_rf44
----------------------------------------
Total 4.082ns (1.505ns logic, 2.577ns route)
(36.9% logic, 63.1% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.998ns (frequency: 250.150MHz)
Total number of paths / destination ports: 1107 / 27
-------------------------------------------------------------------------
Delay: 3.998ns (Levels of Logic = 3)
Source: rg/Q_7 (FF)
Destination: rg/Q_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: rg/Q_7 to rg/Q_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.447 0.981 rg/Q_7 (rg/Q_7)
LUT6:I0->O 3 0.203 0.898 rg/cy<31>4 (rg/cy<31>3)
LUT6:I2->O 14 0.203 0.958 rg/rst_cy_OR_1_o1 (rg/rst_cy_OR_1_o)
LUT2:I1->O 1 0.205 0.000 rg/Q_0_rstpot (rg/Q_0_rstpot)
FD:D 0.102 rg/Q_0
----------------------------------------
Total 3.998ns (1.160ns logic, 2.838ns route)
(29.0% logic, 71.0% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cy'
Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset: 2.656ns (Levels of Logic = 1)
Source: reset (PAD)
Destination: mips/dp/pcreg/q_4 (FF)
Destination Clock: cy rising
Data Path: reset to mips/dp/pcreg/q_4
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 16 1.222 1.004 reset_IBUF (reset_IBUF)
FDC:CLR 0.430 mips/dp/pcreg/q_1
----------------------------------------
Total 2.656ns (1.652ns logic, 1.004ns route)
(62.2% logic, 37.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 27 / 27
-------------------------------------------------------------------------
Offset: 4.059ns (Levels of Logic = 3)
Source: reset (PAD)
Destination: rg/Q_0 (FF)
Destination Clock: clk rising
Data Path: reset to rg/Q_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 16 1.222 1.369 reset_IBUF (reset_IBUF)
LUT6:I0->O 14 0.203 0.958 rg/rst_cy_OR_1_o1 (rg/rst_cy_OR_1_o)
LUT2:I1->O 1 0.205 0.000 rg/Q_0_rstpot (rg/Q_0_rstpot)
FD:D 0.102 rg/Q_0
----------------------------------------
Total 4.059ns (1.732ns logic, 2.327ns route)
(42.7% logic, 57.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cy'
Total number of paths / destination ports: 2107 / 40
-------------------------------------------------------------------------
Offset: 7.251ns (Levels of Logic = 8)
Source: mips/dp/pcreg/q_3_2 (FF)
Destination: dataadr<15> (PAD)
Source Clock: cy rising
Data Path: mips/dp/pcreg/q_3_2 to dataadr<15>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 17 0.447 1.028 mips/dp/pcreg/q_3_2 (mips/dp/pcreg/q_3_2)
LUT4:I3->O 13 0.205 0.932 imem/Mram_RAM81 (imem/Mram_RAM8)
RAM16X1D:DPRA1->DPO 2 0.205 0.617 mips/dp/rf/Mram_rf131 (mips/dp/rf/GND_12_o_read_port_6_OUT<12>)
LUT6:I5->O 1 0.205 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_lut<12> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_lut<12>)
MUXCY:S->O 1 0.172 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<12> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<12>)
MUXCY:CI->O 1 0.019 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<13> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<13>)
MUXCY:CI->O 0 0.019 0.000 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<14> (mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_cy<14>)
XORCY:CI->O 3 0.180 0.650 mips/dp/alu/Madd_a[15]_b[15]_add_6_OUT_xor<15> (dataadr_15_OBUF)
OBUF:I->O 2.571 dataadr_15_OBUF (dataadr<15>)
----------------------------------------
Total 7.251ns (4.023ns logic, 3.228ns route)
(55.5% logic, 44.5% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 3.998| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock cy
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cy | 4.082| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.20 secs
-->
Total memory usage is 259288 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 43 ( 0 filtered)
Number of infos : 5 ( 0 filtered)