-
Notifications
You must be signed in to change notification settings - Fork 1
/
top.drc
17 lines (14 loc) · 867 Bytes
/
top.drc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Tue Nov 20 23:16:14 2018
drc -z top.ncd top.pcf
WARNING:PhysDesignRules:367 - The signal <mips/dp/rf/Mram_rf11_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <mips/dp/rf/Mram_rf2_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <mips/dp/rf/Mram_rf12_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <mips/dp/rf/Mram_rf3_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 4 warnings. Please see the previously displayed
individual error or warning messages for more details.