@@ -600,18 +600,38 @@ static const struct {
600600void rfcore_ble_init (void ) {
601601 DEBUG_printf ("rfcore_ble_init\n" );
602602
603- // Clear any outstanding messages from ipcc_init.
604- tl_check_msg (& ipcc_mem_sys_queue , IPCC_CH_SYS , NULL );
605-
606603 // Configure and reset the BLE controller.
607- tl_sys_hci_cmd_resp (HCI_OPCODE (OGF_VENDOR , OCF_BLE_INIT ), (const uint8_t * )& ble_init_params , sizeof (ble_init_params ), 0 );
608- tl_ble_hci_cmd_resp (HCI_OPCODE (0x03 , 0x0003 ), NULL , 0 );
604+ if (!rfcore_ble_reset ()) {
605+ // ble init can fail if core2 has previously locked up. Reset HSI & rfcore to retry.
606+ LL_RCC_HSI_Disable ();
607+ mp_hal_delay_ms (100 );
608+ LL_RCC_HSI_Enable ();
609+
610+ rfcore_init ();
611+ rfcore_ble_reset ();
612+ }
609613
610614 // Enable PES rather than SEM7 to moderate flash access between the cores.
611615 uint8_t buf = 0 ; // FLASH_ACTIVITY_CONTROL_PES
612616 tl_sys_hci_cmd_resp (HCI_OPCODE (OGF_VENDOR , OCF_C2_SET_FLASH_ACTIVITY_CONTROL ), & buf , 1 , 0 );
613617}
614618
619+ bool rfcore_ble_reset (void ) {
620+ DEBUG_printf ("rfcore_ble_reset\n" );
621+
622+ // Clear any outstanding messages from ipcc_init.
623+ tl_check_msg (& ipcc_mem_sys_queue , IPCC_CH_SYS , NULL );
624+
625+ // Configure and reset the BLE controller.
626+ int ret = tl_sys_hci_cmd_resp (HCI_OPCODE (OGF_VENDOR , OCF_BLE_INIT ), (const uint8_t * )& ble_init_params , sizeof (ble_init_params ), 500 );
627+
628+ if (ret == - MP_ETIMEDOUT ) {
629+ return false;
630+ }
631+ tl_ble_hci_cmd_resp (HCI_OPCODE (0x03 , 0x0003 ), NULL , 0 );
632+ return true;
633+ }
634+
615635void rfcore_ble_hci_cmd (size_t len , const uint8_t * src ) {
616636 DEBUG_printf ("rfcore_ble_hci_cmd\n" );
617637
0 commit comments