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[FIRRTL] Use free variants of isa/cast/dyn_cast
Refer to https://mlir.llvm.org/deprecation/
1 parent 594e3fb commit 5955eff

29 files changed

+118
-122
lines changed

‎include/circt/Dialect/FIRRTL/FIRRTLAttributes.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ def AnnotationArrayAttr
2727
def PortAnnotationsAttr : ArrayAttrBase<
2828
And<[
2929
// Guarantee this is an ArrayAttr first
30-
CPred<"$_self.isa<::mlir::ArrayAttr>()">,
30+
CPred<"llvm::isa<::mlir::ArrayAttr>($_self)">,
3131
// Guarantee all elements are an array or a dictionary.
3232
CPred<"::llvm::all_of(cast<mlir::ArrayAttr>($_self), "
3333
"[&](::mlir::Attribute attr) { return isa<"

‎include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -212,12 +212,12 @@ def InstanceChoiceOp : HardwareDeclOp<"instance_choice", [
212212

213213
/// Return the default target attribute.
214214
FlatSymbolRefAttr getDefaultTargetAttr() {
215-
return getModuleNamesAttr()[0].cast<FlatSymbolRefAttr>();
215+
return llvm::cast<FlatSymbolRefAttr>(getModuleNamesAttr()[0]);
216216
}
217217

218218
/// Return the name of the option group.
219219
StringAttr getOptionNameAttr() {
220-
return getCaseNames()[0].cast<SymbolRefAttr>().getRootReference();
220+
return llvm::cast<SymbolRefAttr>(getCaseNames()[0]).getRootReference();
221221
}
222222

223223
/// Return the target for an option or the default if none specified.

‎include/circt/Dialect/FIRRTL/FIRRTLOpInterfaces.td

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
9292
InterfaceMethod<"Get a port name",
9393
"StringAttr", "getPortNameAttr", (ins "size_t":$portIndex), [{}],
9494
/*defaultImplementation=*/[{
95-
return $_op.getPortNames()[portIndex].template cast<StringAttr>();
95+
return llvm::cast<StringAttr>($_op.getPortNames()[portIndex]);
9696
}]>,
9797

9898
InterfaceMethod<"Get a port name",
@@ -121,7 +121,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
121121
InterfaceMethod<"Get a port type",
122122
"TypeAttr", "getPortTypeAttr", (ins "size_t":$portIndex), [{}],
123123
/*defaultImplementation=*/[{
124-
return $_op.getPortTypes()[portIndex].template cast<TypeAttr>();
124+
return llvm::cast<TypeAttr>($_op.getPortTypes()[portIndex]);
125125
}]>,
126126

127127
InterfaceMethod<"Get a port type",
@@ -154,7 +154,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
154154
auto annos = $_op.getPortAnnotationsAttr();
155155
if (annos.empty())
156156
return annos; // annos already is an empty array
157-
return annos[portIndex].template cast<ArrayAttr>();
157+
return llvm::cast<ArrayAttr>(annos[portIndex]);
158158
}]>,
159159

160160
InterfaceMethod<"Get a port's annotations",
@@ -192,16 +192,16 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
192192
"bool", "hasPortSymbolAttr", (ins "size_t":$portIndex), [{}], [{
193193
auto syms = $_op.getPortSymbols();
194194
return (!syms.empty() &&
195-
!syms[portIndex].template cast<hw::InnerSymAttr>().empty());
195+
!llvm::cast<hw::InnerSymAttr>(syms[portIndex]).empty());
196196
}]>,
197197

198198
InterfaceMethod<"Get the port symbol attribute",
199199
"circt::hw::InnerSymAttr", "getPortSymbolAttr", (ins "size_t":$portIndex), [{}], [{
200200
auto syms = $_op.getPortSymbols();
201201
if (syms.empty() ||
202-
syms[portIndex].template cast<hw::InnerSymAttr>().empty())
202+
llvm::cast<hw::InnerSymAttr>(syms[portIndex]).empty())
203203
return hw::InnerSymAttr();
204-
return syms[portIndex].template cast<hw::InnerSymAttr>();
204+
return llvm::cast<hw::InnerSymAttr>(syms[portIndex]);
205205
}]>,
206206

207207
// Setters
@@ -279,8 +279,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
279279
InterfaceMethod<"Get a port's location attribute",
280280
"LocationAttr", "getPortLocationAttr", (ins "size_t":$portIndex), [{}],
281281
/*defaultImplementation=*/[{
282-
return $_op.getPortLocationsAttr()[portIndex].
283-
template cast<LocationAttr>();
282+
return llvm::cast<LocationAttr>($_op.getPortLocationsAttr()[portIndex]);
284283
}]>,
285284

286285
InterfaceMethod<"Get a port's location",

‎include/circt/Dialect/FIRRTL/FIRRTLTypes.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ def FIRRTLType : FIRRTLDialectTypeHelper<"FIRRTLType", "FIRRTLType", [{
3939
}]>;
4040

4141
def FIRRTLBaseType : FIRRTLDialectType<
42-
CPred<"$_self.isa<FIRRTLBaseType>()">,
42+
CPred<"llvm::isa<FIRRTLBaseType>($_self)">,
4343
"a base type", "::circt::firrtl::FIRRTLBaseType", [{
4444
A base FIRRTL type, such as a clock, integer, or wire.
4545

‎lib/CAPI/Dialect/CHIRRTL.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ MLIR_DEFINE_CAPI_DIALECT_REGISTRATION(CHIRRTL, chirrtl,
2828

2929
MlirType chirrtlTypeGetCMemory(MlirContext ctx, MlirType elementType,
3030
uint64_t numElements) {
31-
auto baseType = unwrap(elementType).cast<firrtl::FIRRTLBaseType>();
31+
auto baseType = cast<firrtl::FIRRTLBaseType>(unwrap(elementType));
3232
assert(baseType && "element must be base type");
3333

3434
return wrap(CMemoryType::get(unwrap(ctx), baseType, numElements));

‎lib/CAPI/Dialect/FIRRTL.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -58,14 +58,14 @@ MlirType firrtlTypeGetAnalog(MlirContext ctx, int32_t width) {
5858
}
5959

6060
MlirType firrtlTypeGetVector(MlirContext ctx, MlirType element, size_t count) {
61-
auto baseType = unwrap(element).cast<FIRRTLBaseType>();
61+
auto baseType = cast<FIRRTLBaseType>(unwrap(element));
6262
assert(baseType && "element must be base type");
6363

6464
return wrap(FVectorType::get(baseType, count));
6565
}
6666

6767
bool firrtlTypeIsAOpenBundle(MlirType type) {
68-
return unwrap(type).isa<OpenBundleType>();
68+
return isa<OpenBundleType>(unwrap(type));
6969
}
7070

7171
MlirType firrtlTypeGetBundle(MlirContext ctx, size_t count,
@@ -77,7 +77,7 @@ MlirType firrtlTypeGetBundle(MlirContext ctx, size_t count,
7777

7878
for (size_t i = 0; i < count; i++) {
7979
auto field = fields[i];
80-
auto type = unwrap(field.type).cast<FIRRTLType>();
80+
auto type = cast<FIRRTLType>(unwrap(field.type));
8181
bundleFields.emplace_back(unwrap(field.name), field.isFlip, type);
8282
bundleCompatible &= isa<BundleType::ElementType>(type);
8383
}
@@ -96,9 +96,9 @@ MlirType firrtlTypeGetBundle(MlirContext ctx, size_t count,
9696

9797
unsigned firrtlTypeGetBundleFieldIndex(MlirType type, MlirStringRef fieldName) {
9898
std::optional<unsigned> fieldIndex;
99-
if (auto bundleType = unwrap(type).dyn_cast<BundleType>()) {
99+
if (auto bundleType = dyn_cast<BundleType>(unwrap(type))) {
100100
fieldIndex = bundleType.getElementIndex(unwrap(fieldName));
101-
} else if (auto bundleType = unwrap(type).dyn_cast<OpenBundleType>()) {
101+
} else if (auto bundleType = dyn_cast<OpenBundleType>(unwrap(type))) {
102102
fieldIndex = bundleType.getElementIndex(unwrap(fieldName));
103103
} else {
104104
llvm_unreachable("must be a bundle type");
@@ -108,7 +108,7 @@ unsigned firrtlTypeGetBundleFieldIndex(MlirType type, MlirStringRef fieldName) {
108108
}
109109

110110
MlirType firrtlTypeGetRef(MlirType target, bool forceable) {
111-
auto baseType = unwrap(target).dyn_cast<FIRRTLBaseType>();
111+
auto baseType = dyn_cast<FIRRTLBaseType>(unwrap(target));
112112
assert(baseType && "target must be base type");
113113

114114
return wrap(RefType::get(baseType, forceable));
@@ -139,7 +139,7 @@ MlirType firrtlTypeGetPath(MlirContext ctx) {
139139
}
140140

141141
MlirType firrtlTypeGetList(MlirContext ctx, MlirType elementType) {
142-
auto type = unwrap(elementType).dyn_cast<PropertyType>();
142+
auto type = dyn_cast<PropertyType>(unwrap(elementType));
143143
assert(type && "element must be property type");
144144

145145
return wrap(ListType::get(unwrap(ctx), type));
@@ -148,7 +148,7 @@ MlirType firrtlTypeGetList(MlirContext ctx, MlirType elementType) {
148148
MlirType firrtlTypeGetClass(MlirContext ctx, MlirAttribute name,
149149
size_t numberOfElements,
150150
const FIRRTLClassElement *elements) {
151-
auto nameSymbol = unwrap(name).dyn_cast<FlatSymbolRefAttr>();
151+
auto nameSymbol = dyn_cast<FlatSymbolRefAttr>(unwrap(name));
152152
assert(nameSymbol && "name must be FlatSymbolRefAttr");
153153

154154
SmallVector<ClassElement, 4> classElements;

‎lib/Conversion/FIRRTLToHW/LowerToHW.cpp

Lines changed: 20 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ static Value castToFIRRTLType(Value val, Type type,
144144
static Value castFromFIRRTLType(Value val, Type type,
145145
ImplicitLocOpBuilder &builder) {
146146

147-
if (hw::StructType structTy = type.dyn_cast<hw::StructType>()) {
147+
if (hw::StructType structTy = dyn_cast<hw::StructType>(type)) {
148148
// Strip off Flip type if needed.
149149
val =
150150
builder
@@ -1217,7 +1217,7 @@ tryEliminatingConnectsToValue(Value flipValue, Operation *insertPoint,
12171217
auto connectSrc = connectOp->getOperand(1);
12181218

12191219
// Directly forward foreign types.
1220-
if (!connectSrc.getType().isa<FIRRTLType>()) {
1220+
if (!isa<FIRRTLType>(connectSrc.getType())) {
12211221
connectOp->erase();
12221222
return connectSrc;
12231223
}
@@ -2007,12 +2007,12 @@ Value FIRRTLLowering::getOrCreateZConstant(Type type) {
20072007
/// does not implicitly read from them.
20082008
Value FIRRTLLowering::getPossiblyInoutLoweredValue(Value value) {
20092009
// Block arguments are considered lowered.
2010-
if (value.isa<BlockArgument>())
2010+
if (isa<BlockArgument>(value))
20112011
return value;
20122012

20132013
// If we lowered this value, then return the lowered value, otherwise fail.
20142014
if (auto lowering = valueMapping.lookup(value)) {
2015-
assert(!lowering.getType().isa<FIRRTLType>() &&
2015+
assert(!isa<FIRRTLType>(lowering.getType()) &&
20162016
"Lowered value should be a non-FIRRTL value");
20172017
return lowering;
20182018
}
@@ -2029,7 +2029,7 @@ Value FIRRTLLowering::getLoweredValue(Value value) {
20292029

20302030
// If we got an inout value, implicitly read it. FIRRTL allows direct use
20312031
// of wires and other things that lower to inout type.
2032-
if (result.getType().isa<hw::InOutType>())
2032+
if (isa<hw::InOutType>(result.getType()))
20332033
return getReadValue(result);
20342034

20352035
return result;
@@ -2189,7 +2189,7 @@ Value FIRRTLLowering::getLoweredAndExtendedValue(Value value, Type destType) {
21892189
}
21902190
}
21912191
// Aggregates values
2192-
if (result.getType().isa<hw::ArrayType, hw::StructType>()) {
2192+
if (isa<hw::ArrayType, hw::StructType>(result.getType())) {
21932193
// Types already match.
21942194
if (destType == value.getType())
21952195
return result;
@@ -2200,7 +2200,7 @@ Value FIRRTLLowering::getLoweredAndExtendedValue(Value value, Type destType) {
22002200
/* allowTruncate */ false);
22012201
}
22022202

2203-
if (result.getType().isa<seq::ClockType>()) {
2203+
if (isa<seq::ClockType>(result.getType())) {
22042204
// Types already match.
22052205
if (destType == value.getType())
22062206
return result;
@@ -2267,7 +2267,7 @@ Value FIRRTLLowering::getLoweredAndExtOrTruncValue(Value value, Type destType) {
22672267
}
22682268

22692269
// Aggregates values
2270-
if (result.getType().isa<hw::ArrayType, hw::StructType>()) {
2270+
if (isa<hw::ArrayType, hw::StructType>(result.getType())) {
22712271
// Types already match.
22722272
if (destType == value.getType())
22732273
return result;
@@ -2572,7 +2572,7 @@ LogicalResult FIRRTLLowering::emitGuards(Location loc,
25722572
emit();
25732573
return success();
25742574
}
2575-
auto guard = guards[0].dyn_cast<StringAttr>();
2575+
auto guard = dyn_cast<StringAttr>(guards[0]);
25762576
if (!guard)
25772577
return mlir::emitError(loc,
25782578
"elements in `guards` array must be `StringAttr`");
@@ -2694,7 +2694,7 @@ LogicalResult FIRRTLLowering::visitExpr(ConstantOp op) {
26942694

26952695
LogicalResult FIRRTLLowering::visitExpr(SpecialConstantOp op) {
26962696
Value cst;
2697-
if (op.getType().isa<ClockType>()) {
2697+
if (isa<ClockType>(op.getType())) {
26982698
cst = getOrCreateClockConstant(op.getValue() ? seq::ClockConst::High
26992699
: seq::ClockConst::Low);
27002700
} else {
@@ -2713,7 +2713,7 @@ FailureOr<Value> FIRRTLLowering::lowerSubindex(SubindexOp op, Value input) {
27132713
// If the input has an inout type, we need to lower to ArrayIndexInOutOp;
27142714
// otherwise hw::ArrayGetOp.
27152715
Value result;
2716-
if (input.getType().isa<sv::InOutType>())
2716+
if (isa<sv::InOutType>(input.getType()))
27172717
result = builder.createOrFold<sv::ArrayIndexInOutOp>(input, iIdx);
27182718
else
27192719
result = builder.createOrFold<hw::ArrayGetOp>(input, iIdx);
@@ -2736,7 +2736,7 @@ FailureOr<Value> FIRRTLLowering::lowerSubaccess(SubaccessOp op, Value input) {
27362736
// If the input has an inout type, we need to lower to ArrayIndexInOutOp;
27372737
// otherwise, lower the op to array indexing.
27382738
Value result;
2739-
if (input.getType().isa<sv::InOutType>())
2739+
if (isa<sv::InOutType>(input.getType()))
27402740
result = builder.createOrFold<sv::ArrayIndexInOutOp>(input, valueIdx);
27412741
else
27422742
result = createArrayIndexing(input, valueIdx);
@@ -2756,7 +2756,7 @@ FailureOr<Value> FIRRTLLowering::lowerSubfield(SubfieldOp op, Value input) {
27562756
auto field = firrtl::type_cast<BundleType>(op.getInput().getType())
27572757
.getElementName(op.getFieldIndex());
27582758
Value result;
2759-
if (input.getType().isa<sv::InOutType>())
2759+
if (isa<sv::InOutType>(input.getType()))
27602760
result = builder.createOrFold<sv::StructFieldInOutOp>(input, field);
27612761
else
27622762
result = builder.createOrFold<hw::StructExtractOp>(input, field);
@@ -3098,8 +3098,7 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) {
30983098

30993099
auto addInput = [&](StringRef field, Value backedge) {
31003100
for (auto a : getAllFieldAccesses(op.getResult(i), field)) {
3101-
if (a.getType()
3102-
.cast<FIRRTLBaseType>()
3101+
if (cast<FIRRTLBaseType>(a.getType())
31033102
.getPassiveType()
31043103
.getBitWidthOrSentinel() > 0)
31053104
(void)setLowering(a, backedge);
@@ -3384,7 +3383,7 @@ LogicalResult FIRRTLLowering::visitUnrealizedConversionCast(
33843383
LogicalResult FIRRTLLowering::visitExpr(HWStructCastOp op) {
33853384
// Conversions from hw struct types to FIRRTL types are lowered as the
33863385
// input operand.
3387-
if (auto opStructType = op.getOperand().getType().dyn_cast<hw::StructType>())
3386+
if (auto opStructType = dyn_cast<hw::StructType>(op.getOperand().getType()))
33883387
return setLowering(op, op.getOperand());
33893388

33903389
// Otherwise must be a conversion from FIRRTL bundle type to hw struct
@@ -3910,7 +3909,7 @@ LogicalResult FIRRTLLowering::visitExpr(MuxPrimOp op) {
39103909
if (!cond || !ifTrue || !ifFalse)
39113910
return failure();
39123911

3913-
if (op.getType().isa<ClockType>())
3912+
if (isa<ClockType>(op.getType()))
39143913
return setLoweringTo<seq::ClockMuxOp>(op, cond, ifTrue, ifFalse);
39153914
return setLoweringTo<comb::MuxOp>(op, ifTrue.getType(), cond, ifTrue, ifFalse,
39163915
true);
@@ -4156,7 +4155,7 @@ LogicalResult FIRRTLLowering::visitStmt(ConnectOp op) {
41564155
if (updateIfBackedge(destVal, srcVal))
41574156
return success();
41584157

4159-
if (!destVal.getType().isa<hw::InOutType>())
4158+
if (!isa<hw::InOutType>(destVal.getType()))
41604159
return op.emitError("destination isn't an inout type");
41614160

41624161
builder.create<sv::AssignOp>(destVal, srcVal);
@@ -4184,7 +4183,7 @@ LogicalResult FIRRTLLowering::visitStmt(StrictConnectOp op) {
41844183
if (updateIfBackedge(destVal, srcVal))
41854184
return success();
41864185

4187-
if (!destVal.getType().isa<hw::InOutType>())
4186+
if (!isa<hw::InOutType>(destVal.getType()))
41884187
return op.emitError("destination isn't an inout type");
41894188

41904189
builder.create<sv::AssignOp>(destVal, srcVal);
@@ -4200,7 +4199,7 @@ LogicalResult FIRRTLLowering::visitStmt(ForceOp op) {
42004199
if (!destVal)
42014200
return failure();
42024201

4203-
if (!destVal.getType().isa<hw::InOutType>())
4202+
if (!isa<hw::InOutType>(destVal.getType()))
42044203
return op.emitError("destination isn't an inout type");
42054204

42064205
// #ifndef SYNTHESIS
@@ -4646,7 +4645,7 @@ LogicalResult FIRRTLLowering::visitStmt(AttachOp op) {
46464645
continue;
46474646
}
46484647

4649-
if (!inoutValues.back().getType().isa<hw::InOutType>())
4648+
if (!isa<hw::InOutType>(inoutValues.back().getType()))
46504649
return op.emitError("operand isn't an inout type");
46514650
}
46524651

‎lib/Dialect/FIRRTL/FIRRTLAnnotationHelper.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -733,7 +733,7 @@ LogicalResult circt::firrtl::applyGCTMemTaps(const AnnoPathValue &target,
733733
if (!tapsAttr || tapsAttr.empty())
734734
return mlir::emitError(loc, "sink must have at least one entry");
735735

736-
auto tap = tapsAttr[0].dyn_cast_or_null<StringAttr>();
736+
auto tap = dyn_cast_or_null<StringAttr>(tapsAttr[0]);
737737
if (!tap) {
738738
return mlir::emitError(
739739
loc, "Annotation '" + Twine(memTapClass) +

‎lib/Dialect/FIRRTL/FIRRTLAnnotations.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -412,7 +412,7 @@ bool AnnotationSet::removeAnnotations(Operation *op, StringRef className) {
412412
bool AnnotationSet::removePortAnnotations(
413413
Operation *module,
414414
llvm::function_ref<bool(unsigned, Annotation)> predicate) {
415-
auto ports = module->getAttr("portAnnotations").dyn_cast_or_null<ArrayAttr>();
415+
auto ports = dyn_cast_or_null<ArrayAttr>(module->getAttr("portAnnotations"));
416416
if (!ports || ports.empty())
417417
return false;
418418

‎lib/Dialect/FIRRTL/FIRRTLFolds.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -228,9 +228,9 @@ static Attribute constFoldFIRRTLBinaryOp(
228228
type_cast<IntType>(op->getOperand(0).getType()).getWidthOrSentinel();
229229
auto rhsWidth =
230230
type_cast<IntType>(op->getOperand(1).getType()).getWidthOrSentinel();
231-
if (auto lhs = operands[0].dyn_cast_or_null<IntegerAttr>())
231+
if (auto lhs = dyn_cast_or_null<IntegerAttr>(operands[0]))
232232
lhsWidth = std::max<int32_t>(lhsWidth, lhs.getValue().getBitWidth());
233-
if (auto rhs = operands[1].dyn_cast_or_null<IntegerAttr>())
233+
if (auto rhs = dyn_cast_or_null<IntegerAttr>(operands[1]))
234234
rhsWidth = std::max<int32_t>(rhsWidth, rhs.getValue().getBitWidth());
235235

236236
// Compares extend the operands to the widest of the operand types, not to the
@@ -465,7 +465,7 @@ OpFoldResult DivPrimOp::fold(FoldAdaptor adaptor) {
465465
/// UInt division by one returns the numerator. SInt division can't
466466
/// be folded here because it increases the return type bitwidth by
467467
/// one and requires sign extension (a new op).
468-
if (auto rhsCst = adaptor.getRhs().dyn_cast_or_null<IntegerAttr>())
468+
if (auto rhsCst = dyn_cast_or_null<IntegerAttr>(adaptor.getRhs()))
469469
if (rhsCst.getValue().isOne() && getLhs().getType() == getType())
470470
return getLhs();
471471

@@ -2126,14 +2126,14 @@ void SubindexOp::getCanonicalizationPatterns(RewritePatternSet &results,
21262126
}
21272127

21282128
OpFoldResult SubindexOp::fold(FoldAdaptor adaptor) {
2129-
auto attr = adaptor.getInput().dyn_cast_or_null<ArrayAttr>();
2129+
auto attr = dyn_cast_or_null<ArrayAttr>(adaptor.getInput());
21302130
if (!attr)
21312131
return {};
21322132
return attr[getIndex()];
21332133
}
21342134

21352135
OpFoldResult SubfieldOp::fold(FoldAdaptor adaptor) {
2136-
auto attr = adaptor.getInput().dyn_cast_or_null<ArrayAttr>();
2136+
auto attr = dyn_cast_or_null<ArrayAttr>(adaptor.getInput());
21372137
if (!attr)
21382138
return {};
21392139
auto index = getFieldIndex();

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