Name		Name	Last commit message	Last commit date
parent directory ..
README.md		README.md
alu.sv		alu.sv
dmem.sv		dmem.sv
imem.sv		imem.sv
regfile.sv		regfile.sv
tb_alu.sv		tb_alu.sv
tb_dmem.sv		tb_dmem.sv
tb_imem.sv		tb_imem.sv
tb_regfile.sv		tb_regfile.sv

README.md

Lab 2: Datapath Element Design

Design

Goal

Complete the design of the datapath elements supporting 7 RV64I instructions: ld, sd, add, sub, or, and, beq`

Implementation

imem.sv (Instruction Memory)
regfile.sv (Register File)
alu.sv (Arithmetic Logic Unit)
dmem.sv (Data Memory)

Testbench

Goal

Making testbench codes for the above designs

Implementation

Result