Exporting a top-module in Verilog containing the instantiations of the sub-circuits

[MortezaRezaalipour]

I partitioned a small circuit (a 2-bit Ripple-Carry Adder named "adder_2") into two subcircuits, and two subcircuits appeared with the names "adder_2_0.v" and "adder_2_1.v".
I wondered if there is a way to export a merged top-level module in Verilog format in which the two subcircuits are instantiated.
More precisely, what I'm looking for is the following:

#===================================================
module top_adder_2_merged_after_partitioning(inputs, outputs);

inputs...
outputs...
wires...

adder_2_0 U0(inputs|wires, outputs|wires)
adder_2_1 U1(inputs|wires, outputs|wires)
#===================================================

If there is no such command, is there a way (maybe through other commands such as "partition_detail") to export the information on how to connect the two subcircuits to create the desired top-level module?