@@ -3256,22 +3256,22 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
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return EmitZTInstr(MI, BB, AArch64::MOVT_TIZ, /*Op0IsDef=*/true);
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case AArch64::AUTx16x17:
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- fixupBlendComponents (MI, BB, MI.getOperand(1), MI.getOperand(2),
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- &AArch64::GPR64noipRegClass);
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+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(1), MI.getOperand(2),
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+ &AArch64::GPR64noipRegClass);
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return BB;
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case AArch64::AUTxMxN:
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- fixupBlendComponents (MI, BB, MI.getOperand(4), MI.getOperand(5),
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- &AArch64::GPR64noipRegClass);
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+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(4), MI.getOperand(5),
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+ &AArch64::GPR64noipRegClass);
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return BB;
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case AArch64::PAC:
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fixupPtrauthDiscriminator(MI, BB, MI.getOperand(3), MI.getOperand(4),
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&AArch64::GPR64noipRegClass);
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return BB;
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case AArch64::AUTPAC:
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- fixupBlendComponents (MI, BB, MI.getOperand(1), MI.getOperand(2),
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- &AArch64::GPR64noipRegClass);
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- fixupBlendComponents (MI, BB, MI.getOperand(4), MI.getOperand(5),
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- &AArch64::GPR64noipRegClass);
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+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(1), MI.getOperand(2),
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+ &AArch64::GPR64noipRegClass);
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+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(4), MI.getOperand(5),
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+ &AArch64::GPR64noipRegClass);
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return BB;
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}
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}
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