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topperctopperc
authoredJun 19, 2025··
[RISCV] Save vector registers in interrupt handler. (#143808)
Corresponding gcc bug report https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110665 The generated code is pretty awful.
·
llvmorg-22-initllvmorg-21.1.0-rc1
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lines changed

4 files changed

+7360
-2
lines changed
 

‎llvm/lib/Target/RISCV/RISCVCallingConv.td‎

Lines changed: 28 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,14 +56,40 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
5656
def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
5757
(sequence "F%u_D", 0, 31))>;
5858

59+
// Same as CSR_Interrupt, but including all vector registers.
60+
def CSR_XLEN_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
61+
(sequence "V%u", 0, 31))>;
62+
63+
// Same as CSR_Interrupt, but including all 32-bit FP registers and all vector
64+
// registers.
65+
def CSR_XLEN_F32_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F32_Interrupt,
66+
(sequence "V%u", 0, 31))>;
67+
68+
// Same as CSR_Interrupt, but including all 64-bit FP registers and all vector
69+
// registers.
70+
def CSR_XLEN_F64_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F64_Interrupt,
71+
(sequence "V%u", 0, 31))>;
72+
5973
// Same as CSR_Interrupt, but excluding X16-X31.
6074
def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt,
6175
(sequence "X%u", 16, 31))>;
6276

6377
// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31.
6478
def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt,
65-
(sequence "X%u", 16, 31))>;
79+
(sequence "X%u", 16, 31))>;
6680

6781
// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31.
6882
def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt,
69-
(sequence "X%u", 16, 31))>;
83+
(sequence "X%u", 16, 31))>;
84+
85+
// Same as CSR_XLEN_V_Interrupt, but excluding X16-X31.
86+
def CSR_XLEN_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_V_Interrupt,
87+
(sequence "X%u", 16, 31))>;
88+
89+
// Same as CSR_XLEN_F32_V_Interrupt, but excluding X16-X31.
90+
def CSR_XLEN_F32_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_V_Interrupt,
91+
(sequence "X%u", 16, 31))>;
92+
93+
// Same as CSR_XLEN_F64_V_Interrupt, but excluding X16-X31.
94+
def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_V_Interrupt,
95+
(sequence "X%u", 16, 31))>;

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,16 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
6969
if (MF->getFunction().getCallingConv() == CallingConv::GHC)
7070
return CSR_NoRegs_SaveList;
7171
if (MF->getFunction().hasFnAttribute("interrupt")) {
72+
if (Subtarget.hasVInstructions()) {
73+
if (Subtarget.hasStdExtD())
74+
return Subtarget.hasStdExtE() ? CSR_XLEN_F64_V_Interrupt_RVE_SaveList
75+
: CSR_XLEN_F64_V_Interrupt_SaveList;
76+
if (Subtarget.hasStdExtF())
77+
return Subtarget.hasStdExtE() ? CSR_XLEN_F32_V_Interrupt_RVE_SaveList
78+
: CSR_XLEN_F32_V_Interrupt_SaveList;
79+
return Subtarget.hasStdExtE() ? CSR_XLEN_V_Interrupt_RVE_SaveList
80+
: CSR_XLEN_V_Interrupt_SaveList;
81+
}
7282
if (Subtarget.hasStdExtD())
7383
return Subtarget.hasStdExtE() ? CSR_XLEN_F64_Interrupt_RVE_SaveList
7484
: CSR_XLEN_F64_Interrupt_SaveList;

‎llvm/test/CodeGen/RISCV/interrupt-attr.ll‎

Lines changed: 6820 additions & 0 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll‎

Lines changed: 502 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,502 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple riscv32-unknown-elf -mattr=+zve32x,+zvl128b -o - %s \
3+
; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
4+
5+
@a = external global <4 x i32>
6+
@b = external global <4 x i32>
7+
@c = external global <4 x i32>
8+
9+
define void @foo_lmul1() nounwind #0 {
10+
; CHECK-RV32-LABEL: foo_lmul1:
11+
; CHECK-RV32: # %bb.0:
12+
; CHECK-RV32-NEXT: addi sp, sp, -32
13+
; CHECK-RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
14+
; CHECK-RV32-NEXT: csrr a0, vlenb
15+
; CHECK-RV32-NEXT: slli a0, a0, 1
16+
; CHECK-RV32-NEXT: sub sp, sp, a0
17+
; CHECK-RV32-NEXT: csrr a0, vlenb
18+
; CHECK-RV32-NEXT: add a0, sp, a0
19+
; CHECK-RV32-NEXT: addi a0, a0, 16
20+
; CHECK-RV32-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
21+
; CHECK-RV32-NEXT: addi a0, sp, 16
22+
; CHECK-RV32-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
23+
; CHECK-RV32-NEXT: lui a0, %hi(a)
24+
; CHECK-RV32-NEXT: addi a0, a0, %lo(a)
25+
; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
26+
; CHECK-RV32-NEXT: vle32.v v8, (a0)
27+
; CHECK-RV32-NEXT: lui a0, %hi(b)
28+
; CHECK-RV32-NEXT: addi a0, a0, %lo(b)
29+
; CHECK-RV32-NEXT: vle32.v v9, (a0)
30+
; CHECK-RV32-NEXT: vadd.vv v8, v9, v8
31+
; CHECK-RV32-NEXT: lui a0, %hi(c)
32+
; CHECK-RV32-NEXT: addi a0, a0, %lo(c)
33+
; CHECK-RV32-NEXT: vse32.v v8, (a0)
34+
; CHECK-RV32-NEXT: csrr a0, vlenb
35+
; CHECK-RV32-NEXT: add a0, sp, a0
36+
; CHECK-RV32-NEXT: addi a0, a0, 16
37+
; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
38+
; CHECK-RV32-NEXT: addi a0, sp, 16
39+
; CHECK-RV32-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
40+
; CHECK-RV32-NEXT: csrr a0, vlenb
41+
; CHECK-RV32-NEXT: slli a0, a0, 1
42+
; CHECK-RV32-NEXT: add sp, sp, a0
43+
; CHECK-RV32-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
44+
; CHECK-RV32-NEXT: addi sp, sp, 32
45+
; CHECK-RV32-NEXT: mret
46+
%1 = load <4 x i32>, ptr @a
47+
%2 = load <4 x i32>, ptr @b
48+
%add = add nsw <4 x i32> %2, %1
49+
store <4 x i32> %add, ptr @c
50+
ret void
51+
}
52+
53+
@d = external global <8 x i32>
54+
@e = external global <8 x i32>
55+
@f = external global <8 x i32>
56+
57+
define void @foo_lmul2() nounwind #0 {
58+
; CHECK-RV32-LABEL: foo_lmul2:
59+
; CHECK-RV32: # %bb.0:
60+
; CHECK-RV32-NEXT: addi sp, sp, -32
61+
; CHECK-RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
62+
; CHECK-RV32-NEXT: csrr a0, vlenb
63+
; CHECK-RV32-NEXT: slli a0, a0, 2
64+
; CHECK-RV32-NEXT: sub sp, sp, a0
65+
; CHECK-RV32-NEXT: csrr a0, vlenb
66+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
67+
; CHECK-RV32-NEXT: slli a1, a0, 1
68+
; CHECK-RV32-NEXT: add a0, a1, a0
69+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
70+
; CHECK-RV32-NEXT: add a0, sp, a0
71+
; CHECK-RV32-NEXT: addi a0, a0, 16
72+
; CHECK-RV32-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
73+
; CHECK-RV32-NEXT: csrr a0, vlenb
74+
; CHECK-RV32-NEXT: slli a0, a0, 1
75+
; CHECK-RV32-NEXT: add a0, sp, a0
76+
; CHECK-RV32-NEXT: addi a0, a0, 16
77+
; CHECK-RV32-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
78+
; CHECK-RV32-NEXT: csrr a0, vlenb
79+
; CHECK-RV32-NEXT: add a0, sp, a0
80+
; CHECK-RV32-NEXT: addi a0, a0, 16
81+
; CHECK-RV32-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
82+
; CHECK-RV32-NEXT: addi a0, sp, 16
83+
; CHECK-RV32-NEXT: vs1r.v v11, (a0) # vscale x 8-byte Folded Spill
84+
; CHECK-RV32-NEXT: lui a0, %hi(d)
85+
; CHECK-RV32-NEXT: addi a0, a0, %lo(d)
86+
; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
87+
; CHECK-RV32-NEXT: vle32.v v8, (a0)
88+
; CHECK-RV32-NEXT: lui a0, %hi(e)
89+
; CHECK-RV32-NEXT: addi a0, a0, %lo(e)
90+
; CHECK-RV32-NEXT: vle32.v v10, (a0)
91+
; CHECK-RV32-NEXT: vadd.vv v8, v10, v8
92+
; CHECK-RV32-NEXT: lui a0, %hi(f)
93+
; CHECK-RV32-NEXT: addi a0, a0, %lo(f)
94+
; CHECK-RV32-NEXT: vse32.v v8, (a0)
95+
; CHECK-RV32-NEXT: csrr a0, vlenb
96+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
97+
; CHECK-RV32-NEXT: slli a1, a0, 1
98+
; CHECK-RV32-NEXT: add a0, a1, a0
99+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
100+
; CHECK-RV32-NEXT: add a0, sp, a0
101+
; CHECK-RV32-NEXT: addi a0, a0, 16
102+
; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
103+
; CHECK-RV32-NEXT: csrr a0, vlenb
104+
; CHECK-RV32-NEXT: slli a0, a0, 1
105+
; CHECK-RV32-NEXT: add a0, sp, a0
106+
; CHECK-RV32-NEXT: addi a0, a0, 16
107+
; CHECK-RV32-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
108+
; CHECK-RV32-NEXT: csrr a0, vlenb
109+
; CHECK-RV32-NEXT: add a0, sp, a0
110+
; CHECK-RV32-NEXT: addi a0, a0, 16
111+
; CHECK-RV32-NEXT: vl1r.v v10, (a0) # vscale x 8-byte Folded Reload
112+
; CHECK-RV32-NEXT: addi a0, sp, 16
113+
; CHECK-RV32-NEXT: vl1r.v v11, (a0) # vscale x 8-byte Folded Reload
114+
; CHECK-RV32-NEXT: csrr a0, vlenb
115+
; CHECK-RV32-NEXT: slli a0, a0, 2
116+
; CHECK-RV32-NEXT: add sp, sp, a0
117+
; CHECK-RV32-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
118+
; CHECK-RV32-NEXT: addi sp, sp, 32
119+
; CHECK-RV32-NEXT: mret
120+
%1 = load <8 x i32>, ptr @d
121+
%2 = load <8 x i32>, ptr @e
122+
%add = add nsw <8 x i32> %2, %1
123+
store <8 x i32> %add, ptr @f
124+
ret void
125+
}
126+
127+
@g = external global <16 x i32>
128+
@h = external global <16 x i32>
129+
@i = external global <16 x i32>
130+
131+
define void @foo_lmul4() nounwind #0 {
132+
; CHECK-RV32-LABEL: foo_lmul4:
133+
; CHECK-RV32: # %bb.0:
134+
; CHECK-RV32-NEXT: addi sp, sp, -32
135+
; CHECK-RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
136+
; CHECK-RV32-NEXT: csrr a0, vlenb
137+
; CHECK-RV32-NEXT: slli a0, a0, 3
138+
; CHECK-RV32-NEXT: sub sp, sp, a0
139+
; CHECK-RV32-NEXT: csrr a0, vlenb
140+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
141+
; CHECK-RV32-NEXT: slli a1, a0, 3
142+
; CHECK-RV32-NEXT: sub a0, a1, a0
143+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
144+
; CHECK-RV32-NEXT: add a0, sp, a0
145+
; CHECK-RV32-NEXT: addi a0, a0, 16
146+
; CHECK-RV32-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
147+
; CHECK-RV32-NEXT: csrr a0, vlenb
148+
; CHECK-RV32-NEXT: slli a0, a0, 1
149+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
150+
; CHECK-RV32-NEXT: mv a1, a0
151+
; CHECK-RV32-NEXT: slli a0, a0, 1
152+
; CHECK-RV32-NEXT: add a0, a0, a1
153+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
154+
; CHECK-RV32-NEXT: add a0, sp, a0
155+
; CHECK-RV32-NEXT: addi a0, a0, 16
156+
; CHECK-RV32-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
157+
; CHECK-RV32-NEXT: csrr a0, vlenb
158+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
159+
; CHECK-RV32-NEXT: slli a1, a0, 2
160+
; CHECK-RV32-NEXT: add a0, a1, a0
161+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
162+
; CHECK-RV32-NEXT: add a0, sp, a0
163+
; CHECK-RV32-NEXT: addi a0, a0, 16
164+
; CHECK-RV32-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
165+
; CHECK-RV32-NEXT: csrr a0, vlenb
166+
; CHECK-RV32-NEXT: slli a0, a0, 2
167+
; CHECK-RV32-NEXT: add a0, sp, a0
168+
; CHECK-RV32-NEXT: addi a0, a0, 16
169+
; CHECK-RV32-NEXT: vs1r.v v11, (a0) # vscale x 8-byte Folded Spill
170+
; CHECK-RV32-NEXT: csrr a0, vlenb
171+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
172+
; CHECK-RV32-NEXT: slli a1, a0, 1
173+
; CHECK-RV32-NEXT: add a0, a1, a0
174+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
175+
; CHECK-RV32-NEXT: add a0, sp, a0
176+
; CHECK-RV32-NEXT: addi a0, a0, 16
177+
; CHECK-RV32-NEXT: vs1r.v v12, (a0) # vscale x 8-byte Folded Spill
178+
; CHECK-RV32-NEXT: csrr a0, vlenb
179+
; CHECK-RV32-NEXT: slli a0, a0, 1
180+
; CHECK-RV32-NEXT: add a0, sp, a0
181+
; CHECK-RV32-NEXT: addi a0, a0, 16
182+
; CHECK-RV32-NEXT: vs1r.v v13, (a0) # vscale x 8-byte Folded Spill
183+
; CHECK-RV32-NEXT: csrr a0, vlenb
184+
; CHECK-RV32-NEXT: add a0, sp, a0
185+
; CHECK-RV32-NEXT: addi a0, a0, 16
186+
; CHECK-RV32-NEXT: vs1r.v v14, (a0) # vscale x 8-byte Folded Spill
187+
; CHECK-RV32-NEXT: addi a0, sp, 16
188+
; CHECK-RV32-NEXT: vs1r.v v15, (a0) # vscale x 8-byte Folded Spill
189+
; CHECK-RV32-NEXT: lui a0, %hi(g)
190+
; CHECK-RV32-NEXT: addi a0, a0, %lo(g)
191+
; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
192+
; CHECK-RV32-NEXT: vle32.v v8, (a0)
193+
; CHECK-RV32-NEXT: lui a0, %hi(h)
194+
; CHECK-RV32-NEXT: addi a0, a0, %lo(h)
195+
; CHECK-RV32-NEXT: vle32.v v12, (a0)
196+
; CHECK-RV32-NEXT: vadd.vv v8, v12, v8
197+
; CHECK-RV32-NEXT: lui a0, %hi(i)
198+
; CHECK-RV32-NEXT: addi a0, a0, %lo(i)
199+
; CHECK-RV32-NEXT: vse32.v v8, (a0)
200+
; CHECK-RV32-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
201+
; CHECK-RV32-NEXT: csrr a0, vlenb
202+
; CHECK-RV32-NEXT: slli a1, a0, 3
203+
; CHECK-RV32-NEXT: sub a0, a1, a0
204+
; CHECK-RV32-NEXT: add a0, sp, a0
205+
; CHECK-RV32-NEXT: addi a0, a0, 16
206+
; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
207+
; CHECK-RV32-NEXT: csrr a0, vlenb
208+
; CHECK-RV32-NEXT: slli a0, a0, 1
209+
; CHECK-RV32-NEXT: mv a1, a0
210+
; CHECK-RV32-NEXT: slli a0, a0, 1
211+
; CHECK-RV32-NEXT: add a0, a0, a1
212+
; CHECK-RV32-NEXT: add a0, sp, a0
213+
; CHECK-RV32-NEXT: addi a0, a0, 16
214+
; CHECK-RV32-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
215+
; CHECK-RV32-NEXT: csrr a0, vlenb
216+
; CHECK-RV32-NEXT: slli a1, a0, 2
217+
; CHECK-RV32-NEXT: add a0, a1, a0
218+
; CHECK-RV32-NEXT: add a0, sp, a0
219+
; CHECK-RV32-NEXT: addi a0, a0, 16
220+
; CHECK-RV32-NEXT: vl1r.v v10, (a0) # vscale x 8-byte Folded Reload
221+
; CHECK-RV32-NEXT: csrr a0, vlenb
222+
; CHECK-RV32-NEXT: slli a0, a0, 2
223+
; CHECK-RV32-NEXT: add a0, sp, a0
224+
; CHECK-RV32-NEXT: addi a0, a0, 16
225+
; CHECK-RV32-NEXT: vl1r.v v11, (a0) # vscale x 8-byte Folded Reload
226+
; CHECK-RV32-NEXT: csrr a0, vlenb
227+
; CHECK-RV32-NEXT: slli a1, a0, 1
228+
; CHECK-RV32-NEXT: add a0, a1, a0
229+
; CHECK-RV32-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
230+
; CHECK-RV32-NEXT: add a0, sp, a0
231+
; CHECK-RV32-NEXT: addi a0, a0, 16
232+
; CHECK-RV32-NEXT: vl1r.v v12, (a0) # vscale x 8-byte Folded Reload
233+
; CHECK-RV32-NEXT: csrr a0, vlenb
234+
; CHECK-RV32-NEXT: slli a0, a0, 1
235+
; CHECK-RV32-NEXT: add a0, sp, a0
236+
; CHECK-RV32-NEXT: addi a0, a0, 16
237+
; CHECK-RV32-NEXT: vl1r.v v13, (a0) # vscale x 8-byte Folded Reload
238+
; CHECK-RV32-NEXT: csrr a0, vlenb
239+
; CHECK-RV32-NEXT: add a0, sp, a0
240+
; CHECK-RV32-NEXT: addi a0, a0, 16
241+
; CHECK-RV32-NEXT: vl1r.v v14, (a0) # vscale x 8-byte Folded Reload
242+
; CHECK-RV32-NEXT: addi a0, sp, 16
243+
; CHECK-RV32-NEXT: vl1r.v v15, (a0) # vscale x 8-byte Folded Reload
244+
; CHECK-RV32-NEXT: csrr a0, vlenb
245+
; CHECK-RV32-NEXT: slli a0, a0, 3
246+
; CHECK-RV32-NEXT: add sp, sp, a0
247+
; CHECK-RV32-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
248+
; CHECK-RV32-NEXT: addi sp, sp, 32
249+
; CHECK-RV32-NEXT: mret
250+
%1 = load <16 x i32>, ptr @g
251+
%2 = load <16 x i32>, ptr @h
252+
%add = add nsw <16 x i32> %2, %1
253+
store <16 x i32> %add, ptr @i
254+
ret void
255+
}
256+
257+
@j = external global <32 x i32>
258+
@k = external global <32 x i32>
259+
@l = external global <32 x i32>
260+
261+
define void @foo_lmul8() nounwind #0 {
262+
; CHECK-RV32-LABEL: foo_lmul8:
263+
; CHECK-RV32: # %bb.0:
264+
; CHECK-RV32-NEXT: addi sp, sp, -32
265+
; CHECK-RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
266+
; CHECK-RV32-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
267+
; CHECK-RV32-NEXT: csrr a0, vlenb
268+
; CHECK-RV32-NEXT: slli a0, a0, 4
269+
; CHECK-RV32-NEXT: sub sp, sp, a0
270+
; CHECK-RV32-NEXT: csrr a0, vlenb
271+
; CHECK-RV32-NEXT: slli a1, a0, 4
272+
; CHECK-RV32-NEXT: sub a0, a1, a0
273+
; CHECK-RV32-NEXT: add a0, sp, a0
274+
; CHECK-RV32-NEXT: addi a0, a0, 16
275+
; CHECK-RV32-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
276+
; CHECK-RV32-NEXT: csrr a0, vlenb
277+
; CHECK-RV32-NEXT: slli a0, a0, 1
278+
; CHECK-RV32-NEXT: mv a1, a0
279+
; CHECK-RV32-NEXT: slli a0, a0, 1
280+
; CHECK-RV32-NEXT: add a1, a1, a0
281+
; CHECK-RV32-NEXT: slli a0, a0, 1
282+
; CHECK-RV32-NEXT: add a0, a0, a1
283+
; CHECK-RV32-NEXT: add a0, sp, a0
284+
; CHECK-RV32-NEXT: addi a0, a0, 16
285+
; CHECK-RV32-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
286+
; CHECK-RV32-NEXT: csrr a0, vlenb
287+
; CHECK-RV32-NEXT: mv a1, a0
288+
; CHECK-RV32-NEXT: slli a0, a0, 2
289+
; CHECK-RV32-NEXT: add a1, a1, a0
290+
; CHECK-RV32-NEXT: slli a0, a0, 1
291+
; CHECK-RV32-NEXT: add a0, a0, a1
292+
; CHECK-RV32-NEXT: add a0, sp, a0
293+
; CHECK-RV32-NEXT: addi a0, a0, 16
294+
; CHECK-RV32-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
295+
; CHECK-RV32-NEXT: csrr a0, vlenb
296+
; CHECK-RV32-NEXT: slli a0, a0, 2
297+
; CHECK-RV32-NEXT: mv a1, a0
298+
; CHECK-RV32-NEXT: slli a0, a0, 1
299+
; CHECK-RV32-NEXT: add a0, a0, a1
300+
; CHECK-RV32-NEXT: add a0, sp, a0
301+
; CHECK-RV32-NEXT: addi a0, a0, 16
302+
; CHECK-RV32-NEXT: vs1r.v v11, (a0) # vscale x 8-byte Folded Spill
303+
; CHECK-RV32-NEXT: csrr a0, vlenb
304+
; CHECK-RV32-NEXT: mv a1, a0
305+
; CHECK-RV32-NEXT: slli a0, a0, 1
306+
; CHECK-RV32-NEXT: add a1, a1, a0
307+
; CHECK-RV32-NEXT: slli a0, a0, 2
308+
; CHECK-RV32-NEXT: add a0, a0, a1
309+
; CHECK-RV32-NEXT: add a0, sp, a0
310+
; CHECK-RV32-NEXT: addi a0, a0, 16
311+
; CHECK-RV32-NEXT: vs1r.v v12, (a0) # vscale x 8-byte Folded Spill
312+
; CHECK-RV32-NEXT: csrr a0, vlenb
313+
; CHECK-RV32-NEXT: slli a0, a0, 1
314+
; CHECK-RV32-NEXT: mv a1, a0
315+
; CHECK-RV32-NEXT: slli a0, a0, 2
316+
; CHECK-RV32-NEXT: add a0, a0, a1
317+
; CHECK-RV32-NEXT: add a0, sp, a0
318+
; CHECK-RV32-NEXT: addi a0, a0, 16
319+
; CHECK-RV32-NEXT: vs1r.v v13, (a0) # vscale x 8-byte Folded Spill
320+
; CHECK-RV32-NEXT: csrr a0, vlenb
321+
; CHECK-RV32-NEXT: slli a1, a0, 3
322+
; CHECK-RV32-NEXT: add a0, a1, a0
323+
; CHECK-RV32-NEXT: add a0, sp, a0
324+
; CHECK-RV32-NEXT: addi a0, a0, 16
325+
; CHECK-RV32-NEXT: vs1r.v v14, (a0) # vscale x 8-byte Folded Spill
326+
; CHECK-RV32-NEXT: csrr a0, vlenb
327+
; CHECK-RV32-NEXT: slli a0, a0, 3
328+
; CHECK-RV32-NEXT: add a0, sp, a0
329+
; CHECK-RV32-NEXT: addi a0, a0, 16
330+
; CHECK-RV32-NEXT: vs1r.v v15, (a0) # vscale x 8-byte Folded Spill
331+
; CHECK-RV32-NEXT: csrr a0, vlenb
332+
; CHECK-RV32-NEXT: slli a1, a0, 3
333+
; CHECK-RV32-NEXT: sub a0, a1, a0
334+
; CHECK-RV32-NEXT: add a0, sp, a0
335+
; CHECK-RV32-NEXT: addi a0, a0, 16
336+
; CHECK-RV32-NEXT: vs1r.v v16, (a0) # vscale x 8-byte Folded Spill
337+
; CHECK-RV32-NEXT: csrr a0, vlenb
338+
; CHECK-RV32-NEXT: slli a0, a0, 1
339+
; CHECK-RV32-NEXT: mv a1, a0
340+
; CHECK-RV32-NEXT: slli a0, a0, 1
341+
; CHECK-RV32-NEXT: add a0, a0, a1
342+
; CHECK-RV32-NEXT: add a0, sp, a0
343+
; CHECK-RV32-NEXT: addi a0, a0, 16
344+
; CHECK-RV32-NEXT: vs1r.v v17, (a0) # vscale x 8-byte Folded Spill
345+
; CHECK-RV32-NEXT: csrr a0, vlenb
346+
; CHECK-RV32-NEXT: slli a1, a0, 2
347+
; CHECK-RV32-NEXT: add a0, a1, a0
348+
; CHECK-RV32-NEXT: add a0, sp, a0
349+
; CHECK-RV32-NEXT: addi a0, a0, 16
350+
; CHECK-RV32-NEXT: vs1r.v v18, (a0) # vscale x 8-byte Folded Spill
351+
; CHECK-RV32-NEXT: csrr a0, vlenb
352+
; CHECK-RV32-NEXT: slli a0, a0, 2
353+
; CHECK-RV32-NEXT: add a0, sp, a0
354+
; CHECK-RV32-NEXT: addi a0, a0, 16
355+
; CHECK-RV32-NEXT: vs1r.v v19, (a0) # vscale x 8-byte Folded Spill
356+
; CHECK-RV32-NEXT: csrr a0, vlenb
357+
; CHECK-RV32-NEXT: slli a1, a0, 1
358+
; CHECK-RV32-NEXT: add a0, a1, a0
359+
; CHECK-RV32-NEXT: add a0, sp, a0
360+
; CHECK-RV32-NEXT: addi a0, a0, 16
361+
; CHECK-RV32-NEXT: vs1r.v v20, (a0) # vscale x 8-byte Folded Spill
362+
; CHECK-RV32-NEXT: csrr a0, vlenb
363+
; CHECK-RV32-NEXT: slli a0, a0, 1
364+
; CHECK-RV32-NEXT: add a0, sp, a0
365+
; CHECK-RV32-NEXT: addi a0, a0, 16
366+
; CHECK-RV32-NEXT: vs1r.v v21, (a0) # vscale x 8-byte Folded Spill
367+
; CHECK-RV32-NEXT: csrr a0, vlenb
368+
; CHECK-RV32-NEXT: add a0, sp, a0
369+
; CHECK-RV32-NEXT: addi a0, a0, 16
370+
; CHECK-RV32-NEXT: vs1r.v v22, (a0) # vscale x 8-byte Folded Spill
371+
; CHECK-RV32-NEXT: addi a0, sp, 16
372+
; CHECK-RV32-NEXT: vs1r.v v23, (a0) # vscale x 8-byte Folded Spill
373+
; CHECK-RV32-NEXT: lui a0, %hi(j)
374+
; CHECK-RV32-NEXT: addi a0, a0, %lo(j)
375+
; CHECK-RV32-NEXT: li a1, 32
376+
; CHECK-RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
377+
; CHECK-RV32-NEXT: vle32.v v8, (a0)
378+
; CHECK-RV32-NEXT: lui a0, %hi(k)
379+
; CHECK-RV32-NEXT: addi a0, a0, %lo(k)
380+
; CHECK-RV32-NEXT: vle32.v v16, (a0)
381+
; CHECK-RV32-NEXT: vadd.vv v8, v16, v8
382+
; CHECK-RV32-NEXT: lui a0, %hi(l)
383+
; CHECK-RV32-NEXT: addi a0, a0, %lo(l)
384+
; CHECK-RV32-NEXT: vse32.v v8, (a0)
385+
; CHECK-RV32-NEXT: csrr a0, vlenb
386+
; CHECK-RV32-NEXT: slli a1, a0, 4
387+
; CHECK-RV32-NEXT: sub a0, a1, a0
388+
; CHECK-RV32-NEXT: add a0, sp, a0
389+
; CHECK-RV32-NEXT: addi a0, a0, 16
390+
; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
391+
; CHECK-RV32-NEXT: csrr a0, vlenb
392+
; CHECK-RV32-NEXT: slli a0, a0, 1
393+
; CHECK-RV32-NEXT: mv a1, a0
394+
; CHECK-RV32-NEXT: slli a0, a0, 1
395+
; CHECK-RV32-NEXT: add a1, a1, a0
396+
; CHECK-RV32-NEXT: slli a0, a0, 1
397+
; CHECK-RV32-NEXT: add a0, a0, a1
398+
; CHECK-RV32-NEXT: add a0, sp, a0
399+
; CHECK-RV32-NEXT: addi a0, a0, 16
400+
; CHECK-RV32-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
401+
; CHECK-RV32-NEXT: csrr a0, vlenb
402+
; CHECK-RV32-NEXT: mv a1, a0
403+
; CHECK-RV32-NEXT: slli a0, a0, 2
404+
; CHECK-RV32-NEXT: add a1, a1, a0
405+
; CHECK-RV32-NEXT: slli a0, a0, 1
406+
; CHECK-RV32-NEXT: add a0, a0, a1
407+
; CHECK-RV32-NEXT: add a0, sp, a0
408+
; CHECK-RV32-NEXT: addi a0, a0, 16
409+
; CHECK-RV32-NEXT: vl1r.v v10, (a0) # vscale x 8-byte Folded Reload
410+
; CHECK-RV32-NEXT: csrr a0, vlenb
411+
; CHECK-RV32-NEXT: slli a0, a0, 2
412+
; CHECK-RV32-NEXT: mv a1, a0
413+
; CHECK-RV32-NEXT: slli a0, a0, 1
414+
; CHECK-RV32-NEXT: add a0, a0, a1
415+
; CHECK-RV32-NEXT: add a0, sp, a0
416+
; CHECK-RV32-NEXT: addi a0, a0, 16
417+
; CHECK-RV32-NEXT: vl1r.v v11, (a0) # vscale x 8-byte Folded Reload
418+
; CHECK-RV32-NEXT: csrr a0, vlenb
419+
; CHECK-RV32-NEXT: mv a1, a0
420+
; CHECK-RV32-NEXT: slli a0, a0, 1
421+
; CHECK-RV32-NEXT: add a1, a1, a0
422+
; CHECK-RV32-NEXT: slli a0, a0, 2
423+
; CHECK-RV32-NEXT: add a0, a0, a1
424+
; CHECK-RV32-NEXT: add a0, sp, a0
425+
; CHECK-RV32-NEXT: addi a0, a0, 16
426+
; CHECK-RV32-NEXT: vl1r.v v12, (a0) # vscale x 8-byte Folded Reload
427+
; CHECK-RV32-NEXT: csrr a0, vlenb
428+
; CHECK-RV32-NEXT: slli a0, a0, 1
429+
; CHECK-RV32-NEXT: mv a1, a0
430+
; CHECK-RV32-NEXT: slli a0, a0, 2
431+
; CHECK-RV32-NEXT: add a0, a0, a1
432+
; CHECK-RV32-NEXT: add a0, sp, a0
433+
; CHECK-RV32-NEXT: addi a0, a0, 16
434+
; CHECK-RV32-NEXT: vl1r.v v13, (a0) # vscale x 8-byte Folded Reload
435+
; CHECK-RV32-NEXT: csrr a0, vlenb
436+
; CHECK-RV32-NEXT: slli a1, a0, 3
437+
; CHECK-RV32-NEXT: add a0, a1, a0
438+
; CHECK-RV32-NEXT: add a0, sp, a0
439+
; CHECK-RV32-NEXT: addi a0, a0, 16
440+
; CHECK-RV32-NEXT: vl1r.v v14, (a0) # vscale x 8-byte Folded Reload
441+
; CHECK-RV32-NEXT: csrr a0, vlenb
442+
; CHECK-RV32-NEXT: slli a0, a0, 3
443+
; CHECK-RV32-NEXT: add a0, sp, a0
444+
; CHECK-RV32-NEXT: addi a0, a0, 16
445+
; CHECK-RV32-NEXT: vl1r.v v15, (a0) # vscale x 8-byte Folded Reload
446+
; CHECK-RV32-NEXT: csrr a0, vlenb
447+
; CHECK-RV32-NEXT: slli a1, a0, 3
448+
; CHECK-RV32-NEXT: sub a0, a1, a0
449+
; CHECK-RV32-NEXT: add a0, sp, a0
450+
; CHECK-RV32-NEXT: addi a0, a0, 16
451+
; CHECK-RV32-NEXT: vl1r.v v16, (a0) # vscale x 8-byte Folded Reload
452+
; CHECK-RV32-NEXT: csrr a0, vlenb
453+
; CHECK-RV32-NEXT: slli a0, a0, 1
454+
; CHECK-RV32-NEXT: mv a1, a0
455+
; CHECK-RV32-NEXT: slli a0, a0, 1
456+
; CHECK-RV32-NEXT: add a0, a0, a1
457+
; CHECK-RV32-NEXT: add a0, sp, a0
458+
; CHECK-RV32-NEXT: addi a0, a0, 16
459+
; CHECK-RV32-NEXT: vl1r.v v17, (a0) # vscale x 8-byte Folded Reload
460+
; CHECK-RV32-NEXT: csrr a0, vlenb
461+
; CHECK-RV32-NEXT: slli a1, a0, 2
462+
; CHECK-RV32-NEXT: add a0, a1, a0
463+
; CHECK-RV32-NEXT: add a0, sp, a0
464+
; CHECK-RV32-NEXT: addi a0, a0, 16
465+
; CHECK-RV32-NEXT: vl1r.v v18, (a0) # vscale x 8-byte Folded Reload
466+
; CHECK-RV32-NEXT: csrr a0, vlenb
467+
; CHECK-RV32-NEXT: slli a0, a0, 2
468+
; CHECK-RV32-NEXT: add a0, sp, a0
469+
; CHECK-RV32-NEXT: addi a0, a0, 16
470+
; CHECK-RV32-NEXT: vl1r.v v19, (a0) # vscale x 8-byte Folded Reload
471+
; CHECK-RV32-NEXT: csrr a0, vlenb
472+
; CHECK-RV32-NEXT: slli a1, a0, 1
473+
; CHECK-RV32-NEXT: add a0, a1, a0
474+
; CHECK-RV32-NEXT: add a0, sp, a0
475+
; CHECK-RV32-NEXT: addi a0, a0, 16
476+
; CHECK-RV32-NEXT: vl1r.v v20, (a0) # vscale x 8-byte Folded Reload
477+
; CHECK-RV32-NEXT: csrr a0, vlenb
478+
; CHECK-RV32-NEXT: slli a0, a0, 1
479+
; CHECK-RV32-NEXT: add a0, sp, a0
480+
; CHECK-RV32-NEXT: addi a0, a0, 16
481+
; CHECK-RV32-NEXT: vl1r.v v21, (a0) # vscale x 8-byte Folded Reload
482+
; CHECK-RV32-NEXT: csrr a0, vlenb
483+
; CHECK-RV32-NEXT: add a0, sp, a0
484+
; CHECK-RV32-NEXT: addi a0, a0, 16
485+
; CHECK-RV32-NEXT: vl1r.v v22, (a0) # vscale x 8-byte Folded Reload
486+
; CHECK-RV32-NEXT: addi a0, sp, 16
487+
; CHECK-RV32-NEXT: vl1r.v v23, (a0) # vscale x 8-byte Folded Reload
488+
; CHECK-RV32-NEXT: csrr a0, vlenb
489+
; CHECK-RV32-NEXT: slli a0, a0, 4
490+
; CHECK-RV32-NEXT: add sp, sp, a0
491+
; CHECK-RV32-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
492+
; CHECK-RV32-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
493+
; CHECK-RV32-NEXT: addi sp, sp, 32
494+
; CHECK-RV32-NEXT: mret
495+
%1 = load <32 x i32>, ptr @j
496+
%2 = load <32 x i32>, ptr @k
497+
%add = add nsw <32 x i32> %2, %1
498+
store <32 x i32> %add, ptr @l
499+
ret void
500+
}
501+
502+
attributes #0 = { "interrupt"="machine" }

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