Skip to content

Commit 66aa206

Browse files
committed
s/fixupBlendComponents/fixupPtrauthDiscriminator/
1 parent 6e3bbe5 commit 66aa206

File tree

1 file changed

+8
-8
lines changed

1 file changed

+8
-8
lines changed

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3268,20 +3268,20 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
32683268
&AArch64::GPR64noipRegClass);
32693269
return BB;
32703270
case AArch64::AUTH_TCRETURN:
3271-
fixupBlendComponents(MI, BB, MI.getOperand(3), MI.getOperand(4),
3272-
&AArch64::tcGPR64RegClass);
3271+
fixupPtrauthDiscriminator(MI, BB, MI.getOperand(3), MI.getOperand(4),
3272+
&AArch64::tcGPR64RegClass);
32733273
return BB;
32743274
case AArch64::AUTH_TCRETURN_BTI:
3275-
fixupBlendComponents(MI, BB, MI.getOperand(3), MI.getOperand(4),
3276-
&AArch64::tcGPRnotx16x17RegClass);
3275+
fixupPtrauthDiscriminator(MI, BB, MI.getOperand(3), MI.getOperand(4),
3276+
&AArch64::tcGPRnotx16x17RegClass);
32773277
return BB;
32783278
case AArch64::BLRA:
3279-
fixupBlendComponents(MI, BB, MI.getOperand(2), MI.getOperand(3),
3280-
&AArch64::GPR64noipRegClass);
3279+
fixupPtrauthDiscriminator(MI, BB, MI.getOperand(2), MI.getOperand(3),
3280+
&AArch64::GPR64noipRegClass);
32813281
return BB;
32823282
case AArch64::BLRA_RVMARKER:
3283-
fixupBlendComponents(MI, BB, MI.getOperand(4), MI.getOperand(5),
3284-
&AArch64::GPR64noipRegClass);
3283+
fixupPtrauthDiscriminator(MI, BB, MI.getOperand(4), MI.getOperand(5),
3284+
&AArch64::GPR64noipRegClass);
32853285
return BB;
32863286
}
32873287
}

0 commit comments

Comments
 (0)