@@ -3268,20 +3268,20 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
3268
3268
&AArch64::GPR64noipRegClass);
3269
3269
return BB;
3270
3270
case AArch64::AUTH_TCRETURN:
3271
- fixupBlendComponents (MI, BB, MI.getOperand(3), MI.getOperand(4),
3272
- &AArch64::tcGPR64RegClass);
3271
+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(3), MI.getOperand(4),
3272
+ &AArch64::tcGPR64RegClass);
3273
3273
return BB;
3274
3274
case AArch64::AUTH_TCRETURN_BTI:
3275
- fixupBlendComponents (MI, BB, MI.getOperand(3), MI.getOperand(4),
3276
- &AArch64::tcGPRnotx16x17RegClass);
3275
+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(3), MI.getOperand(4),
3276
+ &AArch64::tcGPRnotx16x17RegClass);
3277
3277
return BB;
3278
3278
case AArch64::BLRA:
3279
- fixupBlendComponents (MI, BB, MI.getOperand(2), MI.getOperand(3),
3280
- &AArch64::GPR64noipRegClass);
3279
+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(2), MI.getOperand(3),
3280
+ &AArch64::GPR64noipRegClass);
3281
3281
return BB;
3282
3282
case AArch64::BLRA_RVMARKER:
3283
- fixupBlendComponents (MI, BB, MI.getOperand(4), MI.getOperand(5),
3284
- &AArch64::GPR64noipRegClass);
3283
+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(4), MI.getOperand(5),
3284
+ &AArch64::GPR64noipRegClass);
3285
3285
return BB;
3286
3286
}
3287
3287
}
0 commit comments