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committedMay 26, 2025·
[LoongArch] Document the inline asm q constraint
See #141037.
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‎llvm/docs/LangRef.rst

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- ``m``: A memory operand whose address is formed by a base register and
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offset that is suitable for use in instructions with the same addressing
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mode as st.w and ld.w.
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- ``q``: A general-purpose register except for $r0 and $r1 (for the csrxchg
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instruction).
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- ``I``: A signed 12-bit constant (for arithmetic instructions).
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- ``J``: An immediate integer zero.
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- ``K``: An unsigned 12-bit constant (for logic instructions).

‎llvm/docs/ReleaseNotes.md

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--------------------------------
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* Changing the default code model from `small` to `medium` for 64-bit.
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* Added inline asm support for the `q` constraint.
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Changes to the MIPS Backend
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---------------------------

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