From 2160b4d0f350eb067c79afcbdf4dc16b64091325 Mon Sep 17 00:00:00 2001 From: Hideto Ueno Date: Thu, 31 Oct 2024 00:29:43 +0900 Subject: [PATCH] [FIRRTL] Extend Convention to specify type lowering for body Extend the FIRRTL Convention attribute to separately specify type lowering behavior for module ports and module body. This allows more fine-grained control over how types are lowered in different contexts. The Convention attribute now takes two parameters: - Port convention: Controls how module ports are lowered - Body convention: Controls how types within the module body are lowered Updates the syntax from: #firrtl to: #firrtl.convention This change enables modules to have different type lowering strategies for their interfaces and their bodies. For example, a module could preserve aggregate types in its ports while scalarizing them in its body. Updates all relevant tests and code to use the new two-parameter Convention format. --- include/circt/Dialect/FIRRTL/FIRRTLEnums.td | 8 ++- .../Dialect/FIRRTL/FIRRTLOpInterfaces.td | 13 +++- .../circt/Dialect/FIRRTL/FIRRTLStructure.td | 2 +- lib/CAPI/Dialect/FIRRTL.cpp | 26 +++---- lib/Dialect/FIRRTL/FIRRTLOps.cpp | 55 ++++++++------ lib/Dialect/FIRRTL/Import/FIRParser.cpp | 7 +- .../FIRRTL/Transforms/ExtractInstances.cpp | 4 +- .../FIRRTL/Transforms/LowerAnnotations.cpp | 71 ++++++++++++++++--- lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp | 5 +- lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp | 3 +- .../FIRRTL/Transforms/LowerSignatures.cpp | 2 +- lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp | 40 ++++++----- test/Conversion/FIRRTLToHW/intrinsics.mlir | 2 +- test/Conversion/FIRRTLToHW/lower-to-hw.mlir | 10 +-- test/Conversion/FIRRTLToHW/zero-width.mlir | 2 +- test/Dialect/FIRRTL/annotations.mlir | 24 ++++++- test/Dialect/FIRRTL/canonicalization.mlir | 4 +- test/Dialect/FIRRTL/check-comb-loops.mlir | 14 ++-- test/Dialect/FIRRTL/dedup.mlir | 2 +- test/Dialect/FIRRTL/errors.mlir | 10 +-- test/Dialect/FIRRTL/imconstprop.mlir | 2 +- test/Dialect/FIRRTL/imdce.mlir | 10 +-- test/Dialect/FIRRTL/infer-resets.mlir | 2 +- test/Dialect/FIRRTL/inferRW.mlir | 2 +- test/Dialect/FIRRTL/inliner-errors.mlir | 2 +- test/Dialect/FIRRTL/inliner.mlir | 4 +- test/Dialect/FIRRTL/lower-classes.mlir | 10 +-- test/Dialect/FIRRTL/lower-dpi-error.mlir | 4 +- test/Dialect/FIRRTL/lower-dpi.mlir | 4 +- test/Dialect/FIRRTL/lower-layers.mlir | 6 +- test/Dialect/FIRRTL/lower-open-aggs.mlir | 6 +- .../FIRRTL/lower-signatures-error.mlir | 4 +- test/Dialect/FIRRTL/lower-signatures.mlir | 16 ++--- .../Dialect/FIRRTL/lower-types-aggregate.mlir | 12 ++-- .../FIRRTL/lower-types-issue-5592.mlir | 2 +- test/Dialect/FIRRTL/lower-types-remat.mlir | 2 +- test/Dialect/FIRRTL/lower-types.mlir | 39 ++++++++++ test/Dialect/FIRRTL/lowerXMR.mlir | 6 +- .../FIRRTL/probes-to-signals-errors.mlir | 2 +- test/circt-reduce/name-sanitizer.mlir | 2 +- test/firtool/convention.fir | 48 ++++++------- 41 files changed, 317 insertions(+), 172 deletions(-) diff --git a/include/circt/Dialect/FIRRTL/FIRRTLEnums.td b/include/circt/Dialect/FIRRTL/FIRRTLEnums.td index 335d066c96c9..1706d7c16788 100644 --- a/include/circt/Dialect/FIRRTL/FIRRTLEnums.td +++ b/include/circt/Dialect/FIRRTL/FIRRTLEnums.td @@ -44,7 +44,13 @@ def Convention : I32EnumAttr<"Convention", "lowering convention", [ let genSpecializedAttr = 0; } -def ConventionAttr : EnumAttr; +// Pair of port and body conventions +def ConventionAttr : AttrDef { + let parameters = (ins "Convention":$portConvention, "Convention":$bodyConvention); + let summary = "Pair of port and body conventions"; + let mnemonic = "convention"; + let assemblyFormat = "`<` $portConvention `,` $bodyConvention `>`"; +} //===----------------------------------------------------------------------===// // Layer Lowering Conventions diff --git a/include/circt/Dialect/FIRRTL/FIRRTLOpInterfaces.td b/include/circt/Dialect/FIRRTL/FIRRTLOpInterfaces.td index 95765d938cb9..e7137433185f 100644 --- a/include/circt/Dialect/FIRRTL/FIRRTLOpInterfaces.td +++ b/include/circt/Dialect/FIRRTL/FIRRTLOpInterfaces.td @@ -32,10 +32,17 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod //===------------------------------------------------------------------===// InterfaceMethod<"Get the module's instantiation convention", - "ConventionAttr", "getConventionAttr">, + "ConventionAttr", "getConventionAttr", (ins), [{}], + /*defaultImplementation=*/[{ + return ConventionAttr::get($_op.getContext(), $_op.getPortConvention(), + $_op.getBodyConvention()); + }]>, - InterfaceMethod<"Get the module's instantiation convention", - "Convention", "getConvention">, + InterfaceMethod<"Get the module's port convention", + "Convention", "getPortConvention">, + + InterfaceMethod<"Get the module's body convention", + "Convention", "getBodyConvention">, //===------------------------------------------------------------------===// // Enabled (AKA Required) Layers diff --git a/include/circt/Dialect/FIRRTL/FIRRTLStructure.td b/include/circt/Dialect/FIRRTL/FIRRTLStructure.td index 35ebf676e435..7c1557f5593e 100644 --- a/include/circt/Dialect/FIRRTL/FIRRTLStructure.td +++ b/include/circt/Dialect/FIRRTL/FIRRTLStructure.td @@ -126,7 +126,7 @@ class FIRRTLModuleLike traits = []> : } -def FModuleOp : FIRRTLModuleLike<"module", [SingleBlock, NoTerminator]> { +def FModuleOp : FIRRTLModuleLike<"module", [SingleBlock, NoTerminator, DeclareOpInterfaceMethods]> { let summary = "FIRRTL Module"; let description = [{ The "firrtl.module" operation represents a Verilog module, including a given diff --git a/lib/CAPI/Dialect/FIRRTL.cpp b/lib/CAPI/Dialect/FIRRTL.cpp index 8f4f8b4c21fd..7dd94ecc5f1e 100644 --- a/lib/CAPI/Dialect/FIRRTL.cpp +++ b/lib/CAPI/Dialect/FIRRTL.cpp @@ -174,19 +174,19 @@ MlirType firrtlTypeGetMaskType(MlirType type) { //===----------------------------------------------------------------------===// MlirAttribute firrtlAttrGetConvention(MlirContext ctx, - FIRRTLConvention convention) { - Convention value; - - switch (convention) { - case FIRRTL_CONVENTION_INTERNAL: - value = Convention::Internal; - break; - case FIRRTL_CONVENTION_SCALARIZED: - value = Convention::Scalarized; - break; - } - - return wrap(ConventionAttr::get(unwrap(ctx), value)); + FIRRTLConvention portConvention, + FIRRTLConvention bodyConvention) { + auto getConvention = [&](FIRRTLConvention convention) { + switch (convention) { + case FIRRTL_CONVENTION_INTERNAL: + return Convention::Internal; + case FIRRTL_CONVENTION_SCALARIZED: + return Convention::Scalarized; + } + }; + + return wrap(ConventionAttr::get(unwrap(ctx), getConvention(portConvention), + getConvention(bodyConvention))); } MlirAttribute firrtlAttrGetPortDirs(MlirContext ctx, size_t count, diff --git a/lib/Dialect/FIRRTL/FIRRTLOps.cpp b/lib/Dialect/FIRRTL/FIRRTLOps.cpp index e3435b8d613e..941c4355c6ff 100644 --- a/lib/Dialect/FIRRTL/FIRRTLOps.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLOps.cpp @@ -1351,7 +1351,8 @@ static void printFModuleLikeOp(OpAsmPrinter &p, FModuleLike op) { "sym_name", "portDirections", "portTypes", "portAnnotations", "portSymbols", "portLocations", "parameters", visibilityAttrName}; - if (op.getConvention() == Convention::Internal) + if (op.getPortConvention() == Convention::Internal && + op.getBodyConvention() == Convention::Internal) omittedAttrs.push_back("convention"); // We can omit the portNames if they were able to be printed as properly as @@ -1535,9 +1536,10 @@ ParseResult FModuleOp::parse(OpAsmParser &parser, OperationState &result) { if (parseFModuleLikeOp(parser, result, /*hasSSAIdentifiers=*/true)) return failure(); if (!result.attributes.get("convention")) - result.addAttribute( - "convention", - ConventionAttr::get(result.getContext(), Convention::Internal)); + result.addAttribute("convention", + ConventionAttr::get(result.getContext(), + Convention::Internal, + Convention::Internal)); if (!result.attributes.get("layers")) result.addAttribute("layers", ArrayAttr::get(parser.getContext(), {})); return success(); @@ -1547,9 +1549,10 @@ ParseResult FExtModuleOp::parse(OpAsmParser &parser, OperationState &result) { if (parseFModuleLikeOp(parser, result, /*hasSSAIdentifiers=*/false)) return failure(); if (!result.attributes.get("convention")) - result.addAttribute( - "convention", - ConventionAttr::get(result.getContext(), Convention::Internal)); + result.addAttribute("convention", + ConventionAttr::get(result.getContext(), + Convention::Internal, + Convention::Internal)); return success(); } @@ -1767,17 +1770,13 @@ ArrayAttr FMemModuleOp::getParameters() { return {}; } ArrayAttr FModuleOp::getParameters() { return {}; } -Convention FIntModuleOp::getConvention() { return Convention::Internal; } +Convention FIntModuleOp::getPortConvention() { return Convention::Internal; } -ConventionAttr FIntModuleOp::getConventionAttr() { - return ConventionAttr::get(getContext(), getConvention()); -} +Convention FIntModuleOp::getBodyConvention() { return Convention::Internal; } -Convention FMemModuleOp::getConvention() { return Convention::Internal; } +Convention FMemModuleOp::getPortConvention() { return Convention::Internal; } -ConventionAttr FMemModuleOp::getConventionAttr() { - return ConventionAttr::get(getContext(), getConvention()); -} +Convention FMemModuleOp::getBodyConvention() { return Convention::Internal; } //===----------------------------------------------------------------------===// // ClassLike Helpers @@ -2056,12 +2055,26 @@ void ClassOp::insertPorts(ArrayRef> ports) { ::insertPorts(cast((Operation *)*this), ports); } -Convention ClassOp::getConvention() { return Convention::Internal; } +Convention FModuleOp::getPortConvention() { + return getConventionAttr().getPortConvention(); +} + +Convention FModuleOp::getBodyConvention() { + return getConventionAttr().getBodyConvention(); +} + +Convention FExtModuleOp::getPortConvention() { + return getConventionAttr().getPortConvention(); +} -ConventionAttr ClassOp::getConventionAttr() { - return ConventionAttr::get(getContext(), getConvention()); +Convention FExtModuleOp::getBodyConvention() { + return getConventionAttr().getBodyConvention(); } +Convention ClassOp::getPortConvention() { return Convention::Internal; } + +Convention ClassOp::getBodyConvention() { return Convention::Internal; } + ArrayAttr ClassOp::getParameters() { return {}; } ArrayAttr ClassOp::getPortAnnotationsAttr() { @@ -2142,11 +2155,9 @@ void ExtClassOp::insertPorts(ArrayRef> ports) { ::insertPorts(cast((Operation *)*this), ports); } -Convention ExtClassOp::getConvention() { return Convention::Internal; } +Convention ExtClassOp::getPortConvention() { return Convention::Internal; } -ConventionAttr ExtClassOp::getConventionAttr() { - return ConventionAttr::get(getContext(), getConvention()); -} +Convention ExtClassOp::getBodyConvention() { return Convention::Internal; } ArrayAttr ExtClassOp::getLayersAttr() { return ArrayAttr::get(getContext(), {}); diff --git a/lib/Dialect/FIRRTL/Import/FIRParser.cpp b/lib/Dialect/FIRRTL/Import/FIRParser.cpp index 37ffb687fe1d..758426e6d42a 100644 --- a/lib/Dialect/FIRRTL/Import/FIRParser.cpp +++ b/lib/Dialect/FIRRTL/Import/FIRParser.cpp @@ -5237,7 +5237,8 @@ ParseResult FIRCircuitParser::parseExtModule(CircuitOp circuit, getConstants().options.scalarizeExtModules ? Convention::Scalarized : Convention::Internal; - auto conventionAttr = ConventionAttr::get(getContext(), convention); + auto conventionAttr = + ConventionAttr::get(getContext(), convention, Convention::Internal); auto annotations = ArrayAttr::get(getContext(), {}); auto extModuleOp = builder.create( info.getLoc(), name, conventionAttr, portList, defName, annotations, @@ -5325,7 +5326,9 @@ ParseResult FIRCircuitParser::parseModule(CircuitOp circuit, bool isPublic, convention = Convention::Scalarized; if (!isPublic && getConstants().options.scalarizeInternalModules) convention = Convention::Scalarized; - auto conventionAttr = ConventionAttr::get(getContext(), convention); + // Use Internal as body convention. + auto conventionAttr = + ConventionAttr::get(getContext(), convention, Convention::Internal); auto builder = circuit.getBodyBuilder(); auto moduleOp = builder.create(info.getLoc(), name, conventionAttr, portList, annotations, layers); diff --git a/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp b/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp index cc64d74da0fb..3ff5a4e9300c 100644 --- a/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp @@ -983,7 +983,9 @@ void ExtractInstancesPass::groupInstances() { // Create the wrapper module. auto wrapper = builder.create( builder.getUnknownLoc(), wrapperModuleName, - ConventionAttr::get(builder.getContext(), Convention::Internal), ports); + ConventionAttr::get(builder.getContext(), Convention::Internal, + Convention::Internal), + ports); SymbolTable::setSymbolVisibility(wrapper, SymbolTable::Visibility::Private); // Instantiate the wrapper module in the parent and replace uses of the diff --git a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp index e42d83af73fb..d1cecbf0e75d 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp @@ -272,6 +272,7 @@ static LogicalResult applyDUTAnno(const AnnoPathValue &target, static std::optional parseConvention(llvm::StringRef str) { return ::llvm::StringSwitch<::std::optional>(str) .Case("scalarized", Convention::Scalarized) + .Case("internal", Convention::Internal) .Default(std::nullopt); } @@ -293,25 +294,75 @@ static LogicalResult applyConventionAnno(const AnnoPathValue &target, if (!target.isLocal()) return error() << "must be local"; - auto conventionStrAttr = - tryGetAs(anno, anno, "convention", loc, conventionAnnoClass); - if (!conventionStrAttr) + auto getConventionAttr = [&](StringRef name) -> FailureOr { + auto conventionName = + tryGetAs(anno, anno, name, loc, conventionAnnoClass); + if (!conventionName) + return failure(); + + auto conventionOpt = parseConvention(conventionName.getValue()); + if (!conventionOpt) + return error() << "unknown convention " << conventionName.getValue(); + + return *conventionOpt; + }; + auto portConvention = getConventionAttr("portConvention"); + auto bodyConvention = getConventionAttr("bodyConvention"); + if (failed(portConvention) || failed(bodyConvention)) return failure(); - auto conventionStr = conventionStrAttr.getValue(); - auto conventionOpt = parseConvention(conventionStr); - if (!conventionOpt) - return error() << "unknown convention " << conventionStr; + if (*portConvention == Convention::Internal && + *bodyConvention == Convention::Internal) { + // Convention is internal by default so there is nothing to change + return success(); + } + + auto includeHierarchy = anno.getAs("includeHierarchy"); + auto convention = + ConventionAttr::get(op->getContext(), *portConvention, *bodyConvention); - auto convention = *conventionOpt; + bool isBothScalarized = *portConvention == Convention::Scalarized && + *bodyConvention == Convention::Scalarized; + auto setConvention = [&](FModuleOp fmodule) { + if (isBothScalarized) // Fast path. + { + if (convention != fmodule.getConvention()) + fmodule.setConventionAttr(convention); + } else { + // We prioritize scalarized over internal. + auto getStrongerConvention = [&](Convention c1, + Convention c2) -> Convention { + return c1 == Convention::Scalarized ? c1 : c2; + }; + // Update both port and body conventions. + auto newConvention = ConventionAttr::get( + convention.getContext(), + getStrongerConvention(convention.getPortConvention(), + fmodule.getConvention().getPortConvention()), + getStrongerConvention(convention.getBodyConvention(), + fmodule.getConvention().getBodyConvention())); + if (newConvention != fmodule.getConvention()) + fmodule.setConventionAttr(newConvention); + } + }; if (auto moduleOp = dyn_cast(op)) { - moduleOp.setConvention(convention); + if (includeHierarchy && includeHierarchy.getValue()) { + for (auto *node : + llvm::post_order(state.instancePathCache.instanceGraph[moduleOp])) { + if (node) + if (auto fmodule = + dyn_cast_or_null(*node->getModule())) + setConvention(fmodule); + } + } else { + setConvention(moduleOp); + } return success(); } if (auto extModuleOp = dyn_cast(op)) { - extModuleOp.setConvention(convention); + extModuleOp.setConventionAttr(convention); return success(); } diff --git a/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp b/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp index 699fd552008c..9335f92a9c1d 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp @@ -209,8 +209,9 @@ FModuleOp LowerLayersPass::buildNewModule(OpBuilder &builder, llvm::sys::SmartScopedLock instrumentationLock(*circuitMutex); FModuleOp newModule = builder.create( location, builder.getStringAttr(namehint), - ConventionAttr::get(builder.getContext(), Convention::Internal), ports, - ArrayAttr{}); + ConventionAttr::get(builder.getContext(), Convention::Internal, + Convention::Internal), + ports, ArrayAttr{}); if (auto dir = getOutputFile(layerBlock.getLayerNameAttr())) { assert(dir.isDirectory()); newModule->setAttr("output_file", dir); diff --git a/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp b/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp index f0c0394e12fe..6b5fe531150f 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp @@ -244,7 +244,8 @@ void LowerMemoryPass::lowerMemory(MemOp mem, const FirMemory &summary, OpBuilder b(mem->getParentOfType()); auto wrapper = b.create( mem->getLoc(), wrapperName, - ConventionAttr::get(context, Convention::Internal), ports); + ConventionAttr::get(context, Convention::Internal, Convention::Internal), + ports); SymbolTable::setSymbolVisibility(wrapper, SymbolTable::Visibility::Private); // Create an instance of the external memory module. The instance has the diff --git a/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp b/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp index 225c4a462193..8cac74a7f32e 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp @@ -488,7 +488,7 @@ void LowerSignaturesPass::runOnOperation() { auto circuit = getOperation(); for (auto mod : circuit.getOps()) { - if (lowerModuleSignature(mod, mod.getConvention(), cache, + if (lowerModuleSignature(mod, mod.getPortConvention(), cache, portMap[mod.getNameAttr()]) .failed()) return signalPassFailure(); diff --git a/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp b/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp index 62db50f55dc5..a44e44341d10 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp @@ -339,12 +339,17 @@ struct TypeLoweringVisitor : public FIRRTLVisitor { TypeLoweringVisitor( MLIRContext *context, PreserveAggregate::PreserveMode preserveAggregate, + Convention bodyConvention, PreserveAggregate::PreserveMode memoryPreservationMode, SymbolTable &symTbl, const AttrCache &cache, const llvm::DenseMap &conventionTable) - : context(context), aggregatePreservationMode(preserveAggregate), + : context(context), defaultAggregatePreservationMode(preserveAggregate), memoryPreservationMode(memoryPreservationMode), symTbl(symTbl), - cache(cache), conventionTable(conventionTable) {} + cache(cache), conventionTable(conventionTable) { + bodyAggregatePreservationMode = bodyConvention == Convention::Scalarized + ? PreserveAggregate::None + : defaultAggregatePreservationMode; + } using FIRRTLVisitor::visitDecl; using FIRRTLVisitor::visitExpr; using FIRRTLVisitor::visitStmt; @@ -429,7 +434,7 @@ struct TypeLoweringVisitor : public FIRRTLVisitor { Location errorLoc); PreserveAggregate::PreserveMode - getPreservationModeForModule(FModuleLike moduleLike); + getPreservationModeForPorts(FModuleLike moduleLike); Value getSubWhatever(Value val, size_t index); size_t uniqueIdx = 0; @@ -441,7 +446,8 @@ struct TypeLoweringVisitor : public FIRRTLVisitor { MLIRContext *context; /// Aggregate preservation mode. - PreserveAggregate::PreserveMode aggregatePreservationMode; + PreserveAggregate::PreserveMode defaultAggregatePreservationMode; + PreserveAggregate::PreserveMode bodyAggregatePreservationMode; PreserveAggregate::PreserveMode memoryPreservationMode; /// The builder is set and maintained in the main loop. @@ -460,21 +466,21 @@ struct TypeLoweringVisitor : public FIRRTLVisitor { }; } // namespace -/// Return aggregate preservation mode for the module. If the module has a +/// Return aggregate preservation mode for the module ports. If the module has a /// scalarized linkage, then we may not preserve it's aggregate ports. PreserveAggregate::PreserveMode -TypeLoweringVisitor::getPreservationModeForModule(FModuleLike module) { +TypeLoweringVisitor::getPreservationModeForPorts(FModuleLike module) { auto lookup = conventionTable.find(module); if (lookup == conventionTable.end()) - return aggregatePreservationMode; + return defaultAggregatePreservationMode; switch (lookup->second) { case Convention::Scalarized: return PreserveAggregate::None; case Convention::Internal: - return aggregatePreservationMode; + return defaultAggregatePreservationMode; } llvm_unreachable("Unknown convention"); - return aggregatePreservationMode; + return defaultAggregatePreservationMode; } Value TypeLoweringVisitor::getSubWhatever(Value val, size_t index) { @@ -643,7 +649,7 @@ bool TypeLoweringVisitor::lowerProducer( return false; SmallVector fieldTypes; - if (!peelType(srcFType, fieldTypes, aggregatePreservationMode)) + if (!peelType(srcFType, fieldTypes, bodyAggregatePreservationMode)) return false; SmallVector lowered; @@ -809,7 +815,7 @@ bool TypeLoweringVisitor::lowerArg(FModuleLike module, size_t argIndex, // Flatten any bundle types. SmallVector fieldTypes; auto srcType = type_cast(newArgs[argIndex].pi.type); - if (!peelType(srcType, fieldTypes, getPreservationModeForModule(module))) + if (!peelType(srcType, fieldTypes, getPreservationModeForPorts(module))) return false; // Ports with internalPath set cannot be lowered. @@ -929,7 +935,7 @@ bool TypeLoweringVisitor::visitStmt(RefDefineOp op) { // Attempt to get the bundle types. SmallVector fields; - if (!peelType(op.getDest().getType(), fields, aggregatePreservationMode)) + if (!peelType(op.getDest().getType(), fields, bodyAggregatePreservationMode)) return false; // Loop over the leaf aggregates. @@ -1441,7 +1447,7 @@ bool TypeLoweringVisitor::visitDecl(InstanceOp op) { SmallVector newDirs; SmallVector newNames; SmallVector newPortAnno; - PreserveAggregate::PreserveMode mode = getPreservationModeForModule( + PreserveAggregate::PreserveMode mode = getPreservationModeForPorts( cast(op.getReferencedOperation(symTbl))); endFields.push_back(0); @@ -1648,15 +1654,15 @@ void LowerTypesPass::runOnOperation() { DenseMap conventionTable; auto circuit = getOperation(); for (auto module : circuit.getOps()) { - conventionTable.insert({module, module.getConvention()}); + conventionTable.insert({module, module.getPortConvention()}); ops.push_back(module); } // This lambda, executes in parallel for each Op within the circt. auto lowerModules = [&](FModuleLike op) -> LogicalResult { - auto tl = - TypeLoweringVisitor(&getContext(), preserveAggregate, preserveMemories, - symTbl, cache, conventionTable); + auto tl = TypeLoweringVisitor(&getContext(), preserveAggregate, + op.getBodyConvention(), preserveMemories, + symTbl, cache, conventionTable); tl.lowerModule(op); return LogicalResult::failure(tl.isFailed()); diff --git a/test/Conversion/FIRRTLToHW/intrinsics.mlir b/test/Conversion/FIRRTLToHW/intrinsics.mlir index f7a649c28cac..deb36e3ade7c 100644 --- a/test/Conversion/FIRRTLToHW/intrinsics.mlir +++ b/test/Conversion/FIRRTLToHW/intrinsics.mlir @@ -190,7 +190,7 @@ firrtl.circuit "Intrinsics" { in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>, in %in: !firrtl.uint<8> - ) attributes {convention = #firrtl} { + ) attributes {convention = #firrtl.convention} { // CHECK: hw.wire %in firrtl.int.fpga_probe %clock, %in : !firrtl.uint<8> } diff --git a/test/Conversion/FIRRTLToHW/lower-to-hw.mlir b/test/Conversion/FIRRTLToHW/lower-to-hw.mlir index ed875c52962b..c9d733f3c397 100644 --- a/test/Conversion/FIRRTLToHW/lower-to-hw.mlir +++ b/test/Conversion/FIRRTLToHW/lower-to-hw.mlir @@ -1422,7 +1422,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class = // CHECK-NEXT: %w = hw.wire %a {sv.attributes = [#sv.attribute<"mark_debug = \22yes\22">]} // CHECK-NEXT: %n = hw.wire %w {sv.attributes = [#sv.attribute<"mark_debug = \22yes\22">]} // CHECK-NEXT: %r = seq.firreg %a clock %clock {firrtl.random_init_start = 0 : ui64, sv.attributes = [#sv.attribute<"keep = \22true\22", emitAsComment>]} - firrtl.module @SVAttr(in %a: !firrtl.uint<1>, in %clock: !firrtl.clock, out %b1: !firrtl.uint<1>, out %b2: !firrtl.uint<1>) attributes {convention = #firrtl, sv.attributes = [#sv.attribute<"keep_hierarchy = \22true\22">]} { + firrtl.module @SVAttr(in %a: !firrtl.uint<1>, in %clock: !firrtl.clock, out %b1: !firrtl.uint<1>, out %b2: !firrtl.uint<1>) attributes {convention = #firrtl.convention, sv.attributes = [#sv.attribute<"keep_hierarchy = \22true\22">]} { %w = firrtl.wire {sv.attributes = [#sv.attribute<"mark_debug = \22yes\22">]} : !firrtl.uint<1> %n = firrtl.node %w {sv.attributes = [#sv.attribute<"mark_debug = \22yes\22">]} : !firrtl.uint<1> %r = firrtl.reg %clock {firrtl.random_init_start = 0 : ui64, sv.attributes = [#sv.attribute<"keep = \22true\22", emitAsComment>]} : !firrtl.clock, !firrtl.uint<1> @@ -1459,7 +1459,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class = // CHECK-NEXT: hw.output %[[OR]], %[[AND]], %[[XOR]] : !hw.array<2xi1>, !hw.array<2xi1>, !hw.array<2xi1> } // CHECK-LABEL: @MuxIntrinsics - firrtl.module @MuxIntrinsics(in %sel1: !firrtl.uint<1>, in %sel2: !firrtl.uint<2>, in %v3: !firrtl.uint<32>, in %v2: !firrtl.uint<32>, in %v1: !firrtl.uint<32>, in %v0: !firrtl.uint<32>, out %out1: !firrtl.uint<32>, out %out2: !firrtl.uint<32>) attributes {convention = #firrtl} { + firrtl.module @MuxIntrinsics(in %sel1: !firrtl.uint<1>, in %sel2: !firrtl.uint<2>, in %v3: !firrtl.uint<32>, in %v2: !firrtl.uint<32>, in %v1: !firrtl.uint<32>, in %v0: !firrtl.uint<32>, out %out1: !firrtl.uint<32>, out %out2: !firrtl.uint<32>) attributes {convention = #firrtl.convention} { %0 = firrtl.int.mux2cell(%sel1, %v1, %v0) : (!firrtl.uint<1>, !firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32> firrtl.matchingconnect %out1, %0 : !firrtl.uint<32> // CHECK-NEXT: %mux2cell_in0 = hw.wire %sel1 sym @{{.+}} : i1 @@ -1550,7 +1550,7 @@ firrtl.circuit "TypeAlias" { firrtl.circuit "Issue5011" { // CHECK-LABEL: module @Issue5011( // CHECK-NOT: exportPort - firrtl.module @Issue5011(in %clock: !firrtl.clock, in %unused: !firrtl.uint<0>, out %out: !firrtl.uint<5> [{class = "firrtl.transforms.DontTouchAnnotation"}]) attributes {convention = #firrtl} { + firrtl.module @Issue5011(in %clock: !firrtl.clock, in %unused: !firrtl.uint<0>, out %out: !firrtl.uint<5> [{class = "firrtl.transforms.DontTouchAnnotation"}]) attributes {convention = #firrtl.convention} { // CHECK: %[[OUT:.+]] = hw.wire %{{.+}} sym @ %c1_ui1 = firrtl.constant 1 : !firrtl.uint<1> %c1_ui5 = firrtl.constant 1 : !firrtl.uint<5> @@ -1567,7 +1567,7 @@ firrtl.circuit "Issue5011" { firrtl.circuit "Issue5011Sym" { // CHECK-LABEL: module @Issue5011Sym( // CHECK-NOT: exportPort - firrtl.module @Issue5011Sym(in %clock: !firrtl.clock, out %out: !firrtl.uint<5> sym @out_sym) attributes {convention = #firrtl} { + firrtl.module @Issue5011Sym(in %clock: !firrtl.clock, out %out: !firrtl.uint<5> sym @out_sym) attributes {convention = #firrtl.convention} { // CHECK: %[[OUT:.+]] = hw.wire %{{.+}} sym @out_sym %c1_ui1 = firrtl.constant 1 : !firrtl.uint<1> %c1_ui5 = firrtl.constant 1 : !firrtl.uint<5> @@ -1632,7 +1632,7 @@ firrtl.circuit "PortSym" { // CHECK-LABEL: module @PortSym( // CHECK-SAME: out a : i1 {hw.exportPort = #hw} // CHECK-SAME: out out : i5, in %c : i1) - firrtl.module @PortSym(out %a: !firrtl.uint<1> sym @out_a_m, in %b: !firrtl.uint<0>, out %out: !firrtl.uint<5> sym @out_sym, in %c: !firrtl.uint<1>) attributes {convention = #firrtl} { + firrtl.module @PortSym(out %a: !firrtl.uint<1> sym @out_a_m, in %b: !firrtl.uint<0>, out %out: !firrtl.uint<5> sym @out_sym, in %c: !firrtl.uint<1>) attributes {convention = #firrtl.convention} { // CHECK: %[[OUT:.+]] = hw.wire %{{.+}} sym @out_sym %c1_ui1 = firrtl.constant 1 : !firrtl.uint<1> %c1_ui5 = firrtl.constant 1 : !firrtl.uint<5> diff --git a/test/Conversion/FIRRTLToHW/zero-width.mlir b/test/Conversion/FIRRTLToHW/zero-width.mlir index 355be5eaaac2..89cb2576b78b 100644 --- a/test/Conversion/FIRRTLToHW/zero-width.mlir +++ b/test/Conversion/FIRRTLToHW/zero-width.mlir @@ -82,7 +82,7 @@ firrtl.circuit "Arithmetic" { // Check that a zero-width value shifted right produces a zero. // See: https://github.com/llvm/circt/issues/6652 // CHECK-LABEL: hw.module @ShrZW - firrtl.module @ShrZW(in %x: !firrtl.uint<0>, out %out: !firrtl.uint<1>) attributes {convention = #firrtl} { + firrtl.module @ShrZW(in %x: !firrtl.uint<0>, out %out: !firrtl.uint<1>) attributes {convention = #firrtl.convention} { %0 = firrtl.shr %x, 5 : (!firrtl.uint<0>) -> !firrtl.uint<0> firrtl.connect %out, %0 : !firrtl.uint<1>, !firrtl.uint<0> // CHECK: %[[false:.+]] = hw.constant false diff --git a/test/Dialect/FIRRTL/annotations.mlir b/test/Dialect/FIRRTL/annotations.mlir index 0f3e6cbe2059..3adf2fba9535 100644 --- a/test/Dialect/FIRRTL/annotations.mlir +++ b/test/Dialect/FIRRTL/annotations.mlir @@ -734,10 +734,28 @@ firrtl.circuit "Test" attributes {rawAnnotations = [ // ----- firrtl.circuit "Test" attributes {rawAnnotations =[ - {class = "circt.ConventionAnnotation", target = "~Test|Test", convention = "scalarized"} + {class = "circt.ConventionAnnotation", target = "~Test|Test", portConvention = "scalarized", bodyConvention = "scalarized"} ]} { - // CHECK: attributes {convention = #firrtl} - firrtl.module @Test() attributes {convention = #firrtl} {} + // CHECK: attributes {convention = #firrtl.convention} + firrtl.module @Test() attributes {convention = #firrtl.convention} {} +} + +// ----- + +firrtl.circuit "Test" attributes {rawAnnotations =[ + {class = "circt.ConventionAnnotation", target = "~Test|Test", portConvention = "scalarized", + bodyConvention = "internal", includeHierarchy = true} + ]} { + // CHECK: @Test() attributes {convention = #firrtl.convention} + firrtl.module @Test() attributes {convention = #firrtl.convention} { + firrtl.instance child @Child() + } + + // CHECK: @Child() attributes {convention = #firrtl.convention} + firrtl.module @Child() attributes {convention = #firrtl.convention} {} + + // CHECK: @Child2() { + firrtl.module @Child2() attributes {convention = #firrtl.convention} {} } // ----- diff --git a/test/Dialect/FIRRTL/canonicalization.mlir b/test/Dialect/FIRRTL/canonicalization.mlir index 388fbe9057d9..81d1e2b004a4 100644 --- a/test/Dialect/FIRRTL/canonicalization.mlir +++ b/test/Dialect/FIRRTL/canonicalization.mlir @@ -3374,7 +3374,7 @@ firrtl.module @RefTypes( // Do not rename InstanceOp: https://github.com/llvm/circt/issues/5351 firrtl.extmodule @System(out foo: !firrtl.uint<1>) -firrtl.module @DonotUpdateInstanceName(in %in: !firrtl.uint<1>, out %a: !firrtl.uint<1>) attributes {convention = #firrtl} { +firrtl.module @DonotUpdateInstanceName(in %in: !firrtl.uint<1>, out %a: !firrtl.uint<1>) attributes {convention = #firrtl.convention} { %system_foo = firrtl.instance system @System(out foo: !firrtl.uint<1>) // CHECK: firrtl.instance system %b = firrtl.node %system_foo : !firrtl.uint<1> @@ -3393,7 +3393,7 @@ firrtl.module private @RefCastSame(in %in: !firrtl.uint<1>, out %out: !firrtl.pr } // CHECK-LABEL: @Issue5527 -firrtl.module @Issue5527(in %x: !firrtl.uint<1>, out %out: !firrtl.uint<2>) attributes {convention = #firrtl} { +firrtl.module @Issue5527(in %x: !firrtl.uint<1>, out %out: !firrtl.uint<2>) attributes {convention = #firrtl.convention} { %0 = firrtl.cvt %x : (!firrtl.uint<1>) -> !firrtl.sint<2> %c2_si4 = firrtl.constant 2 : !firrtl.sint<4> %1 = firrtl.and %0, %c2_si4 : (!firrtl.sint<2>, !firrtl.sint<4>) -> !firrtl.uint<4> diff --git a/test/Dialect/FIRRTL/check-comb-loops.mlir b/test/Dialect/FIRRTL/check-comb-loops.mlir index a36ef485bcb7..58dfdfdef8b3 100644 --- a/test/Dialect/FIRRTL/check-comb-loops.mlir +++ b/test/Dialect/FIRRTL/check-comb-loops.mlir @@ -896,7 +896,7 @@ firrtl.circuit "Bug5442" { firrtl.matchingconnect %c_d, %a : !firrtl.uint<1> } // expected-error @below {{detected combinational cycle in a FIRRTL module, sample path: Bug5442.{bar.a <- baz.b <- baz.a <- bar.b <- bar.a}}} - firrtl.module @Bug5442() attributes {convention = #firrtl} { + firrtl.module @Bug5442() attributes {convention = #firrtl.convention} { %bar_a, %bar_b = firrtl.instance bar @Bar(in a: !firrtl.uint<1>, out b: !firrtl.uint<1>) %baz_a, %baz_b, %baz_c_d = firrtl.instance baz @Baz(in a: !firrtl.uint<1>, out b: !firrtl.uint<1>, out c_d: !firrtl.uint<1>) firrtl.matchingconnect %bar_a, %baz_b : !firrtl.uint<1> @@ -943,7 +943,7 @@ firrtl.circuit "Issue4691" { firrtl.circuit "Issue5462" { // expected-error @below {{detected combinational cycle in a FIRRTL module, sample path: Issue5462.{n.a <- w.a <- n.a}}} - firrtl.module @Issue5462() attributes {convention = #firrtl} { + firrtl.module @Issue5462() attributes {convention = #firrtl.convention} { %w = firrtl.wire : !firrtl.bundle> %n = firrtl.node %w : !firrtl.bundle> %0 = firrtl.subfield %n[a] : !firrtl.bundle> @@ -965,7 +965,7 @@ firrtl.circuit "Issue5462" { firrtl.matchingconnect %3, %2 : !firrtl.uint<1> } // expected-error @below {{detected combinational cycle in a FIRRTL module, sample path: Issue5462.{c.bundle.b <- c.p.b <- c.bundle.b}}} - firrtl.module @Issue5462(in %x: !firrtl.uint<1>) attributes {convention = #firrtl} { + firrtl.module @Issue5462(in %x: !firrtl.uint<1>) attributes {convention = #firrtl.convention} { %c_bundle, %c_p = firrtl.instance c @Child(in bundle: !firrtl.bundle, b: uint<1>>, out p: !firrtl.bundle, b: uint<1>>) %0 = firrtl.subfield %c_p[b] : !firrtl.bundle, b: uint<1>> %1 = firrtl.subfield %c_bundle[b] : !firrtl.bundle, b: uint<1>> @@ -979,7 +979,7 @@ firrtl.circuit "Issue5462" { firrtl.circuit "Issue5462" { // expected-error @below {{detected combinational cycle in a FIRRTL module, sample path: Issue5462.{a <- n.a <- w.a <- a}}} - firrtl.module @Issue5462(in %in_a: !firrtl.uint<8>, out %out_a: !firrtl.uint<8>, in %c: !firrtl.uint<1>) attributes {convention = #firrtl} { + firrtl.module @Issue5462(in %in_a: !firrtl.uint<8>, out %out_a: !firrtl.uint<8>, in %c: !firrtl.uint<1>) attributes {convention = #firrtl.convention} { %w = firrtl.wire : !firrtl.bundle> %n = firrtl.node %w : !firrtl.bundle> %0 = firrtl.bundlecreate %in_a : (!firrtl.uint<8>) -> !firrtl.bundle> @@ -1043,7 +1043,7 @@ firrtl.circuit "Issue6820" { %0 = firrtl.ref.rwprobe <@Foo::@sym> : !firrtl.rwprobe firrtl.ref.define %clockProbe_bore, %0 : !firrtl.rwprobe } - firrtl.module @Issue6820(in %clock: !firrtl.clock, out %clockProbe: !firrtl.rwprobe) attributes {convention = #firrtl} { + firrtl.module @Issue6820(in %clock: !firrtl.clock, out %clockProbe: !firrtl.rwprobe) attributes {convention = #firrtl.convention} { %foo_clock, %foo_clockProbe_bore = firrtl.instance foo @Foo(in clock: !firrtl.clock, out clockProbe_bore: !firrtl.rwprobe) firrtl.matchingconnect %foo_clock, %clock : !firrtl.clock firrtl.ref.define %clockProbe, %foo_clockProbe_bore : !firrtl.rwprobe @@ -1111,7 +1111,7 @@ firrtl.circuit "MultipleConnects" { // ----- firrtl.circuit "DPI" { - firrtl.module @DPI(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, out %out_0: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @DPI(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, out %out_0: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { %in = firrtl.wire : !firrtl.uint<8> %0 = firrtl.int.dpi.call "clocked_result"(%in) clock %clock enable %enable : (!firrtl.uint<8>) -> !firrtl.uint<8> firrtl.matchingconnect %in, %0 : !firrtl.uint<8> @@ -1124,7 +1124,7 @@ firrtl.circuit "DPI" { firrtl.circuit "DPI" { // expected-error @below {{detected combinational cycle in a FIRRTL module, sample path: DPI.{in <- ... <- in}}} - firrtl.module @DPI(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, out %out_0: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @DPI(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, out %out_0: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { %in = firrtl.wire : !firrtl.uint<8> %0 = firrtl.int.dpi.call "unclocked_result"(%in) enable %enable : (!firrtl.uint<8>) -> !firrtl.uint<8> firrtl.matchingconnect %in, %0 : !firrtl.uint<8> diff --git a/test/Dialect/FIRRTL/dedup.mlir b/test/Dialect/FIRRTL/dedup.mlir index 3164cc145dc4..c2c04418df06 100644 --- a/test/Dialect/FIRRTL/dedup.mlir +++ b/test/Dialect/FIRRTL/dedup.mlir @@ -526,7 +526,7 @@ firrtl.circuit "MuxBundle" { %invalid = firrtl.invalidvalue : !firrtl.bundle> firrtl.matchingconnect %o, %invalid : !firrtl.bundle> } - firrtl.module @MuxBundle(in %p: !firrtl.uint<1>, in %l: !firrtl.bundle>, out %o: !firrtl.bundle>) attributes {convention = #firrtl} { + firrtl.module @MuxBundle(in %p: !firrtl.uint<1>, in %l: !firrtl.bundle>, out %o: !firrtl.bundle>) attributes {convention = #firrtl.convention} { // CHECK: %bar0_o = firrtl.instance bar0 @Bar0(out o: !firrtl.bundle>) %bar0_o = firrtl.instance bar0 @Bar0(out o: !firrtl.bundle>) diff --git a/test/Dialect/FIRRTL/errors.mlir b/test/Dialect/FIRRTL/errors.mlir index ebee4d419a70..11f842c4f221 100644 --- a/test/Dialect/FIRRTL/errors.mlir +++ b/test/Dialect/FIRRTL/errors.mlir @@ -71,7 +71,7 @@ firrtl.module @foo(in %a: !firrtl.uint<1> ["hello"]) {} firrtl.circuit "foo" { // expected-error @+1 {{requires one region}} "firrtl.module"() ( { }, { }) - {sym_name = "foo", convention = #firrtl, + {sym_name = "foo", convention = #firrtl.convention, portTypes = [!firrtl.uint], portDirections = array, portNames = ["in0"], portAnnotations = [], portSymbols = []} : () -> () } @@ -82,7 +82,7 @@ firrtl.circuit "foo" { // expected-error @+1 {{'firrtl.module' op requires attribute 'portLocations'}} "firrtl.module"() ( { ^entry: -}) { sym_name = "foo", convention = #firrtl, +}) { sym_name = "foo", convention = #firrtl.convention, portTypes = [!firrtl.uint], portDirections = array, portNames = ["in0"], portAnnotations = [], portSymbols = []} : () -> () } @@ -93,7 +93,7 @@ firrtl.circuit "foo" { // expected-error @+1 {{requires 1 port locations}} "firrtl.module"() ( { ^entry: -}) {sym_name = "foo", convention = #firrtl, +}) {sym_name = "foo", convention = #firrtl.convention, portTypes = [!firrtl.uint], portDirections = array, portNames = ["in0"], portAnnotations = [], portSymbols = [], portLocations = []} : () -> () @@ -108,7 +108,7 @@ firrtl.circuit "foo" { // expected-error @+1 {{entry block must have 1 arguments to match module signature}} "firrtl.module"() ( { ^entry: -}) {sym_name = "foo", convention = #firrtl, +}) {sym_name = "foo", convention = #firrtl.convention, portTypes = [!firrtl.uint], portDirections = array, portNames = ["in0"], portAnnotations = [], portSymbols = [], portLocations = [loc("loc")]} : () -> () @@ -120,7 +120,7 @@ firrtl.circuit "foo" { // expected-error @+1 {{block argument types should match signature types}} "firrtl.module"() ( { ^entry(%a: i1): -}) {sym_name = "foo", convention = #firrtl, +}) {sym_name = "foo", convention = #firrtl.convention, portTypes = [!firrtl.uint], portDirections = array, portNames = ["in0"], portAnnotations = [], portSymbols = [], portLocations = [loc("foo")]} : () -> () diff --git a/test/Dialect/FIRRTL/imconstprop.mlir b/test/Dialect/FIRRTL/imconstprop.mlir index e908d5de698b..fbc1966d3fe6 100644 --- a/test/Dialect/FIRRTL/imconstprop.mlir +++ b/test/Dialect/FIRRTL/imconstprop.mlir @@ -722,7 +722,7 @@ firrtl.circuit "ObjectConnect" { // Preserve forceable decl that is dead other than its rwprobe result. // CHECK-LABEL: "KeepForceable" firrtl.circuit "KeepForceable" { - firrtl.module @KeepForceable(out %a: !firrtl.rwprobe>) attributes {convention = #firrtl} { + firrtl.module @KeepForceable(out %a: !firrtl.rwprobe>) attributes {convention = #firrtl.convention} { %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1> %b_c = firrtl.wire : !firrtl.rwprobe> %d, %d_ref = firrtl.wire forceable : !firrtl.uint<1>, !firrtl.rwprobe> diff --git a/test/Dialect/FIRRTL/imdce.mlir b/test/Dialect/FIRRTL/imdce.mlir index ad8fe3f82b13..03f3adcf6758 100644 --- a/test/Dialect/FIRRTL/imdce.mlir +++ b/test/Dialect/FIRRTL/imdce.mlir @@ -442,7 +442,7 @@ firrtl.circuit "Test" { %extmodule_out = firrtl.instance extmodule @ExtModule(out out : !firrtl.uint<1>) firrtl.matchingconnect %out, %extmodule_out : !firrtl.uint<1> } - firrtl.module @Test() attributes {convention = #firrtl} { + firrtl.module @Test() attributes {convention = #firrtl.convention} { // CHECK: firrtl.instance blah interesting_name @Blah() %blah_out = firrtl.instance blah interesting_name @Blah(out out : !firrtl.uint<1>) } @@ -487,8 +487,8 @@ firrtl.circuit "Test" { // The write to %o's "in" port is preserved by IMDCE, even though the input // is unused by the class. - // CHECK: firrtl.module @Test() attributes {convention = #firrtl} - firrtl.module @Test() attributes {convention = #firrtl} { + // CHECK: firrtl.module @Test() attributes {convention = #firrtl.convention} + firrtl.module @Test() attributes {convention = #firrtl.convention} { // CHECK: %0 = firrtl.integer 456 // CHECK: %o = firrtl.object @Class(in in: !firrtl.integer, out out: !firrtl.integer) // CHECK: %1 = firrtl.object.subfield %o[in] : !firrtl.class<@Class(in in: !firrtl.integer, out out: !firrtl.integer)> @@ -508,8 +508,8 @@ module { // CHECK: firrtl.extclass private @Class(out out_str: !firrtl.string, in in_str: !firrtl.string) firrtl.extclass private @Class(out out_str: !firrtl.string, in in_str: !firrtl.string) - // CHECK: firrtl.module @Test(out %out_str: !firrtl.string) attributes {convention = #firrtl} - firrtl.module @Test(out %out_str: !firrtl.string) attributes {convention = #firrtl} { + // CHECK: firrtl.module @Test(out %out_str: !firrtl.string) attributes {convention = #firrtl.convention} + firrtl.module @Test(out %out_str: !firrtl.string) attributes {convention = #firrtl.convention} { // CHECK: %0 = firrtl.string "whatever" // CHECK: %obj = firrtl.object @Class(out out_str: !firrtl.string, in in_str: !firrtl.string) // CHECK: %1 = firrtl.object.subfield %obj[out_str] : !firrtl.class<@Class(out out_str: !firrtl.string, in in_str: !firrtl.string)> diff --git a/test/Dialect/FIRRTL/infer-resets.mlir b/test/Dialect/FIRRTL/infer-resets.mlir index 9a64ea1265fc..d4005c263593 100644 --- a/test/Dialect/FIRRTL/infer-resets.mlir +++ b/test/Dialect/FIRRTL/infer-resets.mlir @@ -861,7 +861,7 @@ firrtl.circuit "top" { } // CHECK: firrtl.module @top // CHECK-SAME: annotations = [{class = "circt.FullResetAnnotation"}] - firrtl.module @top(in %clock: !firrtl.clock, in %reset: !firrtl.asyncreset [{class = "circt.FullResetAnnotation", resetType = "async"}], in %in: !firrtl.uint<8>, out %out: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @top(in %clock: !firrtl.clock, in %reset: !firrtl.asyncreset [{class = "circt.FullResetAnnotation", resetType = "async"}], in %in: !firrtl.uint<8>, out %out: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { %child_clock, %child_reset, %child_in, %child_out = firrtl.instance child @test(in clock: !firrtl.clock, in reset: !firrtl.asyncreset, in in: !firrtl.uint<8>, out out: !firrtl.uint<8>) firrtl.matchingconnect %child_clock, %clock : !firrtl.clock firrtl.matchingconnect %child_reset, %reset : !firrtl.asyncreset diff --git a/test/Dialect/FIRRTL/inferRW.mlir b/test/Dialect/FIRRTL/inferRW.mlir index c7347840faef..fb3ca0d7c07f 100644 --- a/test/Dialect/FIRRTL/inferRW.mlir +++ b/test/Dialect/FIRRTL/inferRW.mlir @@ -304,7 +304,7 @@ firrtl.circuit "TLRAM" { } // CHECK: firrtl.module @InferUnmasked - firrtl.module @InferUnmasked(in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>) attributes {convention = #firrtl} { + firrtl.module @InferUnmasked(in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>) attributes {convention = #firrtl.convention} { %readwritePortA_isWrite_2 = firrtl.wire {name = "readwritePortA_isWrite"} : !firrtl.uint<1> %syncreadmem_singleport_readwritePortA_readData_rw = firrtl.mem Undefined {depth = 64 : i64, name = "syncreadmem_singleport", portNames = ["readwritePortA_readData_rw"], readLatency = 1 : i32, writeLatency = 1 : i32} : !firrtl.bundle, en: uint<1>, clk: clock, rdata flip: uint<10>, wmode: uint<1>, wdata: uint<10>, wmask: uint<5>> // CHECK: %syncreadmem_singleport_readwritePortA_readData_rw = firrtl.mem Undefined {depth = 64 : i64, name = "syncreadmem_singleport", portNames = ["readwritePortA_readData_rw"], readLatency = 1 : i32, writeLatency = 1 : i32} : !firrtl.bundle, en: uint<1>, clk: clock, rdata flip: uint<10>, wmode: uint<1>, wdata: uint<10>, wmask: uint<1>> diff --git a/test/Dialect/FIRRTL/inliner-errors.mlir b/test/Dialect/FIRRTL/inliner-errors.mlir index c4a557f19e47..a57b75675f00 100644 --- a/test/Dialect/FIRRTL/inliner-errors.mlir +++ b/test/Dialect/FIRRTL/inliner-errors.mlir @@ -81,7 +81,7 @@ firrtl.circuit "InlineLayerIntoLayer" { } } } - firrtl.module @InlineLayerIntoLayer(in %i: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @InlineLayerIntoLayer(in %i: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { // expected-note @below {{illegal parent op defined here}} firrtl.layerblock @I { %c_i = firrtl.instance c interesting_name @MatchAgain(in i: !firrtl.uint<8>) diff --git a/test/Dialect/FIRRTL/inliner.mlir b/test/Dialect/FIRRTL/inliner.mlir index 8a1dca859451..675f58622f31 100644 --- a/test/Dialect/FIRRTL/inliner.mlir +++ b/test/Dialect/FIRRTL/inliner.mlir @@ -1113,7 +1113,7 @@ firrtl.circuit "RWProbePort" { firrtl.module @RWProbePort(in %in_0: !firrtl.uint<1>, in %in_1: !firrtl.uint<1>, out %p_0: !firrtl.rwprobe>, - out %p_1: !firrtl.rwprobe>) attributes {convention = #firrtl} { + out %p_1: !firrtl.rwprobe>) attributes {convention = #firrtl.convention} { // CHECK-NEXT: %[[C1_IN:.+]] = firrtl.wire sym [<@[[C1_IN_SYM:.+]],2,public>] // CHECK-NEXT: %[[C1_P_WIRE:.+]] = firrtl.wire : !firrtl.rwprobe> @@ -1391,7 +1391,7 @@ firrtl.circuit "InlineBlocks" { } } // CHECK: @InlineBlocks - firrtl.module @InlineBlocks(in %i: !firrtl.enum, None: uint<0>>, in %cond: !firrtl.uint<1>, out %o: !firrtl.probe, @I::@J>) attributes {convention = #firrtl} { + firrtl.module @InlineBlocks(in %i: !firrtl.enum, None: uint<0>>, in %cond: !firrtl.uint<1>, out %o: !firrtl.probe, @I::@J>) attributes {convention = #firrtl.convention} { // Check inlined structure. // CHECK: layerblock @I // CHECK-NEXT: firrtl.when diff --git a/test/Dialect/FIRRTL/lower-classes.mlir b/test/Dialect/FIRRTL/lower-classes.mlir index 234438f92465..ce760cdb1e89 100644 --- a/test/Dialect/FIRRTL/lower-classes.mlir +++ b/test/Dialect/FIRRTL/lower-classes.mlir @@ -90,7 +90,7 @@ firrtl.circuit "Component" { firrtl.propassign %obj_a, %x : !firrtl.integer } - firrtl.module @Component(in %input: !firrtl.uint<1>, out %output: !firrtl.uint<1>, out %omir_out: !firrtl.class<@ClassEntrypoint(out obj_0_out: !firrtl.class<@Class_1(out someInt: !firrtl.integer)>)>) attributes {convention = #firrtl} { + firrtl.module @Component(in %input: !firrtl.uint<1>, out %output: !firrtl.uint<1>, out %omir_out: !firrtl.class<@ClassEntrypoint(out obj_0_out: !firrtl.class<@Class_1(out someInt: !firrtl.integer)>)>) attributes {convention = #firrtl.convention} { %0 = firrtl.object @ClassEntrypoint(out obj_0_out: !firrtl.class<@Class_1(out someInt: !firrtl.integer)>) firrtl.propassign %omir_out, %0 : !firrtl.class<@ClassEntrypoint(out obj_0_out: !firrtl.class<@Class_1(out someInt: !firrtl.integer)>)> firrtl.matchingconnect %output, %input : !firrtl.uint<1> @@ -226,7 +226,7 @@ firrtl.circuit "PathModule" { %module_path = firrtl.path reference distinct[5]<> } // CHECK: -> (propOut: !om.list) - firrtl.module @ListCreate(in %propIn: !firrtl.integer, out %propOut: !firrtl.list) attributes {convention = #firrtl} { + firrtl.module @ListCreate(in %propIn: !firrtl.integer, out %propOut: !firrtl.list) attributes {convention = #firrtl.convention} { %0 = firrtl.integer 123 %1 = firrtl.list.create %propIn, %0 : !firrtl.list firrtl.propassign %propOut, %1 : !firrtl.list @@ -249,7 +249,7 @@ firrtl.circuit "WireProp" { // CHECK: om.class @WireProp // CHECK-SAME: %[[IN:[^ ]+]]: !om.string // CHECK-SAME: -> (out: !om.string) - firrtl.module @WireProp(in %in: !firrtl.string, out %out: !firrtl.string) attributes {convention = #firrtl} { + firrtl.module @WireProp(in %in: !firrtl.string, out %out: !firrtl.string) attributes {convention = #firrtl.convention} { // CHECK-NOT: firrtl.wire // CHECK-NOT: firrtl.propassign // CHECK: om.class.fields %[[IN]] : !om.string @@ -420,14 +420,14 @@ firrtl.circuit "AltBasePath" { } // CHECK: om.class @DUT_Class(%basepath: !om.basepath, %alt_basepath_0: !om.basepath) - firrtl.module @DUT(out %omirOut: !firrtl.class<@OMIR()>) attributes {convention = #firrtl} { + firrtl.module @DUT(out %omirOut: !firrtl.class<@OMIR()>) attributes {convention = #firrtl.convention} { // CHECK: om.object @OMIR(%basepath, %alt_basepath_0) %omir = firrtl.object @OMIR() firrtl.propassign %omirOut, %omir : !firrtl.class<@OMIR()> } // CHECK: om.class @AltBasePath_Class(%basepath: !om.basepath) - firrtl.module @AltBasePath() attributes {convention = #firrtl} { + firrtl.module @AltBasePath() attributes {convention = #firrtl.convention} { // CHECK: om.object @DUT_Class(%0, %basepath) %dut_omirOut = firrtl.instance dut interesting_name @DUT(out omirOut: !firrtl.class<@OMIR()>) firrtl.instance foo interesting_name {annotations = [{class = "circt.tracker", id = distinct[0]<>}]} @Foo() diff --git a/test/Dialect/FIRRTL/lower-dpi-error.mlir b/test/Dialect/FIRRTL/lower-dpi-error.mlir index d280d0a7c7e1..b21eb41f4223 100644 --- a/test/Dialect/FIRRTL/lower-dpi-error.mlir +++ b/test/Dialect/FIRRTL/lower-dpi-error.mlir @@ -2,7 +2,7 @@ // CHECK-LABEL: firrtl.circuit "DPI" { firrtl.circuit "DPI" { - firrtl.module @DPI(in %in_0: !firrtl.uint<8>, in %in_1: !firrtl.uint<16>) attributes {convention = #firrtl} { + firrtl.module @DPI(in %in_0: !firrtl.uint<8>, in %in_1: !firrtl.uint<16>) attributes {convention = #firrtl.convention} { // expected-error @below {{firrtl.int.dpi.call' op DPI function "foo" input types don't match}} firrtl.int.dpi.call "foo"(%in_0) : (!firrtl.uint<8>) -> () // expected-note @below {{mismatched caller is here}} @@ -14,7 +14,7 @@ firrtl.circuit "DPI" { // CHECK-LABEL: firrtl.circuit "DPI" { firrtl.circuit "DPI" { - firrtl.module @DPI(in %in_0: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @DPI(in %in_0: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { // expected-error @below {{firrtl.int.dpi.call' op DPI function "foo" output types don't match}} %0 = firrtl.int.dpi.call "foo"(%in_0) : (!firrtl.uint<8>) -> (!firrtl.uint<16>) // expected-note @below {{mismatched caller is here}} diff --git a/test/Dialect/FIRRTL/lower-dpi.mlir b/test/Dialect/FIRRTL/lower-dpi.mlir index 63105c884330..cd7868ed3f9c 100644 --- a/test/Dialect/FIRRTL/lower-dpi.mlir +++ b/test/Dialect/FIRRTL/lower-dpi.mlir @@ -6,7 +6,7 @@ firrtl.circuit "DPI" { // CHECK-NEXT: sim.func.dpi private @clocked_void(in %in_0 : i8, in %in_1 : i8) attributes {verilogName = "clocked_void"} // CHECK-NEXT: sim.func.dpi private @clocked_result(in %foo : i8, in %bar : i8, out baz : i8) attributes {verilogName = "clocked_result"} // CHECK-LABEL: firrtl.module @DPI - firrtl.module @DPI(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, in %in_0: !firrtl.uint<8>, in %in_1: !firrtl.uint<8>, out %out_0: !firrtl.uint<8>, out %out_1: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @DPI(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, in %in_0: !firrtl.uint<8>, in %in_1: !firrtl.uint<8>, out %out_0: !firrtl.uint<8>, out %out_1: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { // CHECK-NEXT: %0 = builtin.unrealized_conversion_cast %clock : !firrtl.clock to !seq.clock // CHECK-NEXT: %1 = builtin.unrealized_conversion_cast %enable : !firrtl.uint<1> to i1 // CHECK-NEXT: %2 = builtin.unrealized_conversion_cast %in_0 : !firrtl.uint<8> to i8 @@ -33,7 +33,7 @@ firrtl.circuit "DPI" { } // CHECK-LABEL: firrtl.module @DPISignature - firrtl.module @DPISignature(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, in %in_0: !firrtl.uint<8>, in %in_1: !firrtl.uint<8>) attributes {convention = #firrtl} { + firrtl.module @DPISignature(in %clock: !firrtl.clock, in %enable: !firrtl.uint<1>, in %in_0: !firrtl.uint<8>, in %in_1: !firrtl.uint<8>) attributes {convention = #firrtl.convention} { // CHECK: call @clocked_void // CHECK: call @clocked_void firrtl.int.dpi.call "clocked_void"(%in_0, %in_1) clock %clock enable %enable : (!firrtl.uint<8>, !firrtl.uint<8>) -> () diff --git a/test/Dialect/FIRRTL/lower-layers.mlir b/test/Dialect/FIRRTL/lower-layers.mlir index afff6be5e8c6..b41a74d1d269 100644 --- a/test/Dialect/FIRRTL/lower-layers.mlir +++ b/test/Dialect/FIRRTL/lower-layers.mlir @@ -743,7 +743,7 @@ firrtl.circuit "Foo" { // CHECK-LABEL: circuit "RWTH" firrtl.circuit "RWTH" { firrtl.layer @T bind { } - firrtl.module @RWTH() attributes {convention = #firrtl, layers = [@T]} { + firrtl.module @RWTH() attributes {convention = #firrtl.convention, layers = [@T]} { %d_p = firrtl.instance d @DUT(out p: !firrtl.rwprobe, @T>) %one = firrtl.constant 1 : !firrtl.uint<1> firrtl.ref.force_initial %one, %d_p, %one: !firrtl.uint<1>, !firrtl.rwprobe, @T>, !firrtl.uint<1> @@ -753,12 +753,12 @@ firrtl.circuit "RWTH" { // CHECK-NEXT: %0 = firrtl.ref.rwprobe <@DUT_T::@[[SYM]]> : !firrtl.rwprobe> // CHECK-NEXT: firrtl.ref.define %p, %0 : !firrtl.rwprobe> // CHECK-NEXT: } -// CHECK-NEXT: firrtl.module @DUT(out %p: !firrtl.rwprobe>) attributes {convention = #firrtl} { +// CHECK-NEXT: firrtl.module @DUT(out %p: !firrtl.rwprobe>) attributes {convention = #firrtl.convention} { // CHECK-NEXT: %t_p = firrtl.instance t sym @t {lowerToBind, output_file = #hw.output_file<"layers-RWTH-T.sv", excludeFromFileList>} @DUT_T(out p: !firrtl.rwprobe>) // CHECK-NEXT: firrtl.ref.define %p, %t_p : !firrtl.rwprobe> // CHECK-NEXT: } - firrtl.module @DUT(out %p: !firrtl.rwprobe, @T>) attributes {convention = #firrtl} { + firrtl.module @DUT(out %p: !firrtl.rwprobe, @T>) attributes {convention = #firrtl.convention} { firrtl.layerblock @T { %w = firrtl.wire sym @sym : !firrtl.uint<1> %0 = firrtl.ref.rwprobe <@DUT::@sym> : !firrtl.rwprobe> diff --git a/test/Dialect/FIRRTL/lower-open-aggs.mlir b/test/Dialect/FIRRTL/lower-open-aggs.mlir index 54eba20fbacd..db8f5c726ad7 100644 --- a/test/Dialect/FIRRTL/lower-open-aggs.mlir +++ b/test/Dialect/FIRRTL/lower-open-aggs.mlir @@ -66,7 +66,7 @@ firrtl.circuit "Bundle" { firrtl.ref.define %2, %c2_r : !firrtl.probe, b: vector, 2>>> } // CHECK-LABEL: module @Bundle - firrtl.module @Bundle(in %in: !firrtl.bundle, b: vector, 2>>, out %out1: !firrtl.bundle, b: vector, 2>>, out %out2: !firrtl.bundle, b: vector, 2>>, out %out3: !firrtl.bundle, b: vector, 2>>, out %out4: !firrtl.bundle, b: vector, 2>>, out %out5: !firrtl.bundle, b: vector, 2>>, out %out6: !firrtl.bundle, b: vector, 2>>, out %out7: !firrtl.bundle, b: vector, 2>>) attributes {convention = #firrtl} { + firrtl.module @Bundle(in %in: !firrtl.bundle, b: vector, 2>>, out %out1: !firrtl.bundle, b: vector, 2>>, out %out2: !firrtl.bundle, b: vector, 2>>, out %out3: !firrtl.bundle, b: vector, 2>>, out %out4: !firrtl.bundle, b: vector, 2>>, out %out5: !firrtl.bundle, b: vector, 2>>, out %out6: !firrtl.bundle, b: vector, 2>>, out %out7: !firrtl.bundle, b: vector, 2>>) attributes {convention = #firrtl.convention} { %0 = firrtl.subfield %out7[b] : !firrtl.bundle, b: vector, 2>> %1 = firrtl.subfield %out7[a] : !firrtl.bundle, b: vector, 2>> %p_in, %p_r, %p_mixed, %p_nohw = firrtl.instance p interesting_name @Probe(in in: !firrtl.bundle, b: vector, 2>>, out r: !firrtl.openbundle, b: vector, 2>>>, b: probe, b: vector, 2>>>>, out mixed: !firrtl.openbundle, x flip: openvector, b: vector, 2>>>, data flip: uint<1>>, 2>, b: vector, 2>>, out nohw: !firrtl.openbundle, b: vector, 2>>>>, 2>>) @@ -105,7 +105,7 @@ firrtl.circuit "Bundle" { firrtl.extmodule @ExtProbes( out r: !firrtl.openbundle, b: vector, 2>>>, b: probe, b: vector, 2>>>>, out mixed: !firrtl.openbundle, x flip: openvector, b: vector, 2>>>, data flip: uint<1>>, 2>, b: vector, 2>>, - out nohw: !firrtl.openbundle, b: vector, 2>>>>, 2>>) attributes {convention = #firrtl} + out nohw: !firrtl.openbundle, b: vector, 2>>>>, 2>>) attributes {convention = #firrtl.convention} } // ----- @@ -126,7 +126,7 @@ firrtl.circuit "RefsOnlyAggFirstLevel" { firrtl.ref.define %3, %6 : !firrtl.probe> } // CHECK-LABEL: module @RefsOnlyAggFirstLevel( - firrtl.module @RefsOnlyAggFirstLevel(in %x: !firrtl.uint<5>, in %y: !firrtl.uint<1>, out %out: !firrtl.openbundle>, y: probe>>) attributes {convention = #firrtl} { + firrtl.module @RefsOnlyAggFirstLevel(in %x: !firrtl.uint<5>, in %y: !firrtl.uint<1>, out %out: !firrtl.openbundle>, y: probe>>) attributes {convention = #firrtl.convention} { %0 = firrtl.opensubfield %out[y] : !firrtl.openbundle>, y: probe>> %1 = firrtl.opensubfield %out[x] : !firrtl.openbundle>, y: probe>> // CHECK: firrtl.instance c interesting_name @Child(in foo: !firrtl.bundle, y: uint<1>>, out foo_refs_x: !firrtl.probe>, out foo_refs_y: !firrtl.probe>) diff --git a/test/Dialect/FIRRTL/lower-signatures-error.mlir b/test/Dialect/FIRRTL/lower-signatures-error.mlir index 67de1ce38727..44fdb8932461 100644 --- a/test/Dialect/FIRRTL/lower-signatures-error.mlir +++ b/test/Dialect/FIRRTL/lower-signatures-error.mlir @@ -4,7 +4,7 @@ firrtl.circuit "InnerSym" { // expected-error @below {{Port ["x"] should be subdivided, but cannot be because of symbol ["x"] on a bundle}} firrtl.module @InnerSym( in %x: !firrtl.bundle, b: uint<3>> sym [<@x,0,public>] - ) attributes {convention = #firrtl} { } + ) attributes {convention = #firrtl.convention} { } } // ----- @@ -13,5 +13,5 @@ firrtl.circuit "InnerSymMore" { //expected-error @below {{Port ["x"] should be subdivided, but cannot be because of symbol ["y"] on a vector}} firrtl.module @InnerSymMore( in %x: !firrtl.vector, 4> sym [<@y,0, public>] - ) attributes {convention = #firrtl} { } + ) attributes {convention = #firrtl.convention} { } } diff --git a/test/Dialect/FIRRTL/lower-signatures.mlir b/test/Dialect/FIRRTL/lower-signatures.mlir index 43b8e17a3510..b209352f8ef4 100644 --- a/test/Dialect/FIRRTL/lower-signatures.mlir +++ b/test/Dialect/FIRRTL/lower-signatures.mlir @@ -3,13 +3,13 @@ firrtl.circuit "Prop" { // CHECK-LABEL @Prop(out %y: !firrtl.string) - firrtl.module @Prop(out %y: !firrtl.string) attributes {convention = #firrtl} { + firrtl.module @Prop(out %y: !firrtl.string) attributes {convention = #firrtl.convention} { %0 = firrtl.string "test" // CHECK: firrtl.propassign firrtl.propassign %y, %0 : !firrtl.string } - firrtl.module private @emptyVec(in %vi : !firrtl.vector, 0>, out %vo : !firrtl.vector, 0>) attributes {convention = #firrtl} { + firrtl.module private @emptyVec(in %vi : !firrtl.vector, 0>, out %vo : !firrtl.vector, 0>) attributes {convention = #firrtl.convention} { firrtl.matchingconnect %vo, %vi : !firrtl.vector, 0> } @@ -20,12 +20,12 @@ firrtl.circuit "Prop" { firrtl.module private @Annos( in %x: !firrtl.uint<1> [{circt.fieldID = 0 : i64, class = "circt.test", pin = "pin0"}], in %y: !firrtl.bundle, b: uint<2>> [{circt.fieldID = 2 : i64, class = "circt.test", pin = "pin2"}, {circt.fieldID = 1 : i64, class = "circt.test", pin = "pin1"}] - ) attributes {convention = #firrtl} { + ) attributes {convention = #firrtl.convention} { } // CHECK-LABEL: @AnalogBlackBox - firrtl.extmodule private @AnalogBlackBox(out bus: !firrtl.analog<32>) attributes {convention = #firrtl, defname = "AnalogBlackBox"} - firrtl.module @AnalogBlackBoxModule(out %io: !firrtl.bundle>) attributes {convention = #firrtl} { + firrtl.extmodule private @AnalogBlackBox(out bus: !firrtl.analog<32>) attributes {convention = #firrtl.convention, defname = "AnalogBlackBox"} + firrtl.module @AnalogBlackBoxModule(out %io: !firrtl.bundle>) attributes {convention = #firrtl.convention} { // CHECK: %io = firrtl.wire interesting_name : !firrtl.bundle> // CHECK: %0 = firrtl.subfield %io[bus] : !firrtl.bundle> // CHECK: firrtl.attach %0, %io_bus : !firrtl.analog<32>, !firrtl.analog<32> @@ -35,14 +35,14 @@ firrtl.circuit "Prop" { } // CHECK-LABEL: firrtl.module private @Bar - firrtl.module private @Bar(out %in1: !firrtl.bundle, b flip: uint<1>>, in %in2: !firrtl.bundle>, in %out: !firrtl.bundle, e flip: uint<1>>) attributes {convention = #firrtl} { + firrtl.module private @Bar(out %in1: !firrtl.bundle, b flip: uint<1>>, in %in2: !firrtl.bundle>, in %out: !firrtl.bundle, e flip: uint<1>>) attributes {convention = #firrtl.convention} { // CHECK-NEXT: %in1 = firrtl.wire // CHECK-NEXT: %in2 = firrtl.wire // CHECK-NEXT: %out = firrtl.wire } // CHECK-LABEL: firrtl.module private @Foo - firrtl.module private @Foo() attributes {convention = #firrtl} { + firrtl.module private @Foo() attributes {convention = #firrtl.convention} { %bar_in1, %bar_in2, %bar_out = firrtl.instance bar interesting_name @Bar(out in1: !firrtl.bundle, b flip: uint<1>>, in in2: !firrtl.bundle>, in out: !firrtl.bundle, e flip: uint<1>>) // CHECK: %bar.in1 = firrtl.wire // CHECK: %bar.in2 = firrtl.wire @@ -83,7 +83,7 @@ firrtl.circuit "InternalPaths" { out array : !firrtl.vector, 2>, out probe : !firrtl.probe> ) attributes { - convention = #firrtl, + convention = #firrtl.convention, internalPaths = [ #firrtl.internalpath, #firrtl.internalpath, diff --git a/test/Dialect/FIRRTL/lower-types-aggregate.mlir b/test/Dialect/FIRRTL/lower-types-aggregate.mlir index 58ae36477c23..297075fab1a9 100644 --- a/test/Dialect/FIRRTL/lower-types-aggregate.mlir +++ b/test/Dialect/FIRRTL/lower-types-aggregate.mlir @@ -19,14 +19,14 @@ firrtl.circuit "TopLevel" { // PRESERVE_1D_VEC: @InternalModule1(in %port: !firrtl.vector, 2>) // PRESERVE_NONE: @InternalModule1(in %port_0: !firrtl.uint<8>, in %port_1: !firrtl.uint<8>) firrtl.module @InternalModule1(in %port: !firrtl.vector, 2>) - attributes {convention = #firrtl} {} + attributes {convention = #firrtl.convention} {} // PRESERVE_ALL: @ScalarizedModule1(in %port_0: !firrtl.uint<8>, in %port_1: !firrtl.uint<8>) // PRESERVE_VEC: @ScalarizedModule1(in %port_0: !firrtl.uint<8>, in %port_1: !firrtl.uint<8>) // PRESERVE_1D_VEC: @ScalarizedModule1(in %port_0: !firrtl.uint<8>, in %port_1: !firrtl.uint<8>) // PRESERVE_NONE: @ScalarizedModule1(in %port_0: !firrtl.uint<8>, in %port_1: !firrtl.uint<8>) firrtl.module @ScalarizedModule1(in %port: !firrtl.vector, 2>) - attributes {convention = #firrtl} {} + attributes {convention = #firrtl.convention} {} // 2D Vector Ports @@ -35,14 +35,14 @@ firrtl.circuit "TopLevel" { // PRESERVE_1D_VEC: @InternalModule2(in %port_0: !firrtl.vector, 2>, in %port_1: !firrtl.vector, 2>) // PRESERVE_NONE: @InternalModule2(in %port_0_0: !firrtl.uint<8>, in %port_0_1: !firrtl.uint<8>, in %port_1_0: !firrtl.uint<8>, in %port_1_1: !firrtl.uint<8>) firrtl.module @InternalModule2(in %port: !firrtl.vector, 2>, 2>) - attributes {convention = #firrtl} {} + attributes {convention = #firrtl.convention} {} // PRESERVE_ALL: ScalarizedModule2(in %port_0_0: !firrtl.uint<8>, in %port_0_1: !firrtl.uint<8>, in %port_1_0: !firrtl.uint<8>, in %port_1_1: !firrtl.uint<8>) // PRESERVE_VEC: ScalarizedModule2(in %port_0_0: !firrtl.uint<8>, in %port_0_1: !firrtl.uint<8>, in %port_1_0: !firrtl.uint<8>, in %port_1_1: !firrtl.uint<8>) // PRESERVE_1D_VEC: ScalarizedModule2(in %port_0_0: !firrtl.uint<8>, in %port_0_1: !firrtl.uint<8>, in %port_1_0: !firrtl.uint<8>, in %port_1_1: !firrtl.uint<8>) // PRESERVE_NONE: ScalarizedModule2(in %port_0_0: !firrtl.uint<8>, in %port_0_1: !firrtl.uint<8>, in %port_1_0: !firrtl.uint<8>, in %port_1_1: !firrtl.uint<8>) firrtl.module @ScalarizedModule2(in %port: !firrtl.vector, 2>, 2>) - attributes {convention = #firrtl} {} + attributes {convention = #firrtl.convention} {} // Bundle Ports @@ -51,12 +51,12 @@ firrtl.circuit "TopLevel" { // PRESERVE_1D_VEC: @InternalModule3(in %port_field: !firrtl.uint<1>) // PRESERVE_NONE: @InternalModule3(in %port_field: !firrtl.uint<1>) firrtl.module @InternalModule3(in %port: !firrtl.bundle>) - attributes {convention = #firrtl} {} + attributes {convention = #firrtl.convention} {} // PRESERVE_ALL: @ScalarizedModule3(in %port_field: !firrtl.uint<1>) // PRESERVE_VEC: @ScalarizedModule3(in %port_field: !firrtl.uint<1>) // PRESERVE_1D_VEC: @ScalarizedModule3(in %port_field: !firrtl.uint<1>) // PRESERVE_NONE: @ScalarizedModule3(in %port_field: !firrtl.uint<1>) firrtl.module @ScalarizedModule3(in %port: !firrtl.bundle>) - attributes {convention = #firrtl} {} + attributes {convention = #firrtl.convention} {} } diff --git a/test/Dialect/FIRRTL/lower-types-issue-5592.mlir b/test/Dialect/FIRRTL/lower-types-issue-5592.mlir index 6e5d8e6ed08d..9b9b2ac02c40 100644 --- a/test/Dialect/FIRRTL/lower-types-issue-5592.mlir +++ b/test/Dialect/FIRRTL/lower-types-issue-5592.mlir @@ -4,7 +4,7 @@ // https://github.com/llvm/circt/issues/5592 firrtl.circuit "Issue5592" { - firrtl.module @Issue5592(in %clock: !firrtl.clock, in %rAddr: !firrtl.uint<4>, in %rEn: !firrtl.uint<1>, out %rData: !firrtl.vector, 4>, in %wMask: !firrtl.vector, 4>, in %wData: !firrtl.vector, 4>) attributes {convention = #firrtl} { + firrtl.module @Issue5592(in %clock: !firrtl.clock, in %rAddr: !firrtl.uint<4>, in %rEn: !firrtl.uint<1>, out %rData: !firrtl.vector, 4>, in %wMask: !firrtl.vector, 4>, in %wData: !firrtl.vector, 4>) attributes {convention = #firrtl.convention} { // expected-error @below {{has a symbol, but no symbols may exist on aggregates passed through LowerTypes}} %memory_r, %memory_w = firrtl.mem sym @X interesting_name Undefined {depth = 16 : i64, name = "memory", portNames = ["r", "w"], readLatency = 1 : i32, writeLatency = 1 : i32} : !firrtl.bundle, en: uint<1>, clk: clock, data flip: vector, 4>>, !firrtl.bundle, en: uint<1>, clk: clock, data: vector, 4>, mask: vector, 4>> } diff --git a/test/Dialect/FIRRTL/lower-types-remat.mlir b/test/Dialect/FIRRTL/lower-types-remat.mlir index 010d9b8a2a52..1497b9d132e5 100644 --- a/test/Dialect/FIRRTL/lower-types-remat.mlir +++ b/test/Dialect/FIRRTL/lower-types-remat.mlir @@ -34,7 +34,7 @@ firrtl.circuit "Bar" { // ALL-NEXT: vectorcreate // ALL-NEXT: bundlecreate // ALL-NEXT: mux - firrtl.module @Bar(in %a1: !firrtl.bundle, 2>, b: uint<2>>, in %a2: !firrtl.bundle, 2>, b: uint<2>>, in %cond: !firrtl.uint<1>, out %b: !firrtl.bundle, 2>, b: uint<2>>) attributes {convention = #firrtl} { + firrtl.module @Bar(in %a1: !firrtl.bundle, 2>, b: uint<2>>, in %a2: !firrtl.bundle, 2>, b: uint<2>>, in %cond: !firrtl.uint<1>, out %b: !firrtl.bundle, 2>, b: uint<2>>) attributes {convention = #firrtl.convention} { %0 = firrtl.mux(%cond, %a1, %a2) : (!firrtl.uint<1>, !firrtl.bundle, 2>, b: uint<2>>, !firrtl.bundle, 2>, b: uint<2>>) -> !firrtl.bundle, 2>, b: uint<2>> firrtl.matchingconnect %b, %0 : !firrtl.bundle, 2>, b: uint<2>> } diff --git a/test/Dialect/FIRRTL/lower-types.mlir b/test/Dialect/FIRRTL/lower-types.mlir index 344aca12175a..ead58fca1564 100644 --- a/test/Dialect/FIRRTL/lower-types.mlir +++ b/test/Dialect/FIRRTL/lower-types.mlir @@ -1404,3 +1404,42 @@ firrtl.circuit "UnrealizedConversion" { firrtl.matchingconnect %w, %b : !firrtl.bundle, tag: uint<1>> } } + +firrtl.circuit "Conventions1" { + // COMMON-LABEL: @Conventions1 + // AGGREGATE-SAME: %input_0 + // AGGREGATE-NEXT: firrtl.reg + // AGGREGATE-SAME: !firrtl.vector, 1> + firrtl.module public @Conventions1(in %input: !firrtl.vector, 1>, in %clk: !firrtl.clock, out %port: !firrtl.vector, 1>) attributes {convention = #firrtl.convention}{ + %r = firrtl.reg interesting_name %clk : !firrtl.clock, !firrtl.vector, 1> + firrtl.matchingconnect %r, %input : !firrtl.vector, 1> + firrtl.matchingconnect %port, %r : !firrtl.vector, 1> + } + // COMMON-LABEL: @Conventions2 + // AGGREGATE-SAME: %input_0: !firrtl.uint<8> + // AGGREGATE-NEXT: firrtl.reg + // AGGREGATE-SAME: !firrtl.uint<8> + firrtl.module private @Conventions2(in %input: !firrtl.vector, 1>, in %clk: !firrtl.clock, out %port: !firrtl.vector, 1>) attributes {convention = #firrtl.convention}{ + %r = firrtl.reg interesting_name %clk : !firrtl.clock, !firrtl.vector, 1> + firrtl.matchingconnect %r, %input : !firrtl.vector, 1> + firrtl.matchingconnect %port, %r : !firrtl.vector, 1> + } + // COMMON-LABEL: @Conventions3 + // AGGREGATE-SAME: %input: !firrtl.vector, 1> + // AGGREGATE-NEXT: firrtl.reg + // AGGREGATE-SAME: !firrtl.vector, 1> + firrtl.module private @Conventions3(in %input: !firrtl.vector, 1>, in %clk: !firrtl.clock, out %port: !firrtl.vector, 1>) attributes {convention = #firrtl.convention}{ + %r = firrtl.reg interesting_name %clk : !firrtl.clock, !firrtl.vector, 1> + firrtl.matchingconnect %r, %input : !firrtl.vector, 1> + firrtl.matchingconnect %port, %r : !firrtl.vector, 1> + } + // COMMON-LABEL: @Conventions4 + // AGGREGATE-SAME: %input: !firrtl.vector, 1> + // AGGREGATE-NEXT: firrtl.reg + // AGGREGATE-SAME: !firrtl.uint<8> + firrtl.module private @Conventions4(in %input: !firrtl.vector, 1>, in %clk: !firrtl.clock, out %port: !firrtl.vector, 1>) attributes {convention = #firrtl.convention}{ + %r = firrtl.reg interesting_name %clk : !firrtl.clock, !firrtl.vector, 1> + firrtl.matchingconnect %r, %input : !firrtl.vector, 1> + firrtl.matchingconnect %port, %r : !firrtl.vector, 1> + } +} diff --git a/test/Dialect/FIRRTL/lowerXMR.mlir b/test/Dialect/FIRRTL/lowerXMR.mlir index caebcd789d17..d97bdc96e4be 100644 --- a/test/Dialect/FIRRTL/lowerXMR.mlir +++ b/test/Dialect/FIRRTL/lowerXMR.mlir @@ -528,7 +528,7 @@ firrtl.circuit "InternalPaths" { firrtl.extmodule private @RefExtMore(in in: !firrtl.uint<1>, out r: !firrtl.probe>, out data: !firrtl.uint<3>, - out r2: !firrtl.probe>, 3>>) attributes {convention = #firrtl, internalPaths = [#firrtl.internalpath, #firrtl.internalpath<"path.to.internal.signal">, #firrtl.internalpath, #firrtl.internalpath<"in">]} + out r2: !firrtl.probe>, 3>>) attributes {convention = #firrtl.convention, internalPaths = [#firrtl.internalpath, #firrtl.internalpath<"path.to.internal.signal">, #firrtl.internalpath, #firrtl.internalpath<"in">]} // CHECK: hw.hierpath private @xmrPath [@InternalPaths::@[[EXT_SYM:.+]]] // CHECK: module public @InternalPaths( firrtl.module public @InternalPaths(in %in: !firrtl.uint<1>) { @@ -559,7 +559,7 @@ firrtl.circuit "RefABI" { firrtl.extmodule private @RefExtMore(in in: !firrtl.uint<1>, out r: !firrtl.probe>, out data: !firrtl.uint<3>, - out r2: !firrtl.probe>, 3>>) attributes {convention = #firrtl} + out r2: !firrtl.probe>, 3>>) attributes {convention = #firrtl.convention} // CHECK: hw.hierpath private @xmrPath [@RefABI::@[[XMR_SYM:.+]]] // CHECK: module public @RefABI( firrtl.module public @RefABI(in %in: !firrtl.uint<1>) { @@ -749,7 +749,7 @@ firrtl.circuit "RefSubOutputPort" { firrtl.module @RefSubOutputPort(out %outRWBundleProbe: !firrtl.rwprobe, 2>>>, out %outVec: !firrtl.rwprobe, 2>>, out %outElem: !firrtl.rwprobe>, - out %outElemDirect: !firrtl.rwprobe>) attributes {convention = #firrtl} { + out %outElemDirect: !firrtl.rwprobe>) attributes {convention = #firrtl.convention} { %0 = firrtl.ref.sub %outVec[1] : !firrtl.rwprobe, 2>> %1 = firrtl.ref.sub %outRWBundleProbe[0] : !firrtl.rwprobe, 2>>> %2 = firrtl.ref.sub %1[1] : !firrtl.rwprobe, 2>> diff --git a/test/Dialect/FIRRTL/probes-to-signals-errors.mlir b/test/Dialect/FIRRTL/probes-to-signals-errors.mlir index 74aa41b45a01..3f28e4ef7b46 100644 --- a/test/Dialect/FIRRTL/probes-to-signals-errors.mlir +++ b/test/Dialect/FIRRTL/probes-to-signals-errors.mlir @@ -14,7 +14,7 @@ firrtl.circuit "InternalPath" { // Detect and diagnose, and in practice use ExpandWhens first to ensure success. firrtl.circuit "RefProducer" { // expected-note @below {{destination here}} - firrtl.module @RefProducer(in %a: !firrtl.uint<4>, in %en: !firrtl.uint<1>, in %clk: !firrtl.clock, out %thereg: !firrtl.probe) attributes {convention = #firrtl} { + firrtl.module @RefProducer(in %a: !firrtl.uint<4>, in %en: !firrtl.uint<1>, in %clk: !firrtl.clock, out %thereg: !firrtl.probe) attributes {convention = #firrtl.convention} { firrtl.when %en : !firrtl.uint<1> { %myreg = firrtl.reg interesting_name %clk : !firrtl.clock, !firrtl.uint firrtl.connect %myreg, %a : !firrtl.uint, !firrtl.uint<4> diff --git a/test/circt-reduce/name-sanitizer.mlir b/test/circt-reduce/name-sanitizer.mlir index 7245de8caf4d..e65249ea8150 100644 --- a/test/circt-reduce/name-sanitizer.mlir +++ b/test/circt-reduce/name-sanitizer.mlir @@ -43,7 +43,7 @@ firrtl.circuit "A" { out %out: !firrtl.uint<1>, out %aProbe: !firrtl.probe>, out %bProbe: !firrtl.rwprobe> - ) attributes {convention = #firrtl} { + ) attributes {convention = #firrtl.convention} { // CHECK-NEXT: %wire = firrtl.wire // CHECK-NEXT: firrtl.wire {name = "wire"} %foo = firrtl.wire : !firrtl.uint<1> diff --git a/test/firtool/convention.fir b/test/firtool/convention.fir index 10151b68a129..1e26e84be526 100644 --- a/test/firtool/convention.fir +++ b/test/firtool/convention.fir @@ -13,38 +13,38 @@ FIRRTL version 4.0.0 circuit Top : - ; SCALARIZE_FFF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TFF: attributes {convention = #firrtl} - ; SCALARIZE_FTF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TTF: attributes {convention = #firrtl} - ; SCALARIZE_FFT-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TFT: attributes {convention = #firrtl} - ; SCALARIZE_FTT-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TTT: attributes {convention = #firrtl} + ; SCALARIZE_FFF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TFF: attributes {convention = #firrtl.convention} + ; SCALARIZE_FTF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TTF: attributes {convention = #firrtl.convention} + ; SCALARIZE_FFT-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TFT: attributes {convention = #firrtl.convention} + ; SCALARIZE_FTT-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TTT: attributes {convention = #firrtl.convention} public module Top : output port: UInt<8>[2] connect port[0], UInt<8>(0) connect port[1], UInt<8>(0) - ; SCALARIZE_FFF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TFF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_FTF: attributes {convention = #firrtl} - ; SCALARIZE_TTF: attributes {convention = #firrtl} - ; SCALARIZE_FFT-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TFT-NOT: attributes {convention = #firrtl} - ; SCALARIZE_FTT: attributes {convention = #firrtl} - ; SCALARIZE_TTT: attributes {convention = #firrtl} + ; SCALARIZE_FFF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TFF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_FTF: attributes {convention = #firrtl.convention} + ; SCALARIZE_TTF: attributes {convention = #firrtl.convention} + ; SCALARIZE_FFT-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TFT-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_FTT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TTT: attributes {convention = #firrtl.convention} extmodule External : output port: UInt<8>[2] - ; SCALARIZE_FFF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TFF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_FTF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_TTF-NOT: attributes {convention = #firrtl} - ; SCALARIZE_FFT: attributes {convention = #firrtl} - ; SCALARIZE_TFT: attributes {convention = #firrtl} - ; SCALARIZE_FTT: attributes {convention = #firrtl} - ; SCALARIZE_TTT: attributes {convention = #firrtl} + ; SCALARIZE_FFF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TFF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_FTF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TTF-NOT: attributes {convention = #firrtl.convention} + ; SCALARIZE_FFT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TFT: attributes {convention = #firrtl.convention} + ; SCALARIZE_FTT: attributes {convention = #firrtl.convention} + ; SCALARIZE_TTT: attributes {convention = #firrtl.convention} module Internal : output port: UInt<8>[2] connect port[0], UInt<8>(0)