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LNL: Release v1.11 event files
This commit releases LNL v1.11 events and updates mapfile.csv accordingly.
1 parent de5502e commit af32903

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5 files changed

+164
-41
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5 files changed

+164
-41
lines changed

‎LNL/events/lunarlake_lioncove_core.json

Lines changed: 93 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.10",
5-
"DatePublished": "11/19/2024",
6-
"Version": "1.10",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.11",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.11",
77
"Legend": ""
88
},
99
"Events": [
@@ -1411,6 +1411,60 @@
14111411
"PDISTCounter": "NA",
14121412
"Speculative": "1"
14131413
},
1414+
{
1415+
"EventCode": "0x24",
1416+
"UMask": "0x42",
1417+
"UMaskExt": "0x00",
1418+
"EventName": "L2_RQSTS.RFO_HIT",
1419+
"BriefDescription": "RFO requests that hit L2 cache",
1420+
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
1421+
"Counter": "0,1,2,3,4,5,6,7,8,9",
1422+
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
1423+
"SampleAfterValue": "200003",
1424+
"MSRIndex": "0x00",
1425+
"MSRValue": "0x00",
1426+
"Precise": "0",
1427+
"CollectPEBSRecord": "2",
1428+
"TakenAlone": "0",
1429+
"CounterMask": "0",
1430+
"Invert": "0",
1431+
"EdgeDetect": "0",
1432+
"Data_LA": "0",
1433+
"L1_Hit_Indication": "0",
1434+
"Errata": "null",
1435+
"Offcore": "0",
1436+
"Deprecated": "0",
1437+
"Equal": "0",
1438+
"PDISTCounter": "NA",
1439+
"Speculative": "1"
1440+
},
1441+
{
1442+
"EventCode": "0x24",
1443+
"UMask": "0x44",
1444+
"UMaskExt": "0x00",
1445+
"EventName": "L2_RQSTS.CODE_RD_HIT",
1446+
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
1447+
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
1448+
"Counter": "0,1,2,3,4,5,6,7,8,9",
1449+
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
1450+
"SampleAfterValue": "200003",
1451+
"MSRIndex": "0x00",
1452+
"MSRValue": "0x00",
1453+
"Precise": "0",
1454+
"CollectPEBSRecord": "2",
1455+
"TakenAlone": "0",
1456+
"CounterMask": "0",
1457+
"Invert": "0",
1458+
"EdgeDetect": "0",
1459+
"Data_LA": "0",
1460+
"L1_Hit_Indication": "0",
1461+
"Errata": "null",
1462+
"Offcore": "0",
1463+
"Deprecated": "0",
1464+
"Equal": "0",
1465+
"PDISTCounter": "NA",
1466+
"Speculative": "1"
1467+
},
14141468
{
14151469
"EventCode": "0x24",
14161470
"UMask": "0xe1",
@@ -1438,6 +1492,33 @@
14381492
"PDISTCounter": "NA",
14391493
"Speculative": "1"
14401494
},
1495+
{
1496+
"EventCode": "0x24",
1497+
"UMask": "0xe4",
1498+
"UMaskExt": "0x00",
1499+
"EventName": "L2_RQSTS.ALL_CODE_RD",
1500+
"BriefDescription": "L2 code requests",
1501+
"PublicDescription": "Counts the total number of L2 code requests.",
1502+
"Counter": "0,1,2,3,4,5,6,7,8,9",
1503+
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
1504+
"SampleAfterValue": "200003",
1505+
"MSRIndex": "0x00",
1506+
"MSRValue": "0x00",
1507+
"Precise": "0",
1508+
"CollectPEBSRecord": "2",
1509+
"TakenAlone": "0",
1510+
"CounterMask": "0",
1511+
"Invert": "0",
1512+
"EdgeDetect": "0",
1513+
"Data_LA": "0",
1514+
"L1_Hit_Indication": "0",
1515+
"Errata": "null",
1516+
"Offcore": "0",
1517+
"Deprecated": "0",
1518+
"Equal": "0",
1519+
"PDISTCounter": "NA",
1520+
"Speculative": "1"
1521+
},
14411522
{
14421523
"EventCode": "0x24",
14431524
"UMask": "0xff",
@@ -1648,7 +1729,7 @@
16481729
"Data_LA": "0",
16491730
"L1_Hit_Indication": "0",
16501731
"Errata": "null",
1651-
"Offcore": "0",
1732+
"Offcore": "1",
16521733
"Deprecated": "0",
16531734
"Equal": "0",
16541735
"PDISTCounter": "0",
@@ -1675,7 +1756,7 @@
16751756
"Data_LA": "0",
16761757
"L1_Hit_Indication": "0",
16771758
"Errata": "null",
1678-
"Offcore": "0",
1759+
"Offcore": "1",
16791760
"Deprecated": "0",
16801761
"Equal": "0",
16811762
"PDISTCounter": "0",
@@ -1702,7 +1783,7 @@
17021783
"Data_LA": "0",
17031784
"L1_Hit_Indication": "0",
17041785
"Errata": "null",
1705-
"Offcore": "0",
1786+
"Offcore": "1",
17061787
"Deprecated": "0",
17071788
"Equal": "0",
17081789
"PDISTCounter": "0",
@@ -1729,7 +1810,7 @@
17291810
"Data_LA": "0",
17301811
"L1_Hit_Indication": "0",
17311812
"Errata": "null",
1732-
"Offcore": "0",
1813+
"Offcore": "1",
17331814
"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -1756,7 +1837,7 @@
17561837
"Data_LA": "0",
17571838
"L1_Hit_Indication": "0",
17581839
"Errata": "null",
1759-
"Offcore": "0",
1840+
"Offcore": "1",
17601841
"Deprecated": "0",
17611842
"Equal": "0",
17621843
"PDISTCounter": "0",
@@ -1783,7 +1864,7 @@
17831864
"Data_LA": "0",
17841865
"L1_Hit_Indication": "0",
17851866
"Errata": "null",
1786-
"Offcore": "0",
1867+
"Offcore": "1",
17871868
"Deprecated": "0",
17881869
"Equal": "0",
17891870
"PDISTCounter": "0",
@@ -1810,7 +1891,7 @@
18101891
"Data_LA": "0",
18111892
"L1_Hit_Indication": "0",
18121893
"Errata": "null",
1813-
"Offcore": "0",
1894+
"Offcore": "1",
18141895
"Deprecated": "0",
18151896
"Equal": "0",
18161897
"PDISTCounter": "0",
@@ -1837,7 +1918,7 @@
18371918
"Data_LA": "0",
18381919
"L1_Hit_Indication": "0",
18391920
"Errata": "null",
1840-
"Offcore": "0",
1921+
"Offcore": "1",
18411922
"Deprecated": "0",
18421923
"Equal": "0",
18431924
"PDISTCounter": "0",
@@ -1864,7 +1945,7 @@
18641945
"Data_LA": "0",
18651946
"L1_Hit_Indication": "0",
18661947
"Errata": "null",
1867-
"Offcore": "0",
1948+
"Offcore": "1",
18681949
"Deprecated": "0",
18691950
"Equal": "0",
18701951
"PDISTCounter": "0",

‎LNL/events/lunarlake_skymont_core.json

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.10",
5-
"DatePublished": "11/19/2024",
6-
"Version": "1.10",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.11",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.11",
77
"Legend": ""
88
},
99
"Events": [
@@ -4213,7 +4213,7 @@
42134213
"Data_LA": "0",
42144214
"L1_Hit_Indication": "0",
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"Errata": "null",
4216-
"Offcore": "0",
4216+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
42194219
"PDISTCounter": "0",
@@ -4240,7 +4240,7 @@
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"Data_LA": "0",
42414241
"L1_Hit_Indication": "0",
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"Errata": "null",
4243-
"Offcore": "0",
4243+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -4267,7 +4267,7 @@
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
4270-
"Offcore": "0",
4270+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
42734273
"PDISTCounter": "0",
@@ -4294,7 +4294,7 @@
42944294
"Data_LA": "0",
42954295
"L1_Hit_Indication": "0",
42964296
"Errata": "null",
4297-
"Offcore": "0",
4297+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -4321,7 +4321,7 @@
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
4324-
"Offcore": "0",
4324+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -4348,7 +4348,7 @@
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
4351+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -4375,7 +4375,7 @@
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
4378-
"Offcore": "0",
4378+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -4402,7 +4402,7 @@
44024402
"Data_LA": "0",
44034403
"L1_Hit_Indication": "0",
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"Errata": "null",
4405-
"Offcore": "0",
4405+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
@@ -4429,7 +4429,7 @@
44294429
"Data_LA": "0",
44304430
"L1_Hit_Indication": "0",
44314431
"Errata": "null",
4432-
"Offcore": "0",
4432+
"Offcore": "1",
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"Deprecated": "0",
44344434
"Equal": "0",
44354435
"PDISTCounter": "0",
@@ -4456,7 +4456,7 @@
44564456
"Data_LA": "0",
44574457
"L1_Hit_Indication": "0",
44584458
"Errata": "null",
4459-
"Offcore": "0",
4459+
"Offcore": "1",
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"Deprecated": "0",
44614461
"Equal": "0",
44624462
"PDISTCounter": "0",
@@ -4483,7 +4483,7 @@
44834483
"Data_LA": "0",
44844484
"L1_Hit_Indication": "0",
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"Errata": "null",
4486-
"Offcore": "0",
4486+
"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
44894489
"PDISTCounter": "0",
@@ -4510,7 +4510,7 @@
45104510
"Data_LA": "0",
45114511
"L1_Hit_Indication": "0",
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"Errata": "null",
4513-
"Offcore": "0",
4513+
"Offcore": "1",
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"Deprecated": "0",
45154515
"Equal": "0",
45164516
"PDISTCounter": "0",
@@ -4537,7 +4537,7 @@
45374537
"Data_LA": "0",
45384538
"L1_Hit_Indication": "0",
45394539
"Errata": "null",
4540-
"Offcore": "0",
4540+
"Offcore": "1",
45414541
"Deprecated": "0",
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"Equal": "0",
45434543
"PDISTCounter": "0",
@@ -4564,7 +4564,7 @@
45644564
"Data_LA": "0",
45654565
"L1_Hit_Indication": "0",
45664566
"Errata": "null",
4567-
"Offcore": "0",
4567+
"Offcore": "1",
45684568
"Deprecated": "0",
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"Equal": "0",
45704570
"PDISTCounter": "0",
@@ -4591,7 +4591,7 @@
45914591
"Data_LA": "0",
45924592
"L1_Hit_Indication": "0",
45934593
"Errata": "null",
4594-
"Offcore": "0",
4594+
"Offcore": "1",
45954595
"Deprecated": "0",
45964596
"Equal": "0",
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"PDISTCounter": "0",
@@ -4618,7 +4618,7 @@
46184618
"Data_LA": "0",
46194619
"L1_Hit_Indication": "0",
46204620
"Errata": "null",
4621-
"Offcore": "0",
4621+
"Offcore": "1",
46224622
"Deprecated": "0",
46234623
"Equal": "0",
46244624
"PDISTCounter": "0",
@@ -4645,7 +4645,7 @@
46454645
"Data_LA": "0",
46464646
"L1_Hit_Indication": "0",
46474647
"Errata": "null",
4648-
"Offcore": "0",
4648+
"Offcore": "1",
46494649
"Deprecated": "0",
46504650
"Equal": "0",
46514651
"PDISTCounter": "0",
@@ -5115,8 +5115,8 @@
51155115
"UMask": "0x6e",
51165116
"UMaskExt": "0x00",
51175117
"EventName": "MACHINE_CLEARS.SLOW",
5118-
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
5119-
"PublicDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
5118+
"BriefDescription": "This event is deprecated.",
5119+
"PublicDescription": "This event is deprecated.",
51205120
"Counter": "0,1,2,3,4,5,6,7",
51215121
"PEBScounters": "0,1,2,3,4,5,6,7",
51225122
"SampleAfterValue": "20003",
@@ -5132,7 +5132,7 @@
51325132
"L1_Hit_Indication": "0",
51335133
"Errata": "null",
51345134
"Offcore": "0",
5135-
"Deprecated": "0",
5135+
"Deprecated": "1",
51365136
"Equal": "0",
51375137
"PDISTCounter": "NA",
51385138
"Speculative": "1"

‎LNL/events/lunarlake_uncore.json

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.10",
5-
"DatePublished": "11/19/2024",
6-
"Version": "1.10",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.11",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.11",
77
"Legend": ""
88
},
99
"Events": [

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