From cdce3c8f67d6ab396aa0f99635e85b09ce259ab1 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Wed, 29 May 2024 18:41:18 +0300
Subject: [PATCH] ecp5: add buffers.

---
 src/main/scala/ee/hrzn/chryse/ChryseApp.scala |  2 +-
 .../hrzn/chryse/platform/ecp5/ECP5Top.scala   | 45 ++++++++++++++++---
 .../ee/hrzn/chryse/platform/ecp5/IB.scala     |  9 ++++
 .../ee/hrzn/chryse/platform/ecp5/OBZ.scala    | 10 +++++
 .../chryse/platform/ecp5/ULX3SPlatform.scala  |  1 +
 .../ee/hrzn/chryse/platform/ice40/SB_IO.scala |  1 -
 6 files changed, 60 insertions(+), 8 deletions(-)
 create mode 100644 src/main/scala/ee/hrzn/chryse/platform/ecp5/IB.scala
 create mode 100644 src/main/scala/ee/hrzn/chryse/platform/ecp5/OBZ.scala

diff --git a/src/main/scala/ee/hrzn/chryse/ChryseApp.scala b/src/main/scala/ee/hrzn/chryse/ChryseApp.scala
index 3014e79..b75cd26 100644
--- a/src/main/scala/ee/hrzn/chryse/ChryseApp.scala
+++ b/src/main/scala/ee/hrzn/chryse/ChryseApp.scala
@@ -11,7 +11,7 @@ import org.rogach.scallop._
 
 import scala.collection.mutable
 
-// TODO: Restore sbt plugin to attach rm of buildDir to clean.
+// TODO: some platform may program in different ways (ULX3S: flash or SRAM).
 
 abstract class ChryseApp {
   val name: String
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
index dba236d..a853b80 100644
--- a/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
@@ -1,6 +1,8 @@
 package ee.hrzn.chryse.platform.ecp5
 
 import chisel3._
+import chisel3.util.unsignedBitLength
+import ee.hrzn.chryse.chisel.directionOf
 import ee.hrzn.chryse.platform.ChryseTop
 import ee.hrzn.chryse.platform.Platform
 import ee.hrzn.chryse.platform.PlatformBoard
@@ -28,30 +30,61 @@ class ECP5Top[Top <: Module](
     PlatformConnectResultFallthrough
   }
 
-  private val clki = Wire(Clock())
+  override protected def platformPort[HW <: Data](
+      res: ResourceData[HW],
+      topIo: Data,
+      portIo: Data,
+  ) = {
+    directionOf(portIo) match {
+      case directionOf.Input =>
+        val ib = Module(new IB).suggestName(s"${res.name.get}_IB")
+        ib.I  := portIo
+        topIo := ib.O
+      case directionOf.Output =>
+        val obz = Module(new OBZ).suggestName(s"${res.name.get}_OBZ")
+        obz.T  := false.B // OE=1
+        obz.I  := topIo
+        portIo := obz.O
+    }
+  }
+
+  private val clk = Wire(Clock())
 
   private val gsr0 = Wire(Bool())
   private val i0   = Module(new FD1S3AX)
-  i0.CK := clki
+  i0.CK := clk
   i0.D  := true.B
   gsr0  := i0.Q
 
   private val gsr1 = Wire(Bool())
   private val i1   = Module(new FD1S3AX)
-  i1.CK := clki
+  i1.CK := clk
   i1.D  := gsr0
   gsr1  := i1.Q
 
   private val sgsr = Module(new SGSR)
-  sgsr.CLK := clki
+  sgsr.CLK := clk
   sgsr.GSR := gsr1
 
+  // Provide a POR so RegNexts get their value.
+  private val timerLimit = 2
+  private val resetTimerReg =
+    withClock(clk)(Reg(UInt(unsignedBitLength(timerLimit).W)))
+  private val reset = Wire(Bool())
+
+  when(resetTimerReg === timerLimit.U) {
+    reset := false.B
+  }.otherwise {
+    reset         := true.B
+    resetTimerReg := resetTimerReg + 1.U
+  }
+
   private val top =
-    withClockAndReset(clki, false.B)(Module(genTop))
+    withClockAndReset(clk, reset)(Module(genTop))
 
   // TODO (ECP5): allow clock source override.
 
-  val connectedResources = connectResources(platform, Some(clki))
+  val connectedResources = connectResources(platform, Some(clk))
 
   val lpf = LPF(
     connectedResources
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/IB.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/IB.scala
new file mode 100644
index 0000000..4ecca8e
--- /dev/null
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/IB.scala
@@ -0,0 +1,9 @@
+package ee.hrzn.chryse.platform.ecp5
+
+import chisel3._
+import chisel3.experimental.ExtModule
+
+class IB extends ExtModule {
+  val I = IO(Input(Bool()))
+  val O = IO(Output(Bool()))
+}
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/OBZ.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/OBZ.scala
new file mode 100644
index 0000000..0761f31
--- /dev/null
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/OBZ.scala
@@ -0,0 +1,10 @@
+package ee.hrzn.chryse.platform.ecp5
+
+import chisel3._
+import chisel3.experimental.ExtModule
+
+class OBZ extends ExtModule {
+  val T = IO(Input(Bool())) // inverted OE
+  val I = IO(Input(Bool()))
+  val O = IO(Output(Bool()))
+}
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/ULX3SPlatform.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/ULX3SPlatform.scala
index 2712d82..47619d0 100644
--- a/src/main/scala/ee/hrzn/chryse/platform/ecp5/ULX3SPlatform.scala
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/ULX3SPlatform.scala
@@ -72,6 +72,7 @@ class ULX3SPlatformResources extends PlatformBoardResources {
     )
     .withAttributes("PULLMODE" -> "NONE", "DRIVE" -> "4")
 
+  val butt0 = Button().inverted.onPin("D6").withAttributes("PULLMODE" -> "UP")
 // val buttons =
   // DIP switches
   // UART
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ice40/SB_IO.scala b/src/main/scala/ee/hrzn/chryse/platform/ice40/SB_IO.scala
index 7fd2429..9d56386 100644
--- a/src/main/scala/ee/hrzn/chryse/platform/ice40/SB_IO.scala
+++ b/src/main/scala/ee/hrzn/chryse/platform/ice40/SB_IO.scala
@@ -1,7 +1,6 @@
 package ee.hrzn.chryse.platform.ice40
 
 import chisel3._
-import chisel3.experimental.Analog
 import chisel3.experimental.ExtModule
 
 class SB_IO(