diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
index b1ba9bd..e8336d8 100644
--- a/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
@@ -6,25 +6,31 @@ import ee.hrzn.chryse.platform.Platform
 import ee.hrzn.chryse.platform.PlatformBoard
 import ee.hrzn.chryse.platform.PlatformBoardResources
 
-class ECP5Top[Top <: Module](platform: Platform, genTop: => Top)
-    extends RawModule
+class ECP5Top[Top <: Module](
+    platform: PlatformBoard[_ <: PlatformBoardResources],
+    genTop: => Top,
+) extends RawModule
     with ChryseTop {
-  override def desiredName = "ecp5top"
+  private val clki = Wire(Clock())
 
-  private val clki = IO(Input(Clock()))
+  private val gsr0 = Wire(Bool())
+  private val i0   = Module(new FD1S3AX)
+  i0.CK := clki
+  i0.D  := true.B
+  gsr0  := i0.Q
 
-  // TODO (ECP5): GSR stuff. (details follow.)
-  // FD1S3AX D=1    Q=gsr0
-  // FD1S3AX D=gsr0 Q=gsr1
-  // SGSR    GSR=gsr1
-  //
-  // FD1S3AX: posedge-triggered DFF, GSR used for clear.
-  //   Q=Mux(GSR, D, 0).
-  // SGSR:    synchronous-release global set/reset interface.
-  //   Active LOW; when pulsed will (re)set all FFs, latches, registers etc.
-  //   Signals are not connected to SGSR explicitly -- implicitly connected
-  //   globally.
+  private val gsr1 = Wire(Bool())
+  private val i1   = Module(new FD1S3AX)
+  i1.CK := clki
+  i1.D  := gsr0
+  gsr1  := i1.Q
+
+  private val sgsr = Module(new SGSR)
+  sgsr.CLK := clki
+  sgsr.GSR := gsr1
 
   private val top =
     withClockAndReset(clki, false.B)(Module(genTop))
+
+  val connectedResources = connectResources(platform, Some(clki))
 }
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/FD1S3AX.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/FD1S3AX.scala
new file mode 100644
index 0000000..4621884
--- /dev/null
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/FD1S3AX.scala
@@ -0,0 +1,12 @@
+package ee.hrzn.chryse.platform.ecp5
+
+import chisel3._
+import chisel3.experimental.ExtModule
+
+// FD1S3AX: posedge-triggered DFF, GSR used for clear.
+//   Q=Mux(GSR, D, 0).
+class FD1S3AX extends ExtModule(Map("GSR" -> "DISABLED")) {
+  val CK = IO(Input(Clock()))
+  val D  = IO(Input(Bool()))
+  val Q  = IO(Output(Bool()))
+}
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/SGSR.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/SGSR.scala
new file mode 100644
index 0000000..57d5058
--- /dev/null
+++ b/src/main/scala/ee/hrzn/chryse/platform/ecp5/SGSR.scala
@@ -0,0 +1,13 @@
+package ee.hrzn.chryse.platform.ecp5
+
+import chisel3._
+import chisel3.experimental.ExtModule
+
+// SGSR:    synchronous-release global set/reset interface.
+//   Active LOW; when pulsed will (re)set all FFs, latches, registers etc.
+//   Signals are not connected to SGSR explicitly -- implicitly connected
+//   globally.
+class SGSR extends ExtModule {
+  val CLK = IO(Input(Clock()))
+  val GSR = IO(Input(Bool()))
+}