added internal termination instruction and added ci/cd tests for llarm-emu

kernelwernel · kernelwernel · commit efe9da9761f4 · 2026-05-10T04:56:54.000+01:00
diff --git a/.github/workflows/llarm-emu.yml b/.github/workflows/llarm-emu.yml
@@ -10,6 +10,7 @@ on:
       - 'llarm-emu/**/CMakeLists.txt'
       - 'llarm-emu/**/*.cmake'
       - 'llarm-emu/**/*.cmake.in'
+      - 'llarm-emu/tests/**'
       - 'llarm-asm/**/*.cpp'
       - 'llarm-asm/**/*.hpp'
       - 'llarm-asm/**/CMakeLists.txt'
@@ -25,6 +26,7 @@ on:
       - 'llarm-emu/**/CMakeLists.txt'
       - 'llarm-emu/**/*.cmake'
       - 'llarm-emu/**/*.cmake.in'
+      - 'llarm-emu/tests/**'
       - 'llarm-asm/**/*.cpp'
       - 'llarm-asm/**/*.hpp'
       - 'llarm-asm/**/CMakeLists.txt'
@@ -62,6 +64,12 @@ jobs:
       - name: Build
         run: cmake --build llarm-emu/build --parallel
 
+      - name: Install ARM toolchain
+        run: sudo apt-get install -y binutils-arm-none-eabi
+
+      - name: Run integration tests
+        run: bash llarm-emu/tests/run_tests.sh llarm-emu/build/llarm-emu
+
       - name: Install clang-tidy
         run: sudo apt-get install -y clang-tidy clang-tools
 
diff --git a/llarm-asm/src/assemble/arm/generators.cpp b/llarm-asm/src/assemble/arm/generators.cpp
@@ -13,6 +13,7 @@ u32 generators::arm(const IR_arm_struct& IR) {
         case arm_id::UNKNOWN: return 0;
         case arm_id::UNDEFINED:  return 0;
         case arm_id::NOP: return 0;
+        case arm_id::HALT: return 0xE7FFDEAD; // custom instruction, not a real one
         case arm_id::ADC: return data_instruction(id, operands);
         case arm_id::ADD: return data_instruction(id, operands);
         case arm_id::AND: return data_instruction(id, operands);
diff --git a/llarm-asm/src/disassemble/disassemble.cpp b/llarm-asm/src/disassemble/disassemble.cpp
@@ -324,7 +324,8 @@ std::string disassemble::arm_generate(const u32 code, const u32 PC, const settin
         case arm_id::UXTB: return generators::arm::math::UXTB(code, settings);
         case arm_id::UXTB16: return generators::arm::math::UXTB16(code, settings);
         case arm_id::UXTH: return generators::arm::math::UXTH(code, settings);
-        case arm_id::NOP: return generators::arm::misc::NOP();
+        case arm_id::NOP: return "NOP";
+        case arm_id::HALT: return "HALT";
         case arm_id::UNKNOWN: llarm::out::error("Unknown instruction encountered for disassembly");
         case arm_id::UNDEFINED: return UNDEFINED;
         break;
@@ -444,10 +445,11 @@ std::string disassemble::arm_id_to_string(const arm_id id) {
     switch (id) {
         case arm_id::UNKNOWN: return ERROR;
         case arm_id::UNDEFINED: return UNDEFINED; 
+        case arm_id::NOP: return "NOP"; 
+        case arm_id::HALT: return "HALT";
         case arm_id::ADC: return "ADC"; 
         case arm_id::ADD: return "ADD"; 
         case arm_id::AND: return "AND"; 
-        case arm_id::NOP: return "NOP"; 
         case arm_id::B: return "B"; 
         case arm_id::BL: return "BL"; 
         case arm_id::BIC: return "BIC"; 
diff --git a/llarm-asm/src/disassemble/generators/arm/misc.cpp b/llarm-asm/src/disassemble/generators/arm/misc.cpp
@@ -71,15 +71,6 @@ std::string generators::arm::misc::SWI(const u32 code, const settings& settings)
 }
 
 
-/**
- * This isn't a real instruction documentated in the ARM docs, 
- * but i'm still adding this here for the sake of convenience
- */
-std::string generators::arm::misc::NOP() {
-    return "NOP";
-}
-
-
 /**
  * CPS<effect> <iflags> {, #<mode>}
  * CPS #<mode>
diff --git a/llarm-asm/src/disassemble/generators/generators.hpp b/llarm-asm/src/disassemble/generators/generators.hpp
@@ -137,7 +137,6 @@ namespace internal::generators {
         }
 
         namespace misc {
-            std::string NOP();
             std::string CMNP(const u32 code, const settings& settings);
             std::string CMPP(const u32 code, const settings& settings);
             std::string TEQP(const u32 code, const settings& settings);
diff --git a/llarm-asm/src/id/instruction_id.hpp b/llarm-asm/src/id/instruction_id.hpp
@@ -7,6 +7,7 @@ namespace internal {
         UNKNOWN,
         UNDEFINED,
         NOP,
+        HALT,
 
         // ARMv1 and 26-bit architecture instructions
         ADC,
diff --git a/llarm-asm/src/identifiers/bin_arm.cpp b/llarm-asm/src/identifiers/bin_arm.cpp
@@ -852,7 +852,7 @@ arm_id ident::bin_arm::coproc_and_floats(const u32 code) {
 arm_id ident::bin_arm::arm(const u32 code) {
     // note: NOP is not handled because it's a pseudo 
     // instruction that's unique to this project. 
-    
+
     if (llarm::util::bit_range(code, 28, 31) == 0b1111) {
         const arm_id tmp = unconditional(code);
 
@@ -931,6 +931,11 @@ arm_id ident::bin_arm::arm(const u32 code) {
                 return pack_and_saturates(code);
             }
 
+            // special instruction opcode, doesn't exist on real systems
+            if (code == 0xE7FFDEAD) {
+                return arm_id::HALT;
+            }
+
             // load/store register offset
             return load_store(code);
         
diff --git a/llarm-asm/src/interpreter/mnemonic_arm.cpp b/llarm-asm/src/interpreter/mnemonic_arm.cpp
@@ -381,6 +381,7 @@ mnemonic_struct_arm mnemonic_arm::fetch_mnemonic_args(const arm_id id, sv mnemon
         case arm_id::MRC2:
         case arm_id::BKPT:
         case arm_id::NOP: // maybe this shouldn't be here since it's a unique instruction to the project, idk
+        case arm_id::HALT: // same here
         case arm_id::PLD: 
         case arm_id::SETEND:
             args.cond_id = cond_id::NONE;
diff --git a/llarm-asm/src/validation/bin_arm.cpp b/llarm-asm/src/validation/bin_arm.cpp
@@ -101,6 +101,7 @@ bool validation::bin_arm::is_arm_instruction_valid(const u32 code) {
         case arm_id::UNKNOWN: return false;
         case arm_id::UNDEFINED: return false;
         case arm_id::NOP: return false;
+        case arm_id::HALT: return false;
         case arm_id::ADC: return check_shifter(code, shifter_category::DATA);
         case arm_id::ADD: return check_shifter(code, shifter_category::DATA);
         case arm_id::RSB: return check_shifter(code, shifter_category::DATA);
diff --git a/llarm-asm/src/validation/string_arm.cpp b/llarm-asm/src/validation/string_arm.cpp
@@ -26,6 +26,7 @@ bool validation::string_arm::is_arm_instruction_valid(const IR_arm_struct& IR) {
         case arm_id::UNKNOWN: return false;
         case arm_id::UNDEFINED: return false;
         case arm_id::NOP: return false;
+        case arm_id::HALT: return false;
 
         // addressing mode 1: data processing
         case arm_id::ADC: 
diff --git a/llarm-emu/src/cpu/core/core.cpp b/llarm-emu/src/cpu/core/core.cpp
@@ -109,6 +109,10 @@ inline void CORE::thumb_cycle_headless() {
 void CORE::headless_mode() {
     while (true) {
         if (is_halted) {
+            if (is_terminated) {
+                return;
+            }
+
             if (vic.fiq_pending() && !reg.read(id::cpsr::F)) { 
                 is_halted = false; 
                 exception.fiq(); 
diff --git a/llarm-emu/src/cpu/core/core.hpp b/llarm-emu/src/cpu/core/core.hpp
@@ -61,6 +61,7 @@ struct CORE {
 
     // internal core state variables
     bool is_halted = false;
+    bool is_terminated = false;
 
     void initialise(const bool is_headless = false);
 
@@ -102,7 +103,7 @@ struct CORE {
         fcse(coprocessor, settings),
         memory(reg, ram, mmu, mpu, fcse, arch_26, exception, settings, cache, coprocessor),
         address_mode(reg),
-        instructions(reg, address_mode, coprocessor, settings, memory, exception, vfp_reg, vfp_exception, vfp_addressing_mode),
+        instructions(reg, address_mode, coprocessor, settings, memory, exception, vfp_reg, vfp_exception, vfp_addressing_mode, is_halted, is_terminated),
         fetch(reg, memory, globals),
         decode(reg, settings),
         execute(instructions, exception)
diff --git a/llarm-emu/src/cpu/core/cycle/decode.cpp b/llarm-emu/src/cpu/core/cycle/decode.cpp
@@ -46,6 +46,7 @@ bool DECODE::is_arm_instruction_unsupported(const llarm::as::arm_id id) const {
             case arm_id::B:
             case arm_id::BL:
             case arm_id::NOP:
+            case arm_id::HALT:
             case arm_id::CMNP:
             case arm_id::CMPP:
             case arm_id::TEQP:
diff --git a/llarm-emu/src/cpu/core/cycle/execute.cpp b/llarm-emu/src/cpu/core/cycle/execute.cpp
@@ -16,6 +16,8 @@ void EXECUTE::arm_execute(const arm_decode_struct &instruction) {
     switch (id) {
         case arm_id::UNKNOWN: llarm::out::dev_error("Unknown instruction attempted to be executed");
         case arm_id::UNDEFINED: exception.undefined(); return;
+        case arm_id::NOP: instructions.arm.misc.NOP(); return;
+        case arm_id::HALT: instructions.arm.misc.HALT(); return;
         case arm_id::ADC: instructions.arm.math.ADC(code); return;
         case arm_id::ADD: instructions.arm.math.ADD(code); return;
         case arm_id::RSB: instructions.arm.math.RSB(code); return;
@@ -34,7 +36,6 @@ void EXECUTE::arm_execute(const arm_decode_struct &instruction) {
         case arm_id::MVN: instructions.arm.movement.MVN(code); return;
         case arm_id::B: instructions.arm.branching.B(code); return;
         case arm_id::BL: instructions.arm.branching.BL(code); return;
-        case arm_id::NOP: instructions.arm.misc.NOP(); return;
         case arm_id::CMNP: instructions.arm.misc.PSR(code); return;
         case arm_id::CMPP: instructions.arm.misc.PSR(code); return;
         case arm_id::TEQP: instructions.arm.misc.PSR(code); return;
@@ -318,14 +319,14 @@ void EXECUTE::thumb_execute(const thumb_decode_struct &instruction) {
         case thumb_id::STRB2: instructions.thumb.store.STRB2(code); return;
         case thumb_id::STRH1: instructions.thumb.store.STRH1(code); return;
         case thumb_id::STRH2: instructions.thumb.store.STRH2(code); return;
-        case internal::thumb_id::CPS: // TODO
-        case internal::thumb_id::REV16: // TODO
-        case internal::thumb_id::REVSH: // TODO
-        case internal::thumb_id::SETEND: // TODO
-        case internal::thumb_id::SXTB: // TODO
-        case internal::thumb_id::SXTH: // TODO
-        case internal::thumb_id::UXTB: // TODO
-        case internal::thumb_id::UXTH: // TODO
+        case thumb_id::CPS: // TODO
+        case thumb_id::REV16: // TODO
+        case thumb_id::REVSH: // TODO
+        case thumb_id::SETEND: // TODO
+        case thumb_id::SXTB: // TODO
+        case thumb_id::SXTH: // TODO
+        case thumb_id::UXTB: // TODO
+        case thumb_id::UXTH: // TODO
                 break;
         }
 }
diff --git a/llarm-emu/src/cpu/core/cycle/execute.hpp b/llarm-emu/src/cpu/core/cycle/execute.hpp
@@ -16,7 +16,7 @@ struct EXECUTE {
         INSTRUCTIONS& instructions, 
         EXCEPTION& exception
     ) : instructions(instructions), 
-        exception(exception) 
+        exception(exception)
     {
 
     }
diff --git a/llarm-emu/src/cpu/instructions/arm/misc.cpp b/llarm-emu/src/cpu/instructions/arm/misc.cpp
@@ -10,6 +10,12 @@ void INSTRUCTIONS::arm::misc::NOP() {
 }
 
 
+void INSTRUCTIONS::arm::misc::HALT() {
+    is_halted = true;
+    is_terminated = true;
+}
+
+
 /** TODO, this part needs to be extensively analysed (A2-9)
  * if ConditionPassed(<cond>) then
  *    case <opc> of
diff --git a/llarm-emu/src/cpu/instructions/instructions.hpp b/llarm-emu/src/cpu/instructions/instructions.hpp
@@ -16,6 +16,8 @@ struct INSTRUCTIONS {
     COPROCESSOR& coprocessor;
     SETTINGS& settings;
     MEMORY& memory;
+    bool& is_halted;
+    bool& is_terminated;
 
     struct arm {
         struct math {
@@ -123,15 +125,24 @@ struct INSTRUCTIONS {
             REGISTERS& reg;
             ADDRESSING_MODE& address_mode;
             COPROCESSOR& coprocessor;
+            bool& is_halted;
+            bool& is_terminated;
 
             misc(
                 REGISTERS& reg, 
-                
                 ADDRESSING_MODE& address_mode,
-                COPROCESSOR& coprocessor
-            ) : reg(reg), address_mode(address_mode), coprocessor(coprocessor) {}
+                COPROCESSOR& coprocessor,
+                bool& is_halted,
+                bool& is_terminated
+            ) : reg(reg), 
+                address_mode(address_mode), 
+                coprocessor(coprocessor),
+                is_halted(is_halted),
+                is_terminated(is_terminated)
+            {}
 
             void NOP();
+            void HALT();
             void PSR(const u32 code);
             void SWI();
             void BKPT();
@@ -327,14 +338,16 @@ struct INSTRUCTIONS {
             EXCEPTION& exception,
             VFP_REG& vfp_reg,
             VFP_EXCEPTION& vfp_exception,
-            VFP_ADDRESS_MODE& vfp_addressing_mode
+            VFP_ADDRESS_MODE& vfp_addressing_mode,
+            bool& is_halted,
+            bool& is_terminated
         ) : math(reg, address_mode),
             logic(reg, address_mode),
             movement(reg, address_mode),
             multiply(reg),
             branching(reg),
             coproc(reg, address_mode, coprocessor),
-            misc(reg, address_mode, coprocessor),
+            misc(reg, address_mode, coprocessor, is_halted, is_terminated),
             load(reg, memory, address_mode, settings),
             store(reg, memory, address_mode),
             dsp(reg, memory, address_mode, exception),
@@ -503,20 +516,23 @@ struct INSTRUCTIONS {
     INSTRUCTIONS(
         REGISTERS& reg, 
         ADDRESSING_MODE& address_mode,
-        
         COPROCESSOR& coprocessor,
         SETTINGS& settings,
         MEMORY& memory,
         EXCEPTION& exception,
         VFP_REG& vfp_reg,
         VFP_EXCEPTION& vfp_exception,
-        VFP_ADDRESS_MODE& vfp_addressing_mode
+        VFP_ADDRESS_MODE& vfp_addressing_mode,
+        bool& is_halted,
+        bool& is_terminated
     ) : reg(reg),
         address_mode(address_mode),
         coprocessor(coprocessor),
         settings(settings),
         memory(memory),
-        arm(reg, address_mode, coprocessor, memory, settings, exception, vfp_reg, vfp_exception, vfp_addressing_mode),
+        is_halted(is_halted),
+        is_terminated(is_terminated),
+        arm(reg, address_mode, coprocessor, memory, settings, exception, vfp_reg, vfp_exception, vfp_addressing_mode, is_halted, is_terminated),
         thumb(reg, settings, memory)
     {
 
diff --git a/llarm-emu/tests/emulator.cpp b/llarm-emu/tests/emulator.cpp
diff --git a/llarm-emu/tests/peripherals/uart/uart_test.s b/llarm-emu/tests/peripherals/uart/uart_test.s
@@ -20,7 +20,7 @@ _start:
     str r3, [r0] // write to UARTDR
     b 1b
 2:
-    b 2b @ halt
+    .word 0xE7FFDEAD @ halt
 
 msg:
-    .asciz  "If you can read this, the UART emulation works.\n"
+    .asciz  "If you can read this, the UART emulation worked.\n"
diff --git a/llarm-emu/tests/run_tests.sh b/llarm-emu/tests/run_tests.sh
@@ -0,0 +1,63 @@
+#!/usr/bin/env bash
+set -uo pipefail
+
+EMULATOR=${1:?usage: run_tests.sh <path-to-llarm-emu>}
+TESTS_DIR="$(cd "$(dirname "$0")" && pwd)"
+TIMEOUT=10
+
+PASS=0
+FAIL=0
+
+RED='\033[0;31m'
+GRN='\033[0;32m'
+RST='\033[0m'
+
+run_test() {
+    local name="$1"
+    local dir="$TESTS_DIR/$2"
+    local binary="$3"
+    local expected="$4"
+
+    printf "  %-52s" "$name"
+
+    if ! make -C "$dir" --silent 2>/dev/null; then
+        printf "${RED}FAIL${RST} (assembly error)\n"
+        ((FAIL++))
+        return
+    fi
+
+    local actual
+    if ! actual=$(timeout "$TIMEOUT" "$EMULATOR" "$dir/$binary" 2>/dev/null); then
+        local rc=$?
+        if [ "$rc" -eq 124 ]; then
+            printf "${RED}FAIL${RST} (timeout after ${TIMEOUT}s)\n"
+        else
+            printf "${RED}FAIL${RST} (emulator exited with code $rc)\n"
+        fi
+        ((FAIL++))
+        return
+    fi
+
+    if [ "$actual" = "$expected" ]; then
+        printf "${GRN}PASS${RST}\n"
+        ((PASS++))
+    else
+        printf "${RED}FAIL${RST} (output mismatch)\n"
+        printf "    expected: %s\n" "$expected"
+        printf "    actual:   %s\n" "$actual"
+        ((FAIL++))
+    fi
+}
+
+echo "llarm-emu integration tests"
+echo "==========================="
+
+# peripherals
+run_test "uart: basic TX output" \
+    "peripherals/uart" \
+    "uart_test.bin" \
+    "If you can read this, the UART emulation worked."
+
+echo ""
+echo "Results: ${PASS} passed, ${FAIL} failed"
+[ "$FAIL" -eq 0 ]

Original file line number	Diff line number	Diff line change
`@@ -137,7 +137,6 @@ namespace internal::generators {`
`137`	`137`	`}`
`138`	`138`
`139`	`139`	`namespace misc {`
`140`		`- std::string NOP();`
`141`	`140`	`std::string CMNP(const u32 code, const settings& settings);`
`142`	`141`	`std::string CMPP(const u32 code, const settings& settings);`
`143`	`142`	`std::string TEQP(const u32 code, const settings& settings);`