diff --git a/dts/bindings/i3c/cdns,i3c.yaml b/dts/bindings/i3c/cdns,i3c.yaml index 9708fc6903ec2..8f550fd2d2482 100644 --- a/dts/bindings/i3c/cdns,i3c.yaml +++ b/dts/bindings/i3c/cdns,i3c.yaml @@ -23,4 +23,4 @@ properties: ibid-thr: type: int default: 1 - description: IBI Data Fifo Threashold Value + description: IBI Data FIFO Threshold Value diff --git a/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml b/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml index 6b5a028ca18b4..da0c0545515a1 100644 --- a/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml +++ b/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml @@ -9,7 +9,7 @@ properties: type: array required: true description: | - Many DEC/MEC periperals interrupt signals are direct capable. The signals are + Many DEC/MEC peripherals interrupt signals are direct capable. The signals are connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers: status(latched or r/w1-c), set-enable, clr-enable, and result (read-only). The read-only result register bits are the bitwise AND of status and enable. diff --git a/dts/bindings/interrupt-controller/sifive,clint0.yaml b/dts/bindings/interrupt-controller/sifive,clint0.yaml index 608b17b1a4f7b..c476f168b6b46 100644 --- a/dts/bindings/interrupt-controller/sifive,clint0.yaml +++ b/dts/bindings/interrupt-controller/sifive,clint0.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -description: SiFive RISC-V Core-Local Interruptor. +description: SiFive RISC-V Core-Local Interrupt Controller. compatible: "sifive,clint0" diff --git a/dts/bindings/ospi/st,stm32-ospi.yaml b/dts/bindings/ospi/st,stm32-ospi.yaml index f28abdbb1e144..f0c1a5ce1068c 100644 --- a/dts/bindings/ospi/st,stm32-ospi.yaml +++ b/dts/bindings/ospi/st,stm32-ospi.yaml @@ -59,7 +59,7 @@ properties: - For channel configuration, only the config bits priority and periph/mem datasize are used. The periph/mem datasize must be equal, 0 is a correct value. - - There is no Fifo used by this DMA peripheral. + - There is no FIFO used by this DMA peripheral. For example dmas for TX/RX on OSPI dmas = <&dma1 5 41 0x10000>; diff --git a/dts/bindings/pinctrl/adi,max32-pinctrl.yaml b/dts/bindings/pinctrl/adi,max32-pinctrl.yaml index 712600609218c..f45c106cbb79d 100644 --- a/dts/bindings/pinctrl/adi,max32-pinctrl.yaml +++ b/dts/bindings/pinctrl/adi,max32-pinctrl.yaml @@ -52,7 +52,7 @@ child-binding: * 4 : Alternate Function 4 In case selected pin function is GPIO, pin is statically configured as a plain input/output GPIO. Default configuration is input. Output value - can be configured by adding 'ouptut-low' or 'output-high' properties + can be configured by adding 'output-low' or 'output-high' properties to the pin configuration. To simplify the usage, macro is available to generate "pinmux" field. diff --git a/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml b/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml index fd4b2e37358d6..fa0a2e20dd1e3 100644 --- a/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml +++ b/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml @@ -78,7 +78,7 @@ child-binding: Encodes port/pin and alternate function. See helper macro XMC4XX_PINMUX_SET(). Alternate function is only set for output pins; It selects ALT1-ALT4 output line in the GPIO element. The alternate function for input pins is - handled separately by the peripheral. It is upto the peripheral to configure which + handled separately by the peripheral. It is up to the peripheral to configure which input pin to use (For example see parameter input-src in infineon,xmc4xxx-uart.yaml). required: true type: int diff --git a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml index 0be9533919eff..34f822cb9986c 100644 --- a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -70,7 +70,7 @@ child-binding: * 17 : GPIO In case selected pin function is GPIO, pin is statically configured as a plain input/output GPIO. Default configuration is input. Output value - can be configured by adding 'ouptut-low' or 'output-high' properties + can be configured by adding 'output-low' or 'output-high' properties to the pin configuration. To simplify the usage, macro is available to generate "pinmux" field. diff --git a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml index 6de98d270587d..1c12f833390a9 100644 --- a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml +++ b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml @@ -73,7 +73,7 @@ child-binding: * 2 : Analog * 3 : GPIO output In case selected pin function is GPIO output, pin is statically configured as - a plain output GPIO, which configuration can be set by adding 'ouptut-low' or + a plain output GPIO, which configuration can be set by adding 'output-low' or 'output-high' properties to the pinctrl configuration. Default is output-low. - remap: The pin remapping configuration. It allows to assign the pin function to a different peripheral. Remain configuration can be: diff --git a/dts/bindings/regulator/regulator.yaml b/dts/bindings/regulator/regulator.yaml index b072ce8c9200f..760c1917141e6 100644 --- a/dts/bindings/regulator/regulator.yaml +++ b/dts/bindings/regulator/regulator.yaml @@ -17,7 +17,7 @@ properties: regulator-init-microvolt: type: int - description: Voltage set during initialisation + description: Voltage set during initialization regulator-min-microvolt: type: int @@ -33,7 +33,7 @@ properties: regulator-init-microamp: type: int - description: Current set during initialisation + description: Current set during initialization regulator-min-microamp: type: int @@ -78,7 +78,7 @@ properties: type: int description: | ramp delay for regulator(in uV/us) For hardware which supports disabling - ramp rate, it should be explicitly initialised to zero + ramp rate, it should be explicitly initialized to zero (regulator-ramp-delay = <0>) for disabling ramp delay. regulator-enable-ramp-delay: diff --git a/dts/bindings/retained_mem/zephyr,retained-ram.yaml b/dts/bindings/retained_mem/zephyr,retained-ram.yaml index 0b11fdd1bff93..b01063db668c5 100644 --- a/dts/bindings/retained_mem/zephyr,retained-ram.yaml +++ b/dts/bindings/retained_mem/zephyr,retained-ram.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -description: Uninitialised RAM-based retained memory area. +description: Uninitialized RAM-based retained memory area. compatible: "zephyr,retained-ram" diff --git a/dts/bindings/rtc/silabs,gecko-stimer.yaml b/dts/bindings/rtc/silabs,gecko-stimer.yaml index cc45a2ae96753..66e2077f48c98 100644 --- a/dts/bindings/rtc/silabs,gecko-stimer.yaml +++ b/dts/bindings/rtc/silabs,gecko-stimer.yaml @@ -8,7 +8,7 @@ description: | real-time counter that allows for precise timekeeping. The sleeptimer utilizes hardware timer(SYSRTC) to manage ticks and timeouts. gecko stimer uses sleeptimer service from Silicon - Labs SDK which can run mulitple sw timers using a single counter. + Labs SDK which can run multiple sw timers using a single counter. The sleeptimer service itself manages the IRQ handling, and the gecko stimer driver seamlessly connects to the IRQ utilized by the sleeptimer service. diff --git a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml index 788ea54c9568d..e7b0624d9004d 100644 --- a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml +++ b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml @@ -45,8 +45,8 @@ properties: fifo-tx-size: description: | - Fifo size used for buffering transmit bytes. A value of 0 implies that - the fifo is not used while transmitting. transmitting. If the UART is used in async mode + FIFO size used for buffering transmit bytes. A value of 0 implies that + the FIFO is not used while transmitting. If the UART is used in async mode then fifo-tx-size should be set to 0. required: true type: int @@ -61,8 +61,8 @@ properties: fifo-rx-size: description: | - Fifo size used for buffering received bytes. A value of 0 implies that - the fifo is not used while receiving. If the UART is used in async mode + FIFO size used for buffering received bytes. A value of 0 implies that + the FIFO is not used while receiving. If the UART is used in async mode then fifo-rx-size should be set to 0. required: true type: int diff --git a/dts/bindings/watchdog/gd,gd32-fwdgt.yaml b/dts/bindings/watchdog/gd,gd32-fwdgt.yaml index 66499614ca3eb..4cbffab3b8638 100644 --- a/dts/bindings/watchdog/gd,gd32-fwdgt.yaml +++ b/dts/bindings/watchdog/gd,gd32-fwdgt.yaml @@ -18,7 +18,7 @@ properties: Set timeout value in milliseconds. The following equation gives the maximum timeout value - timeout = (reload + 1) / (peripheral_freqency / prescaler). + timeout = (reload + 1) / (peripheral_frequency / prescaler). where the maximum prescaler = 256 and the maximum reload = 4096. The peripheral_frequency uses GD32_LOW_SPEED_IRC_FREQUENCY