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<h1>近期发表期刊论文</h1>
<p><span style="font-size:18px;"></span></p>
<ol style="list-style-type:decimal;" class=" list-paddingleft-2">
<li><p>S. Lu, J. Lu, J. Lin, and Z. Wang, A Hardware-Oriented and Memory-Efficient Method for CTC Decoding, IEEE Access, vol. 7, pp. 120681-120694, 2019.</p></li>
<li><p>C. Zhu, R. Liang, J. Lin, Z. Wang, and L. Li Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs</p></li>
<li><p>W. Li, J. Lin, and Z. Wang, A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes, IEEE Trans. Circuits Syst. I, Reg. Papers, vol.66, no.8, pp. 3174-3187, Aug., 2019. </p></li>
<li><p>H. Cui, J. Lin, and Z. Wang, An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes, IEEE Trans. Circuits Syst. I, Reg. Papers, vol.66, no.8, pp. 3188-3200, Aug., 2019. </p></li>
<li><p>M. Wang, Z. Wang, J. Lu, J. Lin, and Z. Wang, E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 2, pp. 280-291, Jun., 2019. </p></li>
<li><p>J. Tian, S. Song, J. Lin, and Z. Wang, Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes, IEEE Access, vol. 7, pp. 50980-50992, 2019. </p></li>
<li><p>Y. Zhou, J. Lin, and Z. Wang, Improved Fast-SSC-Flip Decoding of Polar Codes, IEEE Communications Letters, vol. 23, no. 6, pp. 950-953, Jun., 2019. </p></li>
<li><p>W. Li, J. Tian, J. Lin, and Z. Wang, Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders, IEEE Communications Letters, vol. 23, no. 5, pp. 785-788, May, 2019. </p></li>
<li><p>X. Liu, L. Zi, D. Yang, and Z. Wang, Improved Decoding Algorithms of LDPC Codes Based on Reliability Metrics of Variable Nodes, IEEE Access, vol. 7, pp. 35769-35778, 2019. </p></li>
<li><p>J. Tian, S. Song, J. Lin, and Z. Wang, Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes, IEEE Trans. Circuits Syst. II, Exp. Brief, online published, 2019. </p></li>
<li><p>Y. Wang, J. Lin, and Z. Wang, “FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 1, pp. 288-301, Jan., 2019. </p></li>
<li><p>C. Zhu, J. Lin and Z. Wang, “Background Calibration of Comparator Offsets in SHA-less pipelined ADCs,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 66, no. 3, pp. 357-361, Mar., 2019. </p></li>
<li><p>C. Zhu, J. Lin and Z. Wang, “A new clock phase calibration method in high-speed and high resolution DACs,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 66, no. 3, pp. 332-336, Mar., 2019. </p></li>
<li><p>H. Cui, J. Lin and Z. Wang, “An Efficient Post Processor for Lowering the Error Floor of LDPC Codes,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 66, no. 1, pp. 397-401, Mar., 2019. </p></li>
<li><p>Y. Zhou, J. Lin and Z. Wang, “A high speed successive cancellation decoder for polar codes using approximate computing,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 66, no. 2, pp. 227-231, Feb., 2019. </p></li>
<li><p>Z. Wang, J. Lin and Z. Wang, “Hardware-Oriented compression of long-short term memory for efficient inference, IEEE Signal Processing Letter, vol. 25, no. 7, pp. 984-988, Jul., 2018. </p></li>
<li><p>J. Zeng, J. Lin and Z. Wang, “Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems,” IEEE Wireless Communications Letters, vol. 7, no. 5, pp. 708-711, Oct., 2018. </p></li>
<li><p>J. Zeng, J. Lin and Z. Wang, “An Improved Gauss-Seidel Algorithm and its Efficient Architecture for Massive MIMO Systems,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 65, no. 9, pp. 1194-1198, Sep., 2018. </p></li>
<li><p>X. Liu, F. Xiong, Z. Wang, and S. Liang Design of Binary LDPC Codes with Parallel Vector Message Passing, IEEE Trans. Comm., vol. 66, no. 4, pp. 1363-1375, Apr., 2018. </p></li>
<li><p><span>J. Wang, J. Lin and Z. Wang, “Efficient hardware architectures for deep convolutional neural network”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol.65, no.6, pp. 1941-1953, Jun., 2018.</span><em><strong><span>(Transactions on Circuits and Systems top 10 monthly popular documents for over 12 months</span></em></strong><span>)</span></span></p></li>
<li><p>Y. Wang, J. Lin and Z. Wang, “An energy-efficient high-performance architecture for binary weight convolutional neural networks”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 2, pp. 280-293, Feb., 2018. </p></li>
<li><p>J. Tian, J. Lin and Z. Wang, “A 21.66Gbps non-binary LDPC decoder for high-speed communications”, IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 65, no. 2, pp. 226-230, Sep., 2018. </p></li>
<li><p>Z. Wang, J. Lin and Z. Wang, “Accelerating recurrent neural networks: a memory-efficient approach”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., In Press, vol. 25, no. 10, pp. 2763-2775, Oct., 2017. </p></li>
<li><p>J. Lin, Z. Yan and Z. Wang, “Efficient soft cancelation decoder architectures for polar codes”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., In Press, vol. 25, no. 1, pp. 87-99, Jan. 2017 (Transactions on VLSI Systems Top 25 Downloaded, 2017) </p></li>
<li><p>J. Lin, C. Xiong and Z. Yan, “A high throughput list decoder architecture for polar codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 6, pp. 2378-2391, Jun. 2016 </p></li>
<li><p>J. Lin and Z. Yan, “Efficient list decoder architecture for polar codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 11, pp. 2508-2518, Nov. 2015 </p></li>
<li><p><span>J. Lin and Z. Yan, “An efficient fully parallel decoder architecture for Non-binary LDPC codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 12, pp. 2649-2660, Dec. 2014 (</span><em><strong><span>Transactions on VLSI Systems Top 20 Downloaded, December 2014</span></strong></em><span>)</span></p></li>
</ol><p><br></p>
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<h1>往期代表性杂志论文（节选）</h1><p><span style="font-size:18px;"></span></p>
<ol style="list-style-type:decimal;" class=" list-paddingleft-2">
<li><p>Z. Wang, Z. Chi and K. Parhi, 'Area–Efficient High Speed Turbo Decoder Architectures”, IEEE Trans. on VLSI Systems, vol. 10, no. 6, pp. 902-912, December, 2002.</p></li>
<li><p>Z. Wang and K. Parhi, 'High Performance, High Throughput Turbo/SOVA Decoder Design', IEEE Trans. on Communications, vol. 51, no 4, April 2003, pp. 570-79.</p></li>
<li><p><span>Z. Wang and J. Ma “Fast Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes”, in IEEE Trans. on VLSI Systems, vol. 14, no. 9, pp. 937-950, Sep. 2006 (</span><em><strong><span>IEEE VLSI Transactions Best Paper Award in 2007</span></strong></em><span>) .</span></p></li>
<li><p><span>Z. Wang and Z. Cui, “Low Complexity, High Speed Decoder Design for Quasi-Cyclic Low Density Parity Check Codes”, in IEEE Trans. on VLSI Systems, vol. 15, no. 1, Jan. 2007 (</span><em><strong><span>Top 4 most downloaded papers in IEEE Trans. on VLSI Systems in 2007</span></strong></em><span>).</span></p></li>
<li><p>Z. Wang, “High-Speed Recursion Architecture for Turbo/MAP Decoders”, in IEEE Trans. on VLSI Systems in Apr. 2007.</p></li>
<li><p>Z. Wang and Q. Li, “Very Low Complexity Hardware Interleaver for Turbo Decoding,” in IEEE Trans. on Circuits and Systems: II, Sep. 2007.</p></li>
<li><p>J. Ma, A. Vardy, and Z. Wang, “Low-latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes,” in IEEE Trans. on VLSI Systems, Nov. 2007.</p></li>
<li><p><span>Z. Cui and Z. Wang “High Speed Layered LDPC Decoder Architecture for QC-LDPC Codes,” in IEEE Trans. on VLSI Systems in Apr. 2009 (</span><em><strong><span>Top 8 most downloaded papers in IEEE Trans. on VLSI in 2009</span></strong></em><span>).</span></p></li>
<li><p><span>J. Sha, Z. Wang, M. Gao, and L. Li, “Multi-Gb LDPC Code Design and Implementation,” in IEEE Trans. on VLAI Systems in Feb. 2009 (</span><em><strong><span>Top 5 most downloaded papers in IEEE Trans. on VLSI in 2009</span></strong></em><span>).</span></p></li>
<li><p>J. He, Z. Wang, and H. Liu, “An Efficient 4-D 8PSK Trellis-Coded Modulator Decoder Architecture” in IEEE Trans. on VLSI Systems in Jan. 2010.</p></li>
<li><p>C. Zhang, Z. Wang, etc, “Flexible LDPC Decoder Design for Multi-Gb/s Applications,” in IEEE Transactions on Circuits and Systems: I, Jan. 2010.</p></li>
<li><p>J. Lin, Z. Wang, L. Li, J. Sha, and M. Gao, “Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders,” in IEEE TCAS-II, in Mar. 2009.</p></li>
<li><p>K. Zhang, X. Huang, and Z. Wang, “High Throughput Irregular LDPC Decoder,” in IEEE Journal of Selected Area on Communications (JSAC) in July 2009.</p></li>
<li><p>J. Sha, J. Lin, Z. Wang, and L. Li, “Decoder Design for RS-Based LDPC Codes,” in IEEE Trans. on Circuits and Systems: II, in Sept. 2009.</p></li>
<li><p>J. Lin, J. Sha, Z.Wang, and L. Li, “An Efficient VLSI Architecture for Non-binary LDPC Decoders,” in IEEE Trans. on Circuits and Systems: II, in Dec. 2009.</p></li>
<li><p><span>P. Zhao, J. McNeely, W. Kuang, and Z. Wang, “Design of Sequential elements for Low Power Clocking Systems,” in IEEE Trans. on VLSI, in May 2011 (</span><em><strong><span>Top 18 most downloaded papers in IEEE Trans. on VLSI in 2011</span></strong></em><span>).</span></p></li>
<li><p>J. Lin, J. Sha, Z. Wang, and L. Li, “Efficient Decoder Design for Non-Binary Quasi-Cyclic LDPC Codes,” in IEEE Trans. on CAS-I, Jan. 2010.</p></li>
<li><p>K. Zhang, X. Huang, and Z. Wang, “A High-Throughput LDPC Decoder Architecture with Rate Compatibility,” in IEEE Trans. on Circuits and Systems-I in 2010.</p></li>
<li><p>Z. Wang, Z, Cui, and J. Sha, “VLSI Design for LDPC Codes Decoding,” in IEEE Circuits and Systems Magazine, First quarter, 2011.</p></li>
<li><p><span>J. He, H. Liu, Z. Wang, and X. Huang,, “High-Speed Low-Power Viterbi Decoder Design for TCM Decoders,” in IEEE Trans. on VLSI Systems, in Apr. 2011 (</span><em><strong><span>Top 15 most downloaded papers in IEEE Trans. on VLSI in 2012</span></strong></em><span>).</span></p></li>
<li><p>Z. Cui, Z. Wang, and X. Zhang, “Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes,” in IET on Communications in Oct. 2011.</p></li>
<li><p>K. He, J. Sha, and Z. Wang, ' Non-binary LDPC Code Decoder Architecture with Efficient Check Node Processing,' in IEEE Trans. on Circuits and Systems II 59-(6): 381-385 (2012).</p></li>
<li><p>Z. Wang, “Super FEC Codes for 40/100Gbps Transport Networking,” in IEEE Communication Letters, in Dec. 2012.</p></li>
<li><p>M. Gustlin, Z. Wang, etc, 'Next Generation Backplane and Copper Cable Challenges,' in IEEE Communications Magazine, Dec. 2013.</p></li>
<li><p>C. Zhang, Z. Wang, and X. You, 'Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes,' in IEEE TCAS-II, vol. 61, no. 10, Oct. 2014</p></li>
</ol>
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