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apio error, can find ram.v for j1a  #82

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@jemo07

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@jemo07

Hello, when running

apio verify --board icestick

I get the following error.

iverilog -o hardware.out -D VCD_OUTPUT= -D NO_ICE40_DEFAULT_ASSIGNMENTS "C:\Users\jemo0.apio\packages\tools-oss-cad-suite\share\yosys/ice40/cells_sim.v" j1a.v j1a8k.v j4a.v uart.v
j1a.v:186: Include file ../build/ram.v not found
j1a.v:157: error: Superfluous comma in port declaration list.
j1a.v:168: syntax error
j1a.v:162: error: syntax error in parameter value assignment list.
j1a.v:162: error: Invalid module instantiation
j1a.v:185: syntax error
I give up.
scons: *** [hardware.out] Error 6
============================================= [ ERROR ] Took 0.34 seconds =============================================

Looking at the ja1.vs file I see reference to include "../build/ram.v"

lined 185:
`include "../build/ram.v"

I can't seem to find the path to the parts.
Thanks,

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