Ramping up the clock rate

[bmentink]

Not an issue as such, but due to the lack of a forum will post here.

I would like to run the clock much higher to see what the limit is to run swapforth at.
I tried to het a handle on this by implementing a bare minimal PWM verilog module and ramped up the PLL until the PWM stopped working.
This went ok till about 560Mhz, (2.2MHz PWM at 8 bits) which I thought was pretty awesome ..

As a 1st attempt with swapforth, I doubled the PLL to 96Mhz (7 as the .DIVF instead of 3) and in the uart.v module doubled the CLKFREQ constant to keep the baudrate at 460800 baud. However it does not work. I am not sure if the problem is the uart or just running that fast ... any idea's

[RGD2]

If you disable the random number generator in icestorm/j1a.v, then icetime
makes better sense of it. The loop in that part causes icetime to give
silly results.

On Thursday, 29 September 2016, bmentink [email protected] wrote:

Not an issue as such, but due to the lack of a forum will post here.

I would like to run the clock much higher to see what the limit is to run
swapforth at.
I tried to het a handle on this by implementing a bare minimal PWM verilog
module and ramped up the PLL until the PWM stopped working.
This went ok till about 550Mhz, (2.2MHz PWM at 8 bits) which I thought was
pretty awesome ..

As a 1st attempt with swapforth, I doubled the PLL to 96Mhz (7 as the
.DIVF instead of 3) and in the uart.v module doubled the CLKFREQ constant
to keep the baudrate at 460800 baud. However it does not work. I am not
sure if the problem is the uart or just running that fast ... any idea's

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-- Remy

[bmentink]

Are you meaning the section marked as "Ring Oscillator"? That's the only reference to random I can see .. and what is icetime?

By the way, where are all the modules starting SB_* defined? I would especially like some documentation on those .. I am guessing they are the technology modules for the FPGA ?..

[RGD2]

Yes, that's it.

Look up icetime on Clifford's site.
Scroll down to the "Where is the Documentation?" heading, there's a link there to the Lattice iCE Technology library, which documents all those SB_* things. I'm not actually sure where they're implemented in verilog - it would have to be somewhere in the yosys/icestorm/arachne-pnr toolchain.

[bmentink]

Tried disabling the Ring Oscillator, but still can't run the PLL at 96Mhz ..
.. no response from shell.py .. or minicom

[jamesbowman]

Maybe try leaving the uart unchanged and connecting at 921600?

On Sep 30, 2016 4:34 PM, "bmentink" [email protected] wrote:

Tried disabling the Ring Oscillator, but still can't run the PLL at 96Mhz
..
.. no response from shell.py .. or minicom

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[bmentink]

Tried that, same result. Maybe there is something wrong with the timing at that speed, I don't know enough to do a timing anaylsis ..

EDIT: I ran icetime after removing the random generator code and got Timing estimate: 24.22 ns (41.29 MHz) Is this why it does not run at 96Mhz? .. and probably marginal at current 48Mhz.
However., my pwm code that I managed to clock fine at over 500Mhz reported an icetime value of only 132Mhz .... go figure ...

[bmentink]

Been a couple of weeks now ... any comment @jamesbowman
By the way James, excellent Forth, works very well ......