From 35427ff06d1ce25036f283654f8e37511d087609 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20=C5=BD=C3=A1dn=C3=ADk?= Date: Thu, 5 Jun 2025 09:53:53 +0300 Subject: [PATCH] Add initial draft of the targets registry --- .../design/spirv-extensions/targets/README.md | 47 + .../targets/architectures.asciidoc | 2298 ++++++++ .../design/spirv-extensions/targets/core.json | 4190 ++++++++++++++ .../spirv-extensions/targets/generate.py | 413 ++ .../spirv-extensions/targets/registry.h | 1006 ++++ .../spirv-extensions/targets/targets.asciidoc | 4804 +++++++++++++++++ 6 files changed, 12758 insertions(+) create mode 100644 sycl/doc/design/spirv-extensions/targets/README.md create mode 100644 sycl/doc/design/spirv-extensions/targets/architectures.asciidoc create mode 100644 sycl/doc/design/spirv-extensions/targets/core.json create mode 100644 sycl/doc/design/spirv-extensions/targets/generate.py create mode 100644 sycl/doc/design/spirv-extensions/targets/registry.h create mode 100644 sycl/doc/design/spirv-extensions/targets/targets.asciidoc diff --git a/sycl/doc/design/spirv-extensions/targets/README.md b/sycl/doc/design/spirv-extensions/targets/README.md new file mode 100644 index 0000000000000..25bbb169340a6 --- /dev/null +++ b/sycl/doc/design/spirv-extensions/targets/README.md @@ -0,0 +1,47 @@ +# Targets Registry + +**Version: 0** + +This directory contains a registry of enumerator values for compute device targets, features and architectures used in the SPV_INTEL_function_variants extension. +Other extensions can also adapt this registry + +The authoritative reference file is `core.json`. +From this file the following files are generated using `generate.py`: +* `architectures.asciidoc` - to be used with the `OpSpecConditionalArchitectureINTEL` instruction +* `targets.asciidoc` - to be used with the `OpSpecConditionalTargetINTEL` instruction +* `registry.h` - contains all the values in a C header format + +## Types of entries + +There are two main types of entries, organized as unorded _sets_, or ordered _lists_. +In both cases, each entry has an associated integer value. + +### Targets + +Targets represent the device's Instruction Set Architecture (ISA), for example x86. +* The **Targets** _set_ contains the recognized targets. +* Each target has also a _set_ of **Features** which represent features/extensions of a particular target. +For example, AVX2 is an extension of the x86/x86_64 ISA and thus is available only for those targets. + +### Architectures + +Architectures represent the processor's model or microarchitecture. +* Architecture **categories** define a _set_ of device types, such as CPU, GPU, or other domain-specific accelerators (eg. an AI accelerator). +* Architecture **families** define a _set_ of distinct lines of products within each category. This generally means a vendor, but can also represent two types of devices of the same category within one vendor that are not directly comparable (eg. Vendor X has two lines of CPUs: high-performance CPUs for servers and low-power CPUs for embedded.). +* **Architecture** is an ordered _list_ of architectures. +Within the same category and family, it is meaningful to compare architecture to say, for example, arch. X larger than arch. Y. +Architectures with a larger enumerator value are evaluated as larger than those with smaller values. +The meaning of the ordering is defined by the vendor, but generally, newer architectures are added after older ones. + +## Adding new entries & Versioning + +Adding a new entry to one of the sets or lists is done by incrementing the enumerator and adding the entry at the end of the set / list. +Adding entries this way is backwards-compatible and does not require incrementing the version number. +Likewise, adding a new alias to an existing enumerator value is backwards-compatible. + +Any changes to the meaning of existing enumerator values are backwards-incompatible and should be as rare as possible. +This includes, for example, removing an entry, adding an architecture somewhere else than at the end of the ordered list, or reordering the architectures. +In such cases, the version should be incremented, specifications using this repository will need to update the version, and finally the implementations of the specifications need to adapt to the changed version. + +Version 0 is used for the initial draft until the SPV_INTEL_function_variants extension is ratified as EXT or KHR. +Until then, contents of the registry is subject to change and breaking changes can occur. diff --git a/sycl/doc/design/spirv-extensions/targets/architectures.asciidoc b/sycl/doc/design/spirv-extensions/targets/architectures.asciidoc new file mode 100644 index 0000000000000..8a352e339a31d --- /dev/null +++ b/sycl/doc/design/spirv-extensions/targets/architectures.asciidoc @@ -0,0 +1,2298 @@ + +== Architecture Categories + +[%header,cols="8,3,10"] +|=== +|Name +|Value +|Description + +a| +[source] +---- +unknown +---- +| 0 +| Unknown category + +a| +[source] +---- +cpu +---- +| 1 +| Central processing unit + +a| +[source] +---- +gpu +---- +| 2 +| Graphics processing unit + +a| +[source] +---- +npu +---- +| 3 +| Neural processing unit (AI accelerator) +|=== + +== Architecture Families + +[%header,cols="8,3,3,10"] +|=== +|Name +|Category +|Value +|Description + +4+^|*Category: unknown (0)* + +a| +[source] +---- +generic +---- +| 0 +| 0 +| Generic family + +4+^|*Category: cpu (1)* + +a| +[source] +---- +generic +---- +| 1 +| 0 +| Generic CPU + +a| +[source] +---- +intel +---- +| 1 +| 1 +| Intel main line of CPUs + +a| +[source] +---- +intel_atom +---- +| 1 +| 2 +| Intel Atom/Low-power line of CPUs + +a| +[source] +---- +amd +---- +| 1 +| 3 +| AMD CPU + +a| +[source] +---- +arm_a +---- +| 1 +| 4 +| ARM Cortex-A CPU family + +a| +[source] +---- +arm_m +---- +| 1 +| 5 +| ARM Cortex-M CPU family + +a| +[source] +---- +arm_r +---- +| 1 +| 6 +| ARM Cortex-R CPU family + +a| +[source] +---- +codasip_lp +---- +| 1 +| 7 +| Codasip low-power cores + +a| +[source] +---- +codasip_hp +---- +| 1 +| 8 +| Codasip high-performance cores + +a| +[source] +---- +codasip_ap +---- +| 1 +| 9 +| Codasip application cores + +a| +[source] +---- +sifive_e2 +---- +| 1 +| 10 +| SiFive Essential 2-series + +a| +[source] +---- +sifive_e6 +---- +| 1 +| 11 +| SiFive Essential 6-series + +a| +[source] +---- +sifive_e7 +---- +| 1 +| 12 +| SiFive Essential 7-series + +a| +[source] +---- +sifive_x200 +---- +| 1 +| 13 +| SiFive Essential X200 Series + +a| +[source] +---- +sifive_x300 +---- +| 1 +| 14 +| SiFive Essential X300 Series + +a| +[source] +---- +sifive_xm +---- +| 1 +| 15 +| SiFive Essential XM Series + +a| +[source] +---- +sifive_p400 +---- +| 1 +| 16 +| SiFive Essential P400 Series + +a| +[source] +---- +sifive_p500 +---- +| 1 +| 17 +| SiFive Essential P500 Series + +a| +[source] +---- +sifive_p600 +---- +| 1 +| 18 +| SiFive Essential P600 Series + +a| +[source] +---- +sifive_p800 +---- +| 1 +| 19 +| SiFive Essential P800 Series + +a| +[source] +---- +sifive_e6a +---- +| 1 +| 20 +| SiFive Essential E6-A Series + +a| +[source] +---- +sifive_e7a +---- +| 1 +| 21 +| SiFive Essential E7-A Series + +a| +[source] +---- +sifive_s7a +---- +| 1 +| 22 +| SiFive Essential S7-A Series + +4+^|*Category: gpu (2)* + +a| +[source] +---- +generic +---- +| 2 +| 0 +| Generic GPU + +a| +[source] +---- +intel +---- +| 2 +| 1 +| Intel GPU + +a| +[source] +---- +amd +---- +| 2 +| 2 +| AMD GPU + +a| +[source] +---- +nvidia +---- +| 2 +| 3 +| NVIDIA GPU + +4+^|*Category: npu (3)* + +a| +[source] +---- +generic +---- +| 3 +| 0 +| Generic NPU + +a| +[source] +---- +intel +---- +| 3 +| 1 +| Intel NPU + +a| +[source] +---- +amd_xdna +---- +| 3 +| 2 +| AMD XDNA NPU +|=== + +== Architectures + +[%header,cols="8,3,3,3,10"] +|=== +|Name +|Category +|Family +|Value +|Description + +5+^|*Category: unknown (0), Family: generic (0)* + +a| +[source] +---- +any +---- +| 0 +| 0 +| 0 +| Any architecture + +5+^|*Category: cpu (1), Family: generic (0)* + +a| +[source] +---- +any +---- +| 1 +| 0 +| 0 +| Any CPU + +5+^|*Category: cpu (1), Family: intel (1)* + +a| +[source] +---- +any +---- +| 1 +| 1 +| 0 +| Any Intel CPU + +a| +[source] +---- +nhm +---- +| 1 +| 1 +| 1 +| Intel Nehalem microarchitecture + +a| +[source] +---- +wsm +---- +| 1 +| 1 +| 2 +| Intel Westmere microarchitecture + +a| +[source] +---- +sdb +---- +| 1 +| 1 +| 3 +| Intel Sandy Bridge microarchitecture + +a| +[source] +---- +ivb +---- +| 1 +| 1 +| 4 +| Intel Ivy Bridge microarchitecture + +a| +[source] +---- +hsw +---- +| 1 +| 1 +| 5 +| Intel Haswell microarchitecture + +a| +[source] +---- +bdw +---- +| 1 +| 1 +| 6 +| Intel Broadwell microarchitecture + +a| +[source] +---- +skl +---- +| 1 +| 1 +| 7 +| Intel Skylake microarchitecture + +a| +[source] +---- +pmc +---- +| 1 +| 1 +| 8 +| Intel Palm Cove microarchitecture + +a| +[source] +---- +snc +---- +| 1 +| 1 +| 9 +| Intel Sunny Cove microarchitecture + +a| +[source] +---- +wlc +---- +| 1 +| 1 +| 10 +| Intel Willow Cove microarchitecture + +a| +[source] +---- +cpc +---- +| 1 +| 1 +| 11 +| Intel Cypress Cove microarchitecture + +a| +[source] +---- +gdc +---- +| 1 +| 1 +| 12 +| Intel Golden Cove microarchitecture + +a| +[source] +---- +rpc +---- +| 1 +| 1 +| 13 +| Intel Raptor Cove microarchitecture + +a| +[source] +---- +rdc +---- +| 1 +| 1 +| 14 +| Intel Redwood Cove microarchitecture + +a| +[source] +---- +lnc +---- +| 1 +| 1 +| 15 +| Intel Lion Cove microarchitecture + +5+^|*Category: cpu (1), Family: intel_atom (2)* + +a| +[source] +---- +any +---- +| 1 +| 2 +| 0 +| Any Intel Atom/Low-power CPU + +a| +[source] +---- +bnl +---- +| 1 +| 2 +| 1 +| Intel Bonnell microarchitecture + +a| +[source] +---- +slw +---- +| 1 +| 2 +| 2 +| Intel Saltwell microarchitecture + +a| +[source] +---- +svm +---- +| 1 +| 2 +| 3 +| Intel Silvermont microarchitecture + +a| +[source] +---- +aim +---- +| 1 +| 2 +| 4 +| Intel Airmont microarchitecture + +a| +[source] +---- +gdm +---- +| 1 +| 2 +| 5 +| Intel Goldmont microarchitecture + +a| +[source] +---- +gdm_p +---- +| 1 +| 2 +| 6 +| Intel Goldmont Plus microarchitecture + +a| +[source] +---- +trm +---- +| 1 +| 2 +| 7 +| Intel Tremont microarchitecture + +a| +[source] +---- +gcm +---- +| 1 +| 2 +| 8 +| Intel Gracemont microarchitecture + +a| +[source] +---- +csm +---- +| 1 +| 2 +| 9 +| Intel Crestmont microarchitecture + +a| +[source] +---- +skm +---- +| 1 +| 2 +| 10 +| Intel Skymont microarchitecture + +5+^|*Category: cpu (1), Family: amd (3)* + +a| +[source] +---- +any +---- +| 1 +| 3 +| 0 +| Any AMD CPU + +a| +[source] +---- +zen +---- +| 1 +| 3 +| 1 +| AMD Zen microarchitecture + +a| +[source] +---- +zenp +---- +| 1 +| 3 +| 2 +| AMD Zen+ microarchitecture + +a| +[source] +---- +zen2 +---- +| 1 +| 3 +| 3 +| AMD Zen2 microarchitecture + +a| +[source] +---- +zen3 +---- +| 1 +| 3 +| 4 +| AMD Zen3 microarchitecture + +a| +[source] +---- +zen3p +---- +| 1 +| 3 +| 5 +| AMD Zen3+ microarchitecture + +a| +[source] +---- +zen4 +---- +| 1 +| 3 +| 6 +| AMD Zen4 microarchitecture + +a| +[source] +---- +zen4c +---- +| 1 +| 3 +| 7 +| AMD Zen4c microarchitecture + +a| +[source] +---- +zen5 +---- +| 1 +| 3 +| 8 +| AMD Zen5 microarchitecture + +a| +[source] +---- +zen5c +---- +| 1 +| 3 +| 9 +| AMD Zen5c microarchitecture + +5+^|*Category: cpu (1), Family: arm_a (4)* + +a| +[source] +---- +any +---- +| 1 +| 4 +| 0 +| Any CPU microarchitecture from the ARM Cortex-A family + +a| +[source] +---- +a8 +---- +| 1 +| 4 +| 1 +| ARM Cortex-A8 (32-bit) + +a| +[source] +---- +a9 +---- +| 1 +| 4 +| 2 +| ARM Cortex-A9 (32-bit) + +a| +[source] +---- +a5 +---- +| 1 +| 4 +| 3 +| ARM Cortex-A5 (32-bit) + +a| +[source] +---- +a15 +---- +| 1 +| 4 +| 4 +| ARM Cortex-A15 (32-bit) + +a| +[source] +---- +a7 +---- +| 1 +| 4 +| 5 +| ARM Cortex-A7 (32-bit) + +a| +[source] +---- +a53 +---- +| 1 +| 4 +| 6 +| ARM Cortex-A53 (32/64-bit) + +a| +[source] +---- +a57 +---- +| 1 +| 4 +| 7 +| ARM Cortex-A57 (32/64-bit) + +a| +[source] +---- +a12 +---- +| 1 +| 4 +| 8 +| ARM Cortex-A12 (32-bit) + +a| +[source] +---- +a17 +---- +| 1 +| 4 +| 9 +| ARM Cortex-A17 (32-bit) + +a| +[source] +---- +a32 +---- +| 1 +| 4 +| 10 +| ARM Cortex-A32 (32-bit) + +a| +[source] +---- +a34 +---- +| 1 +| 4 +| 11 +| ARM Cortex-A34 (64-bit) + +a| +[source] +---- +a73 +---- +| 1 +| 4 +| 12 +| ARM Cortex-A73 (32/64-bit) + +a| +[source] +---- +a55 +---- +| 1 +| 4 +| 13 +| ARM Cortex-A55 (32/64-bit) + +a| +[source] +---- +a75 +---- +| 1 +| 4 +| 14 +| ARM Cortex-A75 (32/64-bit) + +a| +[source] +---- +a65 +---- +| 1 +| 4 +| 15 +| ARM Cortex-A65 (64-bit) + +a| +[source] +---- +a76 +---- +| 1 +| 4 +| 16 +| ARM Cortex-A76 (32/64-bit) + +a| +[source] +---- +a77 +---- +| 1 +| 4 +| 17 +| ARM Cortex-A77 (32/64-bit) + +a| +[source] +---- +a78 +---- +| 1 +| 4 +| 18 +| ARM Cortex-A78 (32/64-bit) + +a| +[source] +---- +a78ae +---- +| 1 +| 4 +| 19 +| ARM Cortex-A78AE (32/64-bit) + +a| +[source] +---- +a510 +---- +| 1 +| 4 +| 20 +| ARM Cortex-A510 (64-bit) + +a| +[source] +---- +a710 +---- +| 1 +| 4 +| 21 +| ARM Cortex-A710 (32/64-bit) + +a| +[source] +---- +a510r +---- +| 1 +| 4 +| 22 +| ARM Cortex-A510 (refresh) (32/64-bit) + +a| +[source] +---- +a715 +---- +| 1 +| 4 +| 23 +| ARM Cortex-A715 (64-bit) + +a| +[source] +---- +a520 +---- +| 1 +| 4 +| 24 +| ARM Cortex-A520 (64-bit) + +a| +[source] +---- +a720 +---- +| 1 +| 4 +| 25 +| ARM Cortex-A720 (64-bit) + +a| +[source] +---- +a520ae +---- +| 1 +| 4 +| 26 +| ARM Cortex-A520AE (64-bit) + +a| +[source] +---- +a720ae +---- +| 1 +| 4 +| 27 +| ARM Cortex-A720AE (64-bit) + +a| +[source] +---- +a725 +---- +| 1 +| 4 +| 28 +| ARM Cortex-A725 (64-bit) + +a| +[source] +---- +a320 +---- +| 1 +| 4 +| 29 +| ARM Cortex-A320 (64-bit) + +a| +[source] +---- +a530 +---- +| 1 +| 4 +| 30 +| ARM Cortex-A530 (64-bit) + +a| +[source] +---- +a730 +---- +| 1 +| 4 +| 31 +| ARM Cortex-A730 (64-bit) + +5+^|*Category: cpu (1), Family: arm_m (5)* + +a| +[source] +---- +any +---- +| 1 +| 5 +| 0 +| Any CPU microarchitecture from the ARM Cortex-M family + +a| +[source] +---- +m3 +---- +| 1 +| 5 +| 1 +| ARM Cortex-M3 + +a| +[source] +---- +m1 +---- +| 1 +| 5 +| 2 +| ARM Cortex-M1 + +a| +[source] +---- +m0 +---- +| 1 +| 5 +| 3 +| ARM Cortex-M0 + +a| +[source] +---- +m4 +---- +| 1 +| 5 +| 4 +| ARM Cortex-M4 + +a| +[source] +---- +m0p +---- +| 1 +| 5 +| 5 +| ARM Cortex-M0+ + +a| +[source] +---- +m7 +---- +| 1 +| 5 +| 6 +| ARM Cortex-M7 + +a| +[source] +---- +m23 +---- +| 1 +| 5 +| 7 +| ARM Cortex-M23 + +a| +[source] +---- +m33 +---- +| 1 +| 5 +| 8 +| ARM Cortex-M33 + +a| +[source] +---- +m35p +---- +| 1 +| 5 +| 9 +| ARM Cortex-M35P + +a| +[source] +---- +m55 +---- +| 1 +| 5 +| 10 +| ARM Cortex-M55 + +a| +[source] +---- +m85 +---- +| 1 +| 5 +| 11 +| ARM Cortex-M85 + +a| +[source] +---- +m52 +---- +| 1 +| 5 +| 12 +| ARM Cortex-M52 + +5+^|*Category: cpu (1), Family: arm_r (6)* + +a| +[source] +---- +any +---- +| 1 +| 6 +| 0 +| Any CPU microarchitecture from the ARM Cortex-R family + +a| +[source] +---- +r4 +---- +| 1 +| 6 +| 1 +| ARM Cortex-R4 (32-bit) + +a| +[source] +---- +r5 +---- +| 1 +| 6 +| 2 +| ARM Cortex-R5 (32-bit) + +a| +[source] +---- +r7 +---- +| 1 +| 6 +| 3 +| ARM Cortex-R7 (32-bit) + +a| +[source] +---- +r8 +---- +| 1 +| 6 +| 4 +| ARM Cortex-R8 (32-bit) + +a| +[source] +---- +r52 +---- +| 1 +| 6 +| 5 +| ARM Cortex-R52 (32-bit) + +a| +[source] +---- +r82 +---- +| 1 +| 6 +| 6 +| ARM Cortex-R82 (64-bit) + +a| +[source] +---- +r52p +---- +| 1 +| 6 +| 7 +| ARM Cortex-R52+ (32-bit) + +5+^|*Category: cpu (1), Family: codasip_lp (7)* + +a| +[source] +---- +any +---- +| 1 +| 7 +| 0 +| Any Codasip low-power CPU + +a| +[source] +---- +l110 +---- +| 1 +| 7 +| 1 +| Codasip L110 + +a| +[source] +---- +l150 +---- +| 1 +| 7 +| 2 +| Codasip L150 + +a| +[source] +---- +l31 +---- +| 1 +| 7 +| 3 +| Codasip L31 + +5+^|*Category: cpu (1), Family: codasip_hp (8)* + +a| +[source] +---- +any +---- +| 1 +| 8 +| 0 +| Any Codasip high-performance CPU + +a| +[source] +---- +l730 +---- +| 1 +| 8 +| 1 +| Codasip L730 + +5+^|*Category: cpu (1), Family: codasip_ap (9)* + +a| +[source] +---- +any +---- +| 1 +| 9 +| 0 +| Any Codasip application CPU + +a| +[source] +---- +a70 +---- +| 1 +| 9 +| 1 +| Codasip A70 + +a| +[source] +---- +a730 +---- +| 1 +| 9 +| 2 +| Codasip A730 + +a| +[source] +---- +x730 +---- +| 1 +| 9 +| 3 +| Codasip X730 + +5+^|*Category: cpu (1), Family: sifive_e2 (10)* + +a| +[source] +---- +any +---- +| 1 +| 10 +| 0 +| Any SiFive Essential 2-series CPU + +5+^|*Category: cpu (1), Family: sifive_e6 (11)* + +a| +[source] +---- +any +---- +| 1 +| 11 +| 0 +| Any SiFive Essential 6-series CPU + +5+^|*Category: cpu (1), Family: sifive_e7 (12)* + +a| +[source] +---- +any +---- +| 1 +| 12 +| 0 +| Any SiFive Essential 7-series CPU + +5+^|*Category: cpu (1), Family: sifive_x200 (13)* + +a| +[source] +---- +any +---- +| 1 +| 13 +| 0 +| Any SiFive Essential X200 Series CPU + +5+^|*Category: cpu (1), Family: sifive_x300 (14)* + +a| +[source] +---- +any +---- +| 1 +| 14 +| 0 +| Any SiFive Essential X300 Series CPU + +5+^|*Category: cpu (1), Family: sifive_xm (15)* + +a| +[source] +---- +any +---- +| 1 +| 15 +| 0 +| Any SiFive Essential XM Series CPU + +5+^|*Category: cpu (1), Family: sifive_p400 (16)* + +a| +[source] +---- +any +---- +| 1 +| 16 +| 0 +| Any SiFive Essential P400 Series CPU + +5+^|*Category: cpu (1), Family: sifive_p500 (17)* + +a| +[source] +---- +any +---- +| 1 +| 17 +| 0 +| Any SiFive Essential P500 Series CPU + +5+^|*Category: cpu (1), Family: sifive_p600 (18)* + +a| +[source] +---- +any +---- +| 1 +| 18 +| 0 +| Any SiFive Essential P600 Series CPU + +5+^|*Category: cpu (1), Family: sifive_p800 (19)* + +a| +[source] +---- +any +---- +| 1 +| 19 +| 0 +| Any SiFive Essential P800 Series CPU + +5+^|*Category: cpu (1), Family: sifive_e6a (20)* + +a| +[source] +---- +any +---- +| 1 +| 20 +| 0 +| Any SiFive Essential E6-A Series CPU + +5+^|*Category: cpu (1), Family: sifive_e7a (21)* + +a| +[source] +---- +any +---- +| 1 +| 21 +| 0 +| Any SiFive Essential E7-A Series CPU + +5+^|*Category: cpu (1), Family: sifive_s7a (22)* + +a| +[source] +---- +any +---- +| 1 +| 22 +| 0 +| Any SiFive Essential S7-A Series CPU + +5+^|*Category: gpu (2), Family: generic (0)* + +a| +[source] +---- +any +---- +| 2 +| 0 +| 0 +| Any GPU + +5+^|*Category: gpu (2), Family: intel (1)* + +a| +[source] +---- +any +---- +| 2 +| 1 +| 0 +| Any Intel GPU + +a| +[source] +---- +bdw +v8_0_0 = bdw +---- +| 2 +| 1 +| 1 +| Broadwell Intel graphics architecture + +a| +[source] +---- +skl +v9_0_9 = skl +---- +| 2 +| 1 +| 2 +| Skylake Intel graphics architecture + +a| +[source] +---- +kbl +v9_1_9 = kbl +---- +| 2 +| 1 +| 3 +| Kaby Lake Intel graphics architecture + +a| +[source] +---- +cfl +v9_2_9 = cfl +---- +| 2 +| 1 +| 4 +| Coffee Lake Intel graphics architecture + +a| +[source] +---- +apl +v9_3_0 = apl +bxt = apl +---- +| 2 +| 1 +| 5 +| Apollo Lake Intel graphics architecture + +a| +[source] +---- +glk +v9_4_0 = glk +---- +| 2 +| 1 +| 6 +| Gemini Lake Intel graphics architecture + +a| +[source] +---- +whl +v9_5_0 = whl +---- +| 2 +| 1 +| 7 +| Whiskey Lake Intel graphics architecture + +a| +[source] +---- +aml +v9_6_0 = aml +---- +| 2 +| 1 +| 8 +| Amber Lake Intel graphics architecture + +a| +[source] +---- +cml +v9_7_0 = cml +---- +| 2 +| 1 +| 9 +| Comet Lake Intel graphics architecture + +a| +[source] +---- +icllp +icl = icllp +v11_0_0 = icllp +---- +| 2 +| 1 +| 10 +| Ice Lake Intel graphics architecture + +a| +[source] +---- +ehl +v11_2_0 = ehl +jsl = ehl +---- +| 2 +| 1 +| 11 +| Elkhart Lake Intel graphics architecture + +a| +[source] +---- +tgllp +tgl = tgllp +v12_0_0 = tgllp +---- +| 2 +| 1 +| 12 +| Tiger Lake Intel graphics architecture + +a| +[source] +---- +rkl +v12_1_0 = rkl +---- +| 2 +| 1 +| 13 +| Rocket Lake Intel graphics architecture + +a| +[source] +---- +adl_s +v12_2_0 = adl_s +rpl_s = adl_s +---- +| 2 +| 1 +| 14 +| Alder Lake S Intel graphics architecture + +a| +[source] +---- +adl_p +v12_3_0 = adl_p +---- +| 2 +| 1 +| 15 +| Alder Lake P Intel graphics architecture + +a| +[source] +---- +adl_n +v12_4_0 = adl_n +---- +| 2 +| 1 +| 16 +| Alder Lake N Intel graphics architecture + +a| +[source] +---- +dg1 +v12_10_0 = dg1 +---- +| 2 +| 1 +| 17 +| DG1 Intel graphics architecture + +a| +[source] +---- +acm_g10 +dg2_g10 = acm_g10 +v12_55_8 = acm_g10 +---- +| 2 +| 1 +| 18 +| Alchemist G10 Intel graphics architecture + +a| +[source] +---- +acm_g11 +dg2_g11 = acm_g11 +v12_56_5 = acm_g11 +---- +| 2 +| 1 +| 19 +| Alchemist G11 Intel graphics architecture + +a| +[source] +---- +acm_g12 +dg2_g12 = acm_g12 +v12_57_0 = acm_g12 +---- +| 2 +| 1 +| 20 +| Alchemist G12 Intel graphics architecture + +a| +[source] +---- +pvc +v12_60_7 = pvc +---- +| 2 +| 1 +| 21 +| Ponte Vecchio Intel graphics architecture + +a| +[source] +---- +pvc_vg +v12_61_7 = pvc_vg +---- +| 2 +| 1 +| 22 +| Ponte Vecchio VG Intel graphics architecture + +a| +[source] +---- +mtl_u +mtl_s = mtl_u +arl_u = mtl_u +arl_s = mtl_u +v12_70_4 = mtl_u +---- +| 2 +| 1 +| 23 +| Meteor Lake U Intel graphics architecture + +a| +[source] +---- +mtl_h +v12_71_4 = mtl_h +---- +| 2 +| 1 +| 24 +| Meteor Lake H Intel graphics architecture + +a| +[source] +---- +arl_h +v12_74_4 = arl_h +---- +| 2 +| 1 +| 25 +| Arrow Lake H Intel graphics architecture + +a| +[source] +---- +bmg_g21 +v20_1_4 = bmg_g21 +---- +| 2 +| 1 +| 26 +| Battlemage G21 Intel graphics architecture + +a| +[source] +---- +lnl_m +v20_4_4 = lnl_m +---- +| 2 +| 1 +| 27 +| Lunar Lake Intel graphics architecture + +a| +[source] +---- +ptl_h +v30_0_4 = ptl_h +---- +| 2 +| 1 +| 28 +| Panther Lake H Intel graphics architecture + +a| +[source] +---- +ptl_u +v30_1_1 = ptl_u +---- +| 2 +| 1 +| 29 +| Panther Lake U Intel graphics architecture + +5+^|*Category: gpu (2), Family: amd (2)* + +a| +[source] +---- +any +---- +| 2 +| 2 +| 0 +| Any AMD GPU + +a| +[source] +---- +gfx700 +gfx701 = gfx700 +gfx702 = gfx700 +gfx703 = gfx700 +gfx704 = gfx700 +gfx705 = gfx700 +---- +| 2 +| 2 +| 1 +| AMD GCN 2.0 microarchitecture + +a| +[source] +---- +gfx801 +gfx802 = gfx801 +---- +| 2 +| 2 +| 2 +| AMD GCN 3.0 microarchitecture + +a| +[source] +---- +gfx803 +---- +| 2 +| 2 +| 3 +| AMD GCN 4.0 microarchitecture + +a| +[source] +---- +gfx805 +gfx810 = gfx805 +---- +| 2 +| 2 +| 4 +| AMD GCN 3.0 microarchitecture + +a| +[source] +---- +gfx900 +gfx902 = gfx900 +gfx904 = gfx900 +---- +| 2 +| 2 +| 5 +| AMD GCN 5.0 microarchitecture + +a| +[source] +---- +gfx906 +---- +| 2 +| 2 +| 6 +| AMD GCN 5.1 microarchitecture + +a| +[source] +---- +gfx908 +---- +| 2 +| 2 +| 7 +| AMD CDNA 1 microarchitecture + +a| +[source] +---- +gfx909 +---- +| 2 +| 2 +| 8 +| AMD GCN 5.0 microarchitecture + +a| +[source] +---- +gfx90a +---- +| 2 +| 2 +| 9 +| AMD CDNA 2 microarchitecture + +a| +[source] +---- +gfx90c +---- +| 2 +| 2 +| 10 +| AMD GCN 5.1 microarchitecture + +a| +[source] +---- +gfx940 +gfx941 = gfx940 +gfx942 = gfx940 +---- +| 2 +| 2 +| 11 +| AMD CDNA 3 microarchitecture + +a| +[source] +---- +gfx1010 +gfx1011 = gfx1010 +gfx1012 = gfx1010 +gfx1013 = gfx1010 +---- +| 2 +| 2 +| 12 +| AMD RDNA 1 microarchitecture + +a| +[source] +---- +gfx1030 +gfx1031 = gfx1030 +gfx1032 = gfx1030 +gfx1033 = gfx1030 +gfx1034 = gfx1030 +gfx1035 = gfx1030 +gfx1036 = gfx1030 +---- +| 2 +| 2 +| 13 +| AMD RDNA 2 microarchitecture + +a| +[source] +---- +gfx1100 +gfx1101 = gfx1100 +gfx1102 = gfx1100 +gfx1103 = gfx1100 +---- +| 2 +| 2 +| 14 +| AMD RDNA 3 microarchitecture + +a| +[source] +---- +gfx1150 +gfx1151 = gfx1150 +---- +| 2 +| 2 +| 15 +| AMD RDNA 3.5 microarchitecture + +a| +[source] +---- +gfx1200 +gfx1201 = gfx1200 +---- +| 2 +| 2 +| 16 +| AMD RDNA 4 microarchitecture + +5+^|*Category: gpu (2), Family: nvidia (3)* + +a| +[source] +---- +any +---- +| 2 +| 3 +| 0 +| Any NVIDIA GPU + +a| +[source] +---- +sm50 +---- +| 2 +| 3 +| 1 +| NVIDIA Maxwell microarchitecture (compute capability 5.0) + +a| +[source] +---- +sm52 +---- +| 2 +| 3 +| 2 +| NVIDIA Maxwell microarchitecture (compute capability 5.2) + +a| +[source] +---- +sm53 +---- +| 2 +| 3 +| 3 +| NVIDIA Maxwell microarchitecture (compute capability 5.3) + +a| +[source] +---- +sm60 +---- +| 2 +| 3 +| 4 +| NVIDIA Pascal microarchitecture (compute capability 6.0) + +a| +[source] +---- +sm61 +---- +| 2 +| 3 +| 5 +| NVIDIA Pascal microarchitecture (compute capability 6.1) + +a| +[source] +---- +sm62 +sm70 = sm62 +---- +| 2 +| 3 +| 6 +| NVIDIA Pascal microarchitecture (compute capability 6.2) + +a| +[source] +---- +sm72 +---- +| 2 +| 3 +| 7 +| NVIDIA Volta microarchitecture (compute capability 7.2) + +a| +[source] +---- +sm75 +---- +| 2 +| 3 +| 8 +| NVIDIA Turing microarchitecture (compute capability 7.5) + +a| +[source] +---- +sm80 +---- +| 2 +| 3 +| 9 +| NVIDIA Ampere microarchitecture (compute capability 8.0) + +a| +[source] +---- +sm86 +---- +| 2 +| 3 +| 10 +| NVIDIA Ampere microarchitecture (compute capability 8.6) + +a| +[source] +---- +sm87 +---- +| 2 +| 3 +| 11 +| NVIDIA Jetson/Drive AGX Orin microarchitecture + +a| +[source] +---- +sm89 +---- +| 2 +| 3 +| 12 +| NVIDIA Ada Lovelace arhitecture + +a| +[source] +---- +sm90 +sm90a = sm90 +---- +| 2 +| 3 +| 13 +| NVIDIA Hopper arhitecture + +5+^|*Category: npu (3), Family: generic (0)* + +a| +[source] +---- +any +---- +| 3 +| 0 +| 0 +| Any NPU + +5+^|*Category: npu (3), Family: intel (1)* + +a| +[source] +---- +any +---- +| 3 +| 1 +| 0 +| Any Intel NPU + +a| +[source] +---- +mtl +---- +| 3 +| 1 +| 1 +| Intel NPU used in Meteor Lake processors + +a| +[source] +---- +lnl +---- +| 3 +| 1 +| 2 +| Intel NPU used in Lunar Lake processors + +5+^|*Category: npu (3), Family: amd_xdna (2)* + +a| +[source] +---- +any +---- +| 3 +| 2 +| 0 +| Any AMD XDNA architecture +|=== diff --git a/sycl/doc/design/spirv-extensions/targets/core.json b/sycl/doc/design/spirv-extensions/targets/core.json new file mode 100644 index 0000000000000..21198259e8a39 --- /dev/null +++ b/sycl/doc/design/spirv-extensions/targets/core.json @@ -0,0 +1,4190 @@ +{ + "version": 0, + "targets": [ + { + "name": "unknown", + "value": 0, + "desc": "Unknown target" + }, + { + "name": "arm", + "value": 1, + "desc": "ARM (32-bit)" + }, + { + "name": "arm32", + "value": 1, + "desc": "ARM (32-bit)" + }, + { + "name": "arm64", + "value": 2, + "desc": "ARM (64-bit)" + }, + { + "name": "aarch64", + "value": 2, + "desc": "ARM (64-bit)" + }, + { + "name": "x86", + "value": 3, + "desc": "x86 (32-bit)" + }, + { + "name": "x86_64", + "value": 4, + "desc": "x86 (64-bit)" + }, + { + "name": "riscv32", + "value": 5, + "desc": "RISC-V (32-bit)" + }, + { + "name": "riscv64", + "value": 6, + "desc": "RISC-V (64-bit)" + }, + { + "name": "nvptx", + "value": 7, + "desc": "NVIDIA PTX (32-bit)" + }, + { + "name": "nvptx64", + "value": 8, + "desc": "NVIDIA PTX (64-bit)" + }, + { + "name": "amdgcn", + "value": 9, + "desc": "AMD GCN" + } + ], + "features": { + "unknown": [ + { + "name": "none", + "value": 0, + "desc": "No features" + } + ], + "arm32": [ + { + "name": "none", + "value": 0, + "desc": "No features" + }, + { + "name": "neon", + "value": 1, + "desc": "Enable NEON instructions" + } + ], + "arm64": [ + { + "name": "none", + "value": 0, + "desc": "No features" + }, + { + "name": "fp8", + "value": 1, + "desc": "Enable FP8 instructions" + }, + { + "name": "fp8dot2", + "value": 2, + "desc": "Enable FP8 2-way dot product instructions" + }, + { + "name": "fp8dot4", + "value": 3, + "desc": "Enable FP8 4-way dot product instructions" + }, + { + "name": "neon", + "value": 4, + "desc": "Enable NEON instructions" + }, + { + "name": "sve", + "value": 5, + "desc": "Enable SVE instructions" + } + ], + "x86": [ + { + "name": "none", + "value": 0, + "desc": "No features" + }, + { + "name": "fma", + "value": 1, + "desc": "Enable fused three-operand multiply-add" + }, + { + "name": "fma4", + "value": 2, + "desc": "Enable fused four-operand multiply-add" + }, + { + "name": "mmx", + "value": 3, + "desc": "Enable MMX instructions" + }, + { + "name": "sse", + "value": 4, + "desc": "Enable SSE instructions" + }, + { + "name": "sse2", + "value": 5, + "desc": "Enable SSE2 instructions" + }, + { + "name": "sse3", + "value": 6, + "desc": "Enable SSE3 instructions" + }, + { + "name": "sse4.1", + "value": 7, + "desc": "Enable SSE4.1 instructions" + }, + { + "name": "sse4.2", + "value": 8, + "desc": "Enable SSE4.2 instructions" + }, + { + "name": "sse4a", + "value": 9, + "desc": "Enable SSE4a instructions" + }, + { + "name": "avx", + "value": 10, + "desc": "Enable AVX instructions" + }, + { + "name": "avx2", + "value": 11, + "desc": "Enable AVX2 instructions" + }, + { + "name": "avx512f", + "value": 12, + "desc": "Enable AVX512 instructions" + } + ], + "x86_64": [ + { + "name": "none", + "value": 0, + "desc": "No features" + }, + { + "name": "fma", + "value": 1, + "desc": "Enable fused three-operand multiply-add" + }, + { + "name": "fma4", + "value": 2, + "desc": "Enable fused four-operand multiply-add" + }, + { + "name": "mmx", + "value": 3, + "desc": "Enable MMX instructions" + }, + { + "name": "sse", + "value": 4, + "desc": "Enable SSE instructions" + }, + { + "name": "sse2", + "value": 5, + "desc": "Enable SSE2 instructions" + }, + { + "name": "sse3", + "value": 6, + "desc": "Enable SSE3 instructions" + }, + { + "name": "sse4.1", + "value": 7, + "desc": "Enable SSE4.1 instructions" + }, + { + "name": "sse4.2", + "value": 8, + "desc": "Enable SSE4.2 instructions" + }, + { + "name": "sse4a", + "value": 9, + "desc": "Enable SSE4a instructions" + }, + { + "name": "avx", + "value": 10, + "desc": "Enable AVX instructions" + }, + { + "name": "avx2", + "value": 11, + "desc": "Enable AVX2 instructions" + }, + { + "name": "avx512f", + "value": 12, + "desc": "Enable AVX512 instructions" + } + ], + "riscv32": [ + { + "name": "32bit", + "value": 0, + "desc": "Implements RV32." + }, + { + "name": "64bit", + "value": 1, + "desc": "Implements RV64." + }, + { + "name": "a", + "value": 2, + "desc": "'A' (Atomic Instructions)." + }, + { + "name": "auipc-addi-fusion", + "value": 3, + "desc": "Enable AUIPC+ADDI macrofusion." + }, + { + "name": "b", + "value": 4, + "desc": "'B' (the collection of the Zba, Zbb, Zbs extensions)." + }, + { + "name": "c", + "value": 5, + "desc": "'C' (Compressed Instructions)." + }, + { + "name": "conditional-cmv-fusion", + "value": 6, + "desc": "Enable branch+c.mv fusion." + }, + { + "name": "d", + "value": 7, + "desc": "'D' (Double-Precision Floating-Point)." + }, + { + "name": "dlen-factor-2", + "value": 8, + "desc": "Vector unit DLEN(data path width) is half of VLEN." + }, + { + "name": "e", + "value": 9, + "desc": "Implements RV{32,64}E (provides 16 rather than 32 GPRs)." + }, + { + "name": "experimental", + "value": 10, + "desc": "Experimental intrinsics." + }, + { + "name": "experimental-rva23s64", + "value": 11, + "desc": "RISC-V experimental-rva23s64 profile." + }, + { + "name": "experimental-rva23u64", + "value": 12, + "desc": "RISC-V experimental-rva23u64 profile." + }, + { + "name": "experimental-rvb23s64", + "value": 13, + "desc": "RISC-V experimental-rvb23s64 profile." + }, + { + "name": "experimental-rvb23u64", + "value": 14, + "desc": "RISC-V experimental-rvb23u64 profile." + }, + { + "name": "experimental-rvm23u32", + "value": 15, + "desc": "RISC-V experimental-rvm23u32 profile." + }, + { + "name": "experimental-smmpm", + "value": 16, + "desc": "'Smmpm' (Machine-level Pointer Masking for M-mode)." + }, + { + "name": "experimental-smnpm", + "value": 17, + "desc": "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)." + }, + { + "name": "experimental-ssnpm", + "value": 18, + "desc": "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)." + }, + { + "name": "experimental-sspm", + "value": 19, + "desc": "'Sspm' (Indicates Supervisor-mode Pointer Masking)." + }, + { + "name": "experimental-ssqosid", + "value": 20, + "desc": "'Ssqosid' (Quality-of-Service (QoS) Identifiers)." + }, + { + "name": "experimental-supm", + "value": 21, + "desc": "'Supm' (Indicates User-mode Pointer Masking)." + }, + { + "name": "experimental-zacas", + "value": 22, + "desc": "'Zacas' (Atomic Compare-And-Swap Instructions)." + }, + { + "name": "experimental-zalasr", + "value": 23, + "desc": "'Zalasr' (Load-Acquire and Store-Release Instructions)." + }, + { + "name": "experimental-zicfilp", + "value": 24, + "desc": "'Zicfilp' (Landing pad)." + }, + { + "name": "experimental-zicfiss", + "value": 25, + "desc": "'Zicfiss' (Shadow stack)." + }, + { + "name": "f", + "value": 26, + "desc": "'F' (Single-Precision Floating-Point)." + }, + { + "name": "forced-atomics", + "value": 27, + "desc": "Assume that lock-free native-width atomics are available." + }, + { + "name": "forced-sw-shadow-stack", + "value": 28, + "desc": "Implement shadow stack with software.." + }, + { + "name": "h", + "value": 29, + "desc": "'H' (Hypervisor)." + }, + { + "name": "i", + "value": 30, + "desc": "'I' (Base Integer Instruction Set)." + }, + { + "name": "ld-add-fusion", + "value": 31, + "desc": "Enable LD+ADD macrofusion." + }, + { + "name": "lui-addi-fusion", + "value": 32, + "desc": "Enable LUI+ADDI macro fusion." + }, + { + "name": "m", + "value": 33, + "desc": "'M' (Integer Multiplication and Division)." + }, + { + "name": "no-default-unroll", + "value": 34, + "desc": "Disable default unroll preference.." + }, + { + "name": "no-rvc-hints", + "value": 35, + "desc": "Disable RVC Hint Instructions.." + }, + { + "name": "no-sink-splat-operands", + "value": 36, + "desc": "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions." + }, + { + "name": "no-trailing-seq-cst-fence", + "value": 37, + "desc": "Disable trailing fence for seq-cst store.." + }, + { + "name": "optimized-zero-stride-load", + "value": 38, + "desc": "Optimized (perform fewer memory operations)zero-stride vector load." + }, + { + "name": "predictable-select-expensive", + "value": 39, + "desc": "Prefer likely predicted branches over selects." + }, + { + "name": "prefer-w-inst", + "value": 40, + "desc": "Prefer instructions with W suffix." + }, + { + "name": "relax", + "value": 41, + "desc": "Enable Linker relaxation.." + }, + { + "name": "reserve-x1", + "value": 42, + "desc": "Reserve X1." + }, + { + "name": "reserve-x10", + "value": 43, + "desc": "Reserve X10." + }, + { + "name": "reserve-x11", + "value": 44, + "desc": "Reserve X11." + }, + { + "name": "reserve-x12", + "value": 45, + "desc": "Reserve X12." + }, + { + "name": "reserve-x13", + "value": 46, + "desc": "Reserve X13." + }, + { + "name": "reserve-x14", + "value": 47, + "desc": "Reserve X14." + }, + { + "name": "reserve-x15", + "value": 48, + "desc": "Reserve X15." + }, + { + "name": "reserve-x16", + "value": 49, + "desc": "Reserve X16." + }, + { + "name": "reserve-x17", + "value": 50, + "desc": "Reserve X17." + }, + { + "name": "reserve-x18", + "value": 51, + "desc": "Reserve X18." + }, + { + "name": "reserve-x19", + "value": 52, + "desc": "Reserve X19." + }, + { + "name": "reserve-x2", + "value": 53, + "desc": "Reserve X2." + }, + { + "name": "reserve-x20", + "value": 54, + "desc": "Reserve X20." + }, + { + "name": "reserve-x21", + "value": 55, + "desc": "Reserve X21." + }, + { + "name": "reserve-x22", + "value": 56, + "desc": "Reserve X22." + }, + { + "name": "reserve-x23", + "value": 57, + "desc": "Reserve X23." + }, + { + "name": "reserve-x24", + "value": 58, + "desc": "Reserve X24." + }, + { + "name": "reserve-x25", + "value": 59, + "desc": "Reserve X25." + }, + { + "name": "reserve-x26", + "value": 60, + "desc": "Reserve X26." + }, + { + "name": "reserve-x27", + "value": 61, + "desc": "Reserve X27." + }, + { + "name": "reserve-x28", + "value": 62, + "desc": "Reserve X28." + }, + { + "name": "reserve-x29", + "value": 63, + "desc": "Reserve X29." + }, + { + "name": "reserve-x3", + "value": 64, + "desc": "Reserve X3." + }, + { + "name": "reserve-x30", + "value": 65, + "desc": "Reserve X30." + }, + { + "name": "reserve-x31", + "value": 66, + "desc": "Reserve X31." + }, + { + "name": "reserve-x4", + "value": 67, + "desc": "Reserve X4." + }, + { + "name": "reserve-x5", + "value": 68, + "desc": "Reserve X5." + }, + { + "name": "reserve-x6", + "value": 69, + "desc": "Reserve X6." + }, + { + "name": "reserve-x7", + "value": 70, + "desc": "Reserve X7." + }, + { + "name": "reserve-x8", + "value": 71, + "desc": "Reserve X8." + }, + { + "name": "reserve-x9", + "value": 72, + "desc": "Reserve X9." + }, + { + "name": "rva20s64", + "value": 73, + "desc": "RISC-V rva20s64 profile." + }, + { + "name": "rva20u64", + "value": 74, + "desc": "RISC-V rva20u64 profile." + }, + { + "name": "rva22s64", + "value": 75, + "desc": "RISC-V rva22s64 profile." + }, + { + "name": "rva22u64", + "value": 76, + "desc": "RISC-V rva22u64 profile." + }, + { + "name": "rvi20u32", + "value": 77, + "desc": "RISC-V rvi20u32 profile." + }, + { + "name": "rvi20u64", + "value": 78, + "desc": "RISC-V rvi20u64 profile." + }, + { + "name": "save-restore", + "value": 79, + "desc": "Enable save/restore.." + }, + { + "name": "shcounterenw", + "value": 80, + "desc": "'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)." + }, + { + "name": "shgatpa", + "value": 81, + "desc": "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)." + }, + { + "name": "shifted-zextw-fusion", + "value": 82, + "desc": "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension." + }, + { + "name": "short-forward-branch-opt", + "value": 83, + "desc": "Enable short forward branch optimization." + }, + { + "name": "shtvala", + "value": 84, + "desc": "'Shtvala' (htval provides all needed values)." + }, + { + "name": "shvsatpa", + "value": 85, + "desc": "'Svsatpa' (vsatp supports all modes supported by satp)." + }, + { + "name": "shvstvala", + "value": 86, + "desc": "'Shvstvala' (vstval provides all needed values)." + }, + { + "name": "shvstvecd", + "value": 87, + "desc": "'Shvstvecd' (vstvec supports Direct mode)." + }, + { + "name": "sifive7", + "value": 88, + "desc": "SiFive 7-Series processors." + }, + { + "name": "smaia", + "value": 89, + "desc": "'Smaia' (Advanced Interrupt Architecture Machine Level)." + }, + { + "name": "smcdeleg", + "value": 90, + "desc": "'Smcdeleg' (Counter Delegation Machine Level)." + }, + { + "name": "smcsrind", + "value": 91, + "desc": "'Smcsrind' (Indirect CSR Access Machine Level)." + }, + { + "name": "smepmp", + "value": 92, + "desc": "'Smepmp' (Enhanced Physical Memory Protection)." + }, + { + "name": "smstateen", + "value": 93, + "desc": "'Smstateen' (Machine-mode view of the state-enable extension)." + }, + { + "name": "ssaia", + "value": 94, + "desc": "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)." + }, + { + "name": "ssccfg", + "value": 95, + "desc": "'Ssccfg' (Counter Configuration Supervisor Level)." + }, + { + "name": "ssccptr", + "value": 96, + "desc": "'Ssccptr' (Main memory supports page table reads)." + }, + { + "name": "sscofpmf", + "value": 97, + "desc": "'Sscofpmf' (Count Overflow and Mode-Based Filtering)." + }, + { + "name": "sscounterenw", + "value": 98, + "desc": "'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)." + }, + { + "name": "sscsrind", + "value": 99, + "desc": "'Sscsrind' (Indirect CSR Access Supervisor Level)." + }, + { + "name": "ssstateen", + "value": 100, + "desc": "'Ssstateen' (Supervisor-mode view of the state-enable extension)." + }, + { + "name": "ssstrict", + "value": 101, + "desc": "'Ssstrict' (No non-conforming extensions are present)." + }, + { + "name": "sstc", + "value": 102, + "desc": "'Sstc' (Supervisor-mode timer interrupts)." + }, + { + "name": "sstvala", + "value": 103, + "desc": "'Sstvala' (stval provides all needed values)." + }, + { + "name": "sstvecd", + "value": 104, + "desc": "'Sstvecd' (stvec supports Direct mode)." + }, + { + "name": "ssu64xl", + "value": 105, + "desc": "'Ssu64xl' (UXLEN=64 supported)." + }, + { + "name": "svade", + "value": 106, + "desc": "'Svade' (Raise exceptions on improper A/D bits)." + }, + { + "name": "svadu", + "value": 107, + "desc": "'Svadu' (Hardware A/D updates)." + }, + { + "name": "svbare", + "value": 108, + "desc": "'Svbare' $(satp mode Bare supported)." + }, + { + "name": "svinval", + "value": 109, + "desc": "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)." + }, + { + "name": "svnapot", + "value": 110, + "desc": "'Svnapot' (NAPOT Translation Contiguity)." + }, + { + "name": "svpbmt", + "value": 111, + "desc": "'Svpbmt' (Page-Based Memory Types)." + }, + { + "name": "tagged-globals", + "value": 112, + "desc": "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits." + }, + { + "name": "unaligned-scalar-mem", + "value": 113, + "desc": "Has reasonably performant unaligned scalar loads and stores." + }, + { + "name": "unaligned-vector-mem", + "value": 114, + "desc": "Has reasonably performant unaligned vector loads and stores." + }, + { + "name": "use-postra-scheduler", + "value": 115, + "desc": "Schedule again after register allocation." + }, + { + "name": "v", + "value": 116, + "desc": "'V' (Vector Extension for Application Processors)." + }, + { + "name": "ventana-veyron", + "value": 117, + "desc": "Ventana Veyron-Series processors." + }, + { + "name": "xcvalu", + "value": 118, + "desc": "'XCValu' (CORE-V ALU Operations)." + }, + { + "name": "xcvbi", + "value": 119, + "desc": "'XCVbi' (CORE-V Immediate Branching)." + }, + { + "name": "xcvbitmanip", + "value": 120, + "desc": "'XCVbitmanip' (CORE-V Bit Manipulation)." + }, + { + "name": "xcvelw", + "value": 121, + "desc": "'XCVelw' (CORE-V Event Load Word)." + }, + { + "name": "xcvmac", + "value": 122, + "desc": "'XCVmac' (CORE-V Multiply-Accumulate)." + }, + { + "name": "xcvmem", + "value": 123, + "desc": "'XCVmem' (CORE-V Post-incrementing Load & Store)." + }, + { + "name": "xcvsimd", + "value": 124, + "desc": "'XCVsimd' (CORE-V SIMD ALU)." + }, + { + "name": "xsfcease", + "value": 125, + "desc": "'XSfcease' (SiFive sf.cease Instruction)." + }, + { + "name": "xsfvcp", + "value": 126, + "desc": "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)." + }, + { + "name": "xsfvfnrclipxfqf", + "value": 127, + "desc": "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)." + }, + { + "name": "xsfvfwmaccqqq", + "value": 128, + "desc": "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))." + }, + { + "name": "xsfvqmaccdod", + "value": 129, + "desc": "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))." + }, + { + "name": "xsfvqmaccqoq", + "value": 130, + "desc": "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))." + }, + { + "name": "xsifivecdiscarddlone", + "value": 131, + "desc": "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)." + }, + { + "name": "xsifivecflushdlone", + "value": 132, + "desc": "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)." + }, + { + "name": "xtheadba", + "value": 133, + "desc": "'XTHeadBa' (T-Head address calculation instructions)." + }, + { + "name": "xtheadbb", + "value": 134, + "desc": "'XTHeadBb' (T-Head basic bit-manipulation instructions)." + }, + { + "name": "xtheadbs", + "value": 135, + "desc": "'XTHeadBs' (T-Head single-bit instructions)." + }, + { + "name": "xtheadcmo", + "value": 136, + "desc": "'XTHeadCmo' (T-Head cache management instructions)." + }, + { + "name": "xtheadcondmov", + "value": 137, + "desc": "'XTHeadCondMov' (T-Head conditional move instructions)." + }, + { + "name": "xtheadfmemidx", + "value": 138, + "desc": "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)." + }, + { + "name": "xtheadmac", + "value": 139, + "desc": "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)." + }, + { + "name": "xtheadmemidx", + "value": 140, + "desc": "'XTHeadMemIdx' (T-Head Indexed Memory Operations)." + }, + { + "name": "xtheadmempair", + "value": 141, + "desc": "'XTHeadMemPair' (T-Head two-GPR Memory Operations)." + }, + { + "name": "xtheadsync", + "value": 142, + "desc": "'XTHeadSync' (T-Head multicore synchronization instructions)." + }, + { + "name": "xtheadvdot", + "value": 143, + "desc": "'XTHeadVdot' (T-Head Vector Extensions for Dot)." + }, + { + "name": "xventanacondops", + "value": 144, + "desc": "'XVentanaCondOps' (Ventana Conditional Ops)." + }, + { + "name": "xwchc", + "value": 145, + "desc": "'Xwchc' (WCH/QingKe additional compressed opcodes)." + }, + { + "name": "za128rs", + "value": 146, + "desc": "'Za128rs' (Reservation Set Size of at Most 128 Bytes)." + }, + { + "name": "za64rs", + "value": 147, + "desc": "'Za64rs' (Reservation Set Size of at Most 64 Bytes)." + }, + { + "name": "zaamo", + "value": 148, + "desc": "'Zaamo' (Atomic Memory Operations)." + }, + { + "name": "zabha", + "value": 149, + "desc": "'Zabha' (Byte and Halfword Atomic Memory Operations)." + }, + { + "name": "zalrsc", + "value": 150, + "desc": "'Zalrsc' (Load-Reserved/Store-Conditional)." + }, + { + "name": "zama16b", + "value": 151, + "desc": "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)." + }, + { + "name": "zawrs", + "value": 152, + "desc": "'Zawrs' (Wait on Reservation Set)." + }, + { + "name": "zba", + "value": 153, + "desc": "'Zba' (Address Generation Instructions)." + }, + { + "name": "zbb", + "value": 154, + "desc": "'Zbb' (Basic Bit-Manipulation)." + }, + { + "name": "zbc", + "value": 155, + "desc": "'Zbc' (Carry-Less Multiplication)." + }, + { + "name": "zbkb", + "value": 156, + "desc": "'Zbkb' (Bitmanip instructions for Cryptography)." + }, + { + "name": "zbkc", + "value": 157, + "desc": "'Zbkc' (Carry-less multiply instructions for Cryptography)." + }, + { + "name": "zbkx", + "value": 158, + "desc": "'Zbkx' (Crossbar permutation instructions)." + }, + { + "name": "zbs", + "value": 159, + "desc": "'Zbs' (Single-Bit Instructions)." + }, + { + "name": "zca", + "value": 160, + "desc": "'Zca' (part of the C extension, excluding compressed floating point loads/stores)." + }, + { + "name": "zcb", + "value": 161, + "desc": "'Zcb' (Compressed basic bit manipulation instructions)." + }, + { + "name": "zcd", + "value": 162, + "desc": "'Zcd' (Compressed Double-Precision Floating-Point Instructions)." + }, + { + "name": "zce", + "value": 163, + "desc": "'Zce' (Compressed extensions for microcontrollers)." + }, + { + "name": "zcf", + "value": 164, + "desc": "'Zcf' (Compressed Single-Precision Floating-Point Instructions)." + }, + { + "name": "zcmop", + "value": 165, + "desc": "'Zcmop' (Compressed May-Be-Operations)." + }, + { + "name": "zcmp", + "value": 166, + "desc": "'Zcmp' (sequenced instructions for code-size reduction)." + }, + { + "name": "zcmt", + "value": 167, + "desc": "'Zcmt' (table jump instructions for code-size reduction)." + }, + { + "name": "zdinx", + "value": 168, + "desc": "'Zdinx' (Double in Integer)." + }, + { + "name": "zexth-fusion", + "value": 169, + "desc": "Enable SLLI+SRLI to be fused to zero extension of halfword." + }, + { + "name": "zextw-fusion", + "value": 170, + "desc": "Enable SLLI+SRLI to be fused to zero extension of word." + }, + { + "name": "zfa", + "value": 171, + "desc": "'Zfa' (Additional Floating-Point)." + }, + { + "name": "zfbfmin", + "value": 172, + "desc": "'Zfbfmin' (Scalar BF16 Converts)." + }, + { + "name": "zfh", + "value": 173, + "desc": "'Zfh' (Half-Precision Floating-Point)." + }, + { + "name": "zfhmin", + "value": 174, + "desc": "'Zfhmin' (Half-Precision Floating-Point Minimal)." + }, + { + "name": "zfinx", + "value": 175, + "desc": "'Zfinx' (Float in Integer)." + }, + { + "name": "zhinx", + "value": 176, + "desc": "'Zhinx' (Half Float in Integer)." + }, + { + "name": "zhinxmin", + "value": 177, + "desc": "'Zhinxmin' (Half Float in Integer Minimal)." + }, + { + "name": "zic64b", + "value": 178, + "desc": "'Zic64b' (Cache Block Size Is 64 Bytes)." + }, + { + "name": "zicbom", + "value": 179, + "desc": "'Zicbom' (Cache-Block Management Instructions)." + }, + { + "name": "zicbop", + "value": 180, + "desc": "'Zicbop' (Cache-Block Prefetch Instructions)." + }, + { + "name": "zicboz", + "value": 181, + "desc": "'Zicboz' (Cache-Block Zero Instructions)." + }, + { + "name": "ziccamoa", + "value": 182, + "desc": "'Ziccamoa' (Main Memory Supports All Atomics in A)." + }, + { + "name": "ziccif", + "value": 183, + "desc": "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)." + }, + { + "name": "zicclsm", + "value": 184, + "desc": "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)." + }, + { + "name": "ziccrse", + "value": 185, + "desc": "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)." + }, + { + "name": "zicntr", + "value": 186, + "desc": "'Zicntr' (Base Counters and Timers)." + }, + { + "name": "zicond", + "value": 187, + "desc": "'Zicond' (Integer Conditional Operations)." + }, + { + "name": "zicsr", + "value": 188, + "desc": "'zicsr' (CSRs)." + }, + { + "name": "zifencei", + "value": 189, + "desc": "'Zifencei' (fence.i)." + }, + { + "name": "zihintntl", + "value": 190, + "desc": "'Zihintntl' (Non-Temporal Locality Hints)." + }, + { + "name": "zihintpause", + "value": 191, + "desc": "'Zihintpause' (Pause Hint)." + }, + { + "name": "zihpm", + "value": 192, + "desc": "'Zihpm' (Hardware Performance Counters)." + }, + { + "name": "zimop", + "value": 193, + "desc": "'Zimop' (May-Be-Operations)." + }, + { + "name": "zk", + "value": 194, + "desc": "'Zk' (Standard scalar cryptography extension)." + }, + { + "name": "zkn", + "value": 195, + "desc": "'Zkn' (NIST Algorithm Suite)." + }, + { + "name": "zknd", + "value": 196, + "desc": "'Zknd' (NIST Suite: AES Decryption)." + }, + { + "name": "zkne", + "value": 197, + "desc": "'Zkne' (NIST Suite: AES Encryption)." + }, + { + "name": "zknh", + "value": 198, + "desc": "'Zknh' (NIST Suite: Hash Function Instructions)." + }, + { + "name": "zkr", + "value": 199, + "desc": "'Zkr' (Entropy Source Extension)." + }, + { + "name": "zks", + "value": 200, + "desc": "'Zks' (ShangMi Algorithm Suite)." + }, + { + "name": "zksed", + "value": 201, + "desc": "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)." + }, + { + "name": "zksh", + "value": 202, + "desc": "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)." + }, + { + "name": "zkt", + "value": 203, + "desc": "'Zkt' (Data Independent Execution Latency)." + }, + { + "name": "zmmul", + "value": 204, + "desc": "'Zmmul' (Integer Multiplication)." + }, + { + "name": "ztso", + "value": 205, + "desc": "'Ztso' (Memory Model" + }, + { + "name": "zvbb", + "value": 206, + "desc": "'Zvbb' (Vector basic bit-manipulation instructions)." + }, + { + "name": "zvbc", + "value": 207, + "desc": "'Zvbc' (Vector Carryless Multiplication)." + }, + { + "name": "zve32f", + "value": 208, + "desc": "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)." + }, + { + "name": "zve32x", + "value": 209, + "desc": "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)." + }, + { + "name": "zve64d", + "value": 210, + "desc": "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)." + }, + { + "name": "zve64f", + "value": 211, + "desc": "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)." + }, + { + "name": "zve64x", + "value": 212, + "desc": "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)." + }, + { + "name": "zvfbfmin", + "value": 213, + "desc": "'Zvbfmin' (Vector BF16 Converts)." + }, + { + "name": "zvfbfwma", + "value": 214, + "desc": "'Zvfbfwma' (Vector BF16 widening mul-add)." + }, + { + "name": "zvfh", + "value": 215, + "desc": "'Zvfh' (Vector Half-Precision Floating-Point)." + }, + { + "name": "zvfhmin", + "value": 216, + "desc": "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)." + }, + { + "name": "zvkb", + "value": 217, + "desc": "'Zvkb' (Vector Bit-manipulation used in Cryptography)." + }, + { + "name": "zvkg", + "value": 218, + "desc": "'Zvkg' (Vector GCM instructions for Cryptography)." + }, + { + "name": "zvkn", + "value": 219, + "desc": "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')." + }, + { + "name": "zvknc", + "value": 220, + "desc": "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')." + }, + { + "name": "zvkned", + "value": 221, + "desc": "'Zvkned' (Vector AES Encryption & Decryption (Single Round))." + }, + { + "name": "zvkng", + "value": 222, + "desc": "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')." + }, + { + "name": "zvknha", + "value": 223, + "desc": "'Zvknha' (Vector SHA-2 (SHA-256 only))." + }, + { + "name": "zvknhb", + "value": 224, + "desc": "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))." + }, + { + "name": "zvks", + "value": 225, + "desc": "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')." + }, + { + "name": "zvksc", + "value": 226, + "desc": "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')." + }, + { + "name": "zvksed", + "value": 227, + "desc": "'Zvksed' (SM4 Block Cipher Instructions)." + }, + { + "name": "zvksg", + "value": 228, + "desc": "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')." + }, + { + "name": "zvksh", + "value": 229, + "desc": "'Zvksh' (SM3 Hash Function Instructions)." + }, + { + "name": "zvkt", + "value": 230, + "desc": "'Zvkt' (Vector Data-Independent Execution Latency)." + }, + { + "name": "zvl1024b", + "value": 231, + "desc": "'Zvl' (Minimum Vector Length) 1024." + }, + { + "name": "zvl128b", + "value": 232, + "desc": "'Zvl' (Minimum Vector Length) 128." + }, + { + "name": "zvl16384b", + "value": 233, + "desc": "'Zvl' (Minimum Vector Length) 16384." + }, + { + "name": "zvl2048b", + "value": 234, + "desc": "'Zvl' (Minimum Vector Length) 2048." + }, + { + "name": "zvl256b", + "value": 235, + "desc": "'Zvl' (Minimum Vector Length) 256." + }, + { + "name": "zvl32768b", + "value": 236, + "desc": "'Zvl' (Minimum Vector Length) 32768." + }, + { + "name": "zvl32b", + "value": 237, + "desc": "'Zvl' (Minimum Vector Length) 32." + }, + { + "name": "zvl4096b", + "value": 238, + "desc": "'Zvl' (Minimum Vector Length) 4096." + }, + { + "name": "zvl512b", + "value": 239, + "desc": "'Zvl' (Minimum Vector Length) 512." + }, + { + "name": "zvl64b", + "value": 240, + "desc": "'Zvl' (Minimum Vector Length) 64." + }, + { + "name": "zvl65536b", + "value": 241, + "desc": "'Zvl' (Minimum Vector Length) 65536." + }, + { + "name": "zvl8192b", + "value": 242, + "desc": "'Zvl' (Minimum Vector Length) 8192." + } + ], + "riscv64": [ + { + "name": "32bit", + "value": 0, + "desc": "Implements RV32." + }, + { + "name": "64bit", + "value": 1, + "desc": "Implements RV64." + }, + { + "name": "a", + "value": 2, + "desc": "'A' (Atomic Instructions)." + }, + { + "name": "auipc-addi-fusion", + "value": 3, + "desc": "Enable AUIPC+ADDI macrofusion." + }, + { + "name": "b", + "value": 4, + "desc": "'B' (the collection of the Zba, Zbb, Zbs extensions)." + }, + { + "name": "c", + "value": 5, + "desc": "'C' (Compressed Instructions)." + }, + { + "name": "conditional-cmv-fusion", + "value": 6, + "desc": "Enable branch+c.mv fusion." + }, + { + "name": "d", + "value": 7, + "desc": "'D' (Double-Precision Floating-Point)." + }, + { + "name": "dlen-factor-2", + "value": 8, + "desc": "Vector unit DLEN(data path width) is half of VLEN." + }, + { + "name": "e", + "value": 9, + "desc": "Implements RV{32,64}E (provides 16 rather than 32 GPRs)." + }, + { + "name": "experimental", + "value": 10, + "desc": "Experimental intrinsics." + }, + { + "name": "experimental-rva23s64", + "value": 11, + "desc": "RISC-V experimental-rva23s64 profile." + }, + { + "name": "experimental-rva23u64", + "value": 12, + "desc": "RISC-V experimental-rva23u64 profile." + }, + { + "name": "experimental-rvb23s64", + "value": 13, + "desc": "RISC-V experimental-rvb23s64 profile." + }, + { + "name": "experimental-rvb23u64", + "value": 14, + "desc": "RISC-V experimental-rvb23u64 profile." + }, + { + "name": "experimental-rvm23u32", + "value": 15, + "desc": "RISC-V experimental-rvm23u32 profile." + }, + { + "name": "experimental-smmpm", + "value": 16, + "desc": "'Smmpm' (Machine-level Pointer Masking for M-mode)." + }, + { + "name": "experimental-smnpm", + "value": 17, + "desc": "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)." + }, + { + "name": "experimental-ssnpm", + "value": 18, + "desc": "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)." + }, + { + "name": "experimental-sspm", + "value": 19, + "desc": "'Sspm' (Indicates Supervisor-mode Pointer Masking)." + }, + { + "name": "experimental-ssqosid", + "value": 20, + "desc": "'Ssqosid' (Quality-of-Service (QoS) Identifiers)." + }, + { + "name": "experimental-supm", + "value": 21, + "desc": "'Supm' (Indicates User-mode Pointer Masking)." + }, + { + "name": "experimental-zacas", + "value": 22, + "desc": "'Zacas' (Atomic Compare-And-Swap Instructions)." + }, + { + "name": "experimental-zalasr", + "value": 23, + "desc": "'Zalasr' (Load-Acquire and Store-Release Instructions)." + }, + { + "name": "experimental-zicfilp", + "value": 24, + "desc": "'Zicfilp' (Landing pad)." + }, + { + "name": "experimental-zicfiss", + "value": 25, + "desc": "'Zicfiss' (Shadow stack)." + }, + { + "name": "f", + "value": 26, + "desc": "'F' (Single-Precision Floating-Point)." + }, + { + "name": "forced-atomics", + "value": 27, + "desc": "Assume that lock-free native-width atomics are available." + }, + { + "name": "forced-sw-shadow-stack", + "value": 28, + "desc": "Implement shadow stack with software.." + }, + { + "name": "h", + "value": 29, + "desc": "'H' (Hypervisor)." + }, + { + "name": "i", + "value": 30, + "desc": "'I' (Base Integer Instruction Set)." + }, + { + "name": "ld-add-fusion", + "value": 31, + "desc": "Enable LD+ADD macrofusion." + }, + { + "name": "lui-addi-fusion", + "value": 32, + "desc": "Enable LUI+ADDI macro fusion." + }, + { + "name": "m", + "value": 33, + "desc": "'M' (Integer Multiplication and Division)." + }, + { + "name": "no-default-unroll", + "value": 34, + "desc": "Disable default unroll preference.." + }, + { + "name": "no-rvc-hints", + "value": 35, + "desc": "Disable RVC Hint Instructions.." + }, + { + "name": "no-sink-splat-operands", + "value": 36, + "desc": "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions." + }, + { + "name": "no-trailing-seq-cst-fence", + "value": 37, + "desc": "Disable trailing fence for seq-cst store.." + }, + { + "name": "optimized-zero-stride-load", + "value": 38, + "desc": "Optimized (perform fewer memory operations)zero-stride vector load." + }, + { + "name": "predictable-select-expensive", + "value": 39, + "desc": "Prefer likely predicted branches over selects." + }, + { + "name": "prefer-w-inst", + "value": 40, + "desc": "Prefer instructions with W suffix." + }, + { + "name": "relax", + "value": 41, + "desc": "Enable Linker relaxation.." + }, + { + "name": "reserve-x1", + "value": 42, + "desc": "Reserve X1." + }, + { + "name": "reserve-x10", + "value": 43, + "desc": "Reserve X10." + }, + { + "name": "reserve-x11", + "value": 44, + "desc": "Reserve X11." + }, + { + "name": "reserve-x12", + "value": 45, + "desc": "Reserve X12." + }, + { + "name": "reserve-x13", + "value": 46, + "desc": "Reserve X13." + }, + { + "name": "reserve-x14", + "value": 47, + "desc": "Reserve X14." + }, + { + "name": "reserve-x15", + "value": 48, + "desc": "Reserve X15." + }, + { + "name": "reserve-x16", + "value": 49, + "desc": "Reserve X16." + }, + { + "name": "reserve-x17", + "value": 50, + "desc": "Reserve X17." + }, + { + "name": "reserve-x18", + "value": 51, + "desc": "Reserve X18." + }, + { + "name": "reserve-x19", + "value": 52, + "desc": "Reserve X19." + }, + { + "name": "reserve-x2", + "value": 53, + "desc": "Reserve X2." + }, + { + "name": "reserve-x20", + "value": 54, + "desc": "Reserve X20." + }, + { + "name": "reserve-x21", + "value": 55, + "desc": "Reserve X21." + }, + { + "name": "reserve-x22", + "value": 56, + "desc": "Reserve X22." + }, + { + "name": "reserve-x23", + "value": 57, + "desc": "Reserve X23." + }, + { + "name": "reserve-x24", + "value": 58, + "desc": "Reserve X24." + }, + { + "name": "reserve-x25", + "value": 59, + "desc": "Reserve X25." + }, + { + "name": "reserve-x26", + "value": 60, + "desc": "Reserve X26." + }, + { + "name": "reserve-x27", + "value": 61, + "desc": "Reserve X27." + }, + { + "name": "reserve-x28", + "value": 62, + "desc": "Reserve X28." + }, + { + "name": "reserve-x29", + "value": 63, + "desc": "Reserve X29." + }, + { + "name": "reserve-x3", + "value": 64, + "desc": "Reserve X3." + }, + { + "name": "reserve-x30", + "value": 65, + "desc": "Reserve X30." + }, + { + "name": "reserve-x31", + "value": 66, + "desc": "Reserve X31." + }, + { + "name": "reserve-x4", + "value": 67, + "desc": "Reserve X4." + }, + { + "name": "reserve-x5", + "value": 68, + "desc": "Reserve X5." + }, + { + "name": "reserve-x6", + "value": 69, + "desc": "Reserve X6." + }, + { + "name": "reserve-x7", + "value": 70, + "desc": "Reserve X7." + }, + { + "name": "reserve-x8", + "value": 71, + "desc": "Reserve X8." + }, + { + "name": "reserve-x9", + "value": 72, + "desc": "Reserve X9." + }, + { + "name": "rva20s64", + "value": 73, + "desc": "RISC-V rva20s64 profile." + }, + { + "name": "rva20u64", + "value": 74, + "desc": "RISC-V rva20u64 profile." + }, + { + "name": "rva22s64", + "value": 75, + "desc": "RISC-V rva22s64 profile." + }, + { + "name": "rva22u64", + "value": 76, + "desc": "RISC-V rva22u64 profile." + }, + { + "name": "rvi20u32", + "value": 77, + "desc": "RISC-V rvi20u32 profile." + }, + { + "name": "rvi20u64", + "value": 78, + "desc": "RISC-V rvi20u64 profile." + }, + { + "name": "save-restore", + "value": 79, + "desc": "Enable save/restore.." + }, + { + "name": "shcounterenw", + "value": 80, + "desc": "'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)." + }, + { + "name": "shgatpa", + "value": 81, + "desc": "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)." + }, + { + "name": "shifted-zextw-fusion", + "value": 82, + "desc": "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension." + }, + { + "name": "short-forward-branch-opt", + "value": 83, + "desc": "Enable short forward branch optimization." + }, + { + "name": "shtvala", + "value": 84, + "desc": "'Shtvala' (htval provides all needed values)." + }, + { + "name": "shvsatpa", + "value": 85, + "desc": "'Svsatpa' (vsatp supports all modes supported by satp)." + }, + { + "name": "shvstvala", + "value": 86, + "desc": "'Shvstvala' (vstval provides all needed values)." + }, + { + "name": "shvstvecd", + "value": 87, + "desc": "'Shvstvecd' (vstvec supports Direct mode)." + }, + { + "name": "sifive7", + "value": 88, + "desc": "SiFive 7-Series processors." + }, + { + "name": "smaia", + "value": 89, + "desc": "'Smaia' (Advanced Interrupt Architecture Machine Level)." + }, + { + "name": "smcdeleg", + "value": 90, + "desc": "'Smcdeleg' (Counter Delegation Machine Level)." + }, + { + "name": "smcsrind", + "value": 91, + "desc": "'Smcsrind' (Indirect CSR Access Machine Level)." + }, + { + "name": "smepmp", + "value": 92, + "desc": "'Smepmp' (Enhanced Physical Memory Protection)." + }, + { + "name": "smstateen", + "value": 93, + "desc": "'Smstateen' (Machine-mode view of the state-enable extension)." + }, + { + "name": "ssaia", + "value": 94, + "desc": "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)." + }, + { + "name": "ssccfg", + "value": 95, + "desc": "'Ssccfg' (Counter Configuration Supervisor Level)." + }, + { + "name": "ssccptr", + "value": 96, + "desc": "'Ssccptr' (Main memory supports page table reads)." + }, + { + "name": "sscofpmf", + "value": 97, + "desc": "'Sscofpmf' (Count Overflow and Mode-Based Filtering)." + }, + { + "name": "sscounterenw", + "value": 98, + "desc": "'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)." + }, + { + "name": "sscsrind", + "value": 99, + "desc": "'Sscsrind' (Indirect CSR Access Supervisor Level)." + }, + { + "name": "ssstateen", + "value": 100, + "desc": "'Ssstateen' (Supervisor-mode view of the state-enable extension)." + }, + { + "name": "ssstrict", + "value": 101, + "desc": "'Ssstrict' (No non-conforming extensions are present)." + }, + { + "name": "sstc", + "value": 102, + "desc": "'Sstc' (Supervisor-mode timer interrupts)." + }, + { + "name": "sstvala", + "value": 103, + "desc": "'Sstvala' (stval provides all needed values)." + }, + { + "name": "sstvecd", + "value": 104, + "desc": "'Sstvecd' (stvec supports Direct mode)." + }, + { + "name": "ssu64xl", + "value": 105, + "desc": "'Ssu64xl' (UXLEN=64 supported)." + }, + { + "name": "svade", + "value": 106, + "desc": "'Svade' (Raise exceptions on improper A/D bits)." + }, + { + "name": "svadu", + "value": 107, + "desc": "'Svadu' (Hardware A/D updates)." + }, + { + "name": "svbare", + "value": 108, + "desc": "'Svbare' $(satp mode Bare supported)." + }, + { + "name": "svinval", + "value": 109, + "desc": "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)." + }, + { + "name": "svnapot", + "value": 110, + "desc": "'Svnapot' (NAPOT Translation Contiguity)." + }, + { + "name": "svpbmt", + "value": 111, + "desc": "'Svpbmt' (Page-Based Memory Types)." + }, + { + "name": "tagged-globals", + "value": 112, + "desc": "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits." + }, + { + "name": "unaligned-scalar-mem", + "value": 113, + "desc": "Has reasonably performant unaligned scalar loads and stores." + }, + { + "name": "unaligned-vector-mem", + "value": 114, + "desc": "Has reasonably performant unaligned vector loads and stores." + }, + { + "name": "use-postra-scheduler", + "value": 115, + "desc": "Schedule again after register allocation." + }, + { + "name": "v", + "value": 116, + "desc": "'V' (Vector Extension for Application Processors)." + }, + { + "name": "ventana-veyron", + "value": 117, + "desc": "Ventana Veyron-Series processors." + }, + { + "name": "xcvalu", + "value": 118, + "desc": "'XCValu' (CORE-V ALU Operations)." + }, + { + "name": "xcvbi", + "value": 119, + "desc": "'XCVbi' (CORE-V Immediate Branching)." + }, + { + "name": "xcvbitmanip", + "value": 120, + "desc": "'XCVbitmanip' (CORE-V Bit Manipulation)." + }, + { + "name": "xcvelw", + "value": 121, + "desc": "'XCVelw' (CORE-V Event Load Word)." + }, + { + "name": "xcvmac", + "value": 122, + "desc": "'XCVmac' (CORE-V Multiply-Accumulate)." + }, + { + "name": "xcvmem", + "value": 123, + "desc": "'XCVmem' (CORE-V Post-incrementing Load & Store)." + }, + { + "name": "xcvsimd", + "value": 124, + "desc": "'XCVsimd' (CORE-V SIMD ALU)." + }, + { + "name": "xsfcease", + "value": 125, + "desc": "'XSfcease' (SiFive sf.cease Instruction)." + }, + { + "name": "xsfvcp", + "value": 126, + "desc": "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)." + }, + { + "name": "xsfvfnrclipxfqf", + "value": 127, + "desc": "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)." + }, + { + "name": "xsfvfwmaccqqq", + "value": 128, + "desc": "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))." + }, + { + "name": "xsfvqmaccdod", + "value": 129, + "desc": "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))." + }, + { + "name": "xsfvqmaccqoq", + "value": 130, + "desc": "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))." + }, + { + "name": "xsifivecdiscarddlone", + "value": 131, + "desc": "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)." + }, + { + "name": "xsifivecflushdlone", + "value": 132, + "desc": "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)." + }, + { + "name": "xtheadba", + "value": 133, + "desc": "'XTHeadBa' (T-Head address calculation instructions)." + }, + { + "name": "xtheadbb", + "value": 134, + "desc": "'XTHeadBb' (T-Head basic bit-manipulation instructions)." + }, + { + "name": "xtheadbs", + "value": 135, + "desc": "'XTHeadBs' (T-Head single-bit instructions)." + }, + { + "name": "xtheadcmo", + "value": 136, + "desc": "'XTHeadCmo' (T-Head cache management instructions)." + }, + { + "name": "xtheadcondmov", + "value": 137, + "desc": "'XTHeadCondMov' (T-Head conditional move instructions)." + }, + { + "name": "xtheadfmemidx", + "value": 138, + "desc": "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)." + }, + { + "name": "xtheadmac", + "value": 139, + "desc": "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)." + }, + { + "name": "xtheadmemidx", + "value": 140, + "desc": "'XTHeadMemIdx' (T-Head Indexed Memory Operations)." + }, + { + "name": "xtheadmempair", + "value": 141, + "desc": "'XTHeadMemPair' (T-Head two-GPR Memory Operations)." + }, + { + "name": "xtheadsync", + "value": 142, + "desc": "'XTHeadSync' (T-Head multicore synchronization instructions)." + }, + { + "name": "xtheadvdot", + "value": 143, + "desc": "'XTHeadVdot' (T-Head Vector Extensions for Dot)." + }, + { + "name": "xventanacondops", + "value": 144, + "desc": "'XVentanaCondOps' (Ventana Conditional Ops)." + }, + { + "name": "xwchc", + "value": 145, + "desc": "'Xwchc' (WCH/QingKe additional compressed opcodes)." + }, + { + "name": "za128rs", + "value": 146, + "desc": "'Za128rs' (Reservation Set Size of at Most 128 Bytes)." + }, + { + "name": "za64rs", + "value": 147, + "desc": "'Za64rs' (Reservation Set Size of at Most 64 Bytes)." + }, + { + "name": "zaamo", + "value": 148, + "desc": "'Zaamo' (Atomic Memory Operations)." + }, + { + "name": "zabha", + "value": 149, + "desc": "'Zabha' (Byte and Halfword Atomic Memory Operations)." + }, + { + "name": "zalrsc", + "value": 150, + "desc": "'Zalrsc' (Load-Reserved/Store-Conditional)." + }, + { + "name": "zama16b", + "value": 151, + "desc": "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)." + }, + { + "name": "zawrs", + "value": 152, + "desc": "'Zawrs' (Wait on Reservation Set)." + }, + { + "name": "zba", + "value": 153, + "desc": "'Zba' (Address Generation Instructions)." + }, + { + "name": "zbb", + "value": 154, + "desc": "'Zbb' (Basic Bit-Manipulation)." + }, + { + "name": "zbc", + "value": 155, + "desc": "'Zbc' (Carry-Less Multiplication)." + }, + { + "name": "zbkb", + "value": 156, + "desc": "'Zbkb' (Bitmanip instructions for Cryptography)." + }, + { + "name": "zbkc", + "value": 157, + "desc": "'Zbkc' (Carry-less multiply instructions for Cryptography)." + }, + { + "name": "zbkx", + "value": 158, + "desc": "'Zbkx' (Crossbar permutation instructions)." + }, + { + "name": "zbs", + "value": 159, + "desc": "'Zbs' (Single-Bit Instructions)." + }, + { + "name": "zca", + "value": 160, + "desc": "'Zca' (part of the C extension, excluding compressed floating point loads/stores)." + }, + { + "name": "zcb", + "value": 161, + "desc": "'Zcb' (Compressed basic bit manipulation instructions)." + }, + { + "name": "zcd", + "value": 162, + "desc": "'Zcd' (Compressed Double-Precision Floating-Point Instructions)." + }, + { + "name": "zce", + "value": 163, + "desc": "'Zce' (Compressed extensions for microcontrollers)." + }, + { + "name": "zcf", + "value": 164, + "desc": "'Zcf' (Compressed Single-Precision Floating-Point Instructions)." + }, + { + "name": "zcmop", + "value": 165, + "desc": "'Zcmop' (Compressed May-Be-Operations)." + }, + { + "name": "zcmp", + "value": 166, + "desc": "'Zcmp' (sequenced instructions for code-size reduction)." + }, + { + "name": "zcmt", + "value": 167, + "desc": "'Zcmt' (table jump instructions for code-size reduction)." + }, + { + "name": "zdinx", + "value": 168, + "desc": "'Zdinx' (Double in Integer)." + }, + { + "name": "zexth-fusion", + "value": 169, + "desc": "Enable SLLI+SRLI to be fused to zero extension of halfword." + }, + { + "name": "zextw-fusion", + "value": 170, + "desc": "Enable SLLI+SRLI to be fused to zero extension of word." + }, + { + "name": "zfa", + "value": 171, + "desc": "'Zfa' (Additional Floating-Point)." + }, + { + "name": "zfbfmin", + "value": 172, + "desc": "'Zfbfmin' (Scalar BF16 Converts)." + }, + { + "name": "zfh", + "value": 173, + "desc": "'Zfh' (Half-Precision Floating-Point)." + }, + { + "name": "zfhmin", + "value": 174, + "desc": "'Zfhmin' (Half-Precision Floating-Point Minimal)." + }, + { + "name": "zfinx", + "value": 175, + "desc": "'Zfinx' (Float in Integer)." + }, + { + "name": "zhinx", + "value": 176, + "desc": "'Zhinx' (Half Float in Integer)." + }, + { + "name": "zhinxmin", + "value": 177, + "desc": "'Zhinxmin' (Half Float in Integer Minimal)." + }, + { + "name": "zic64b", + "value": 178, + "desc": "'Zic64b' (Cache Block Size Is 64 Bytes)." + }, + { + "name": "zicbom", + "value": 179, + "desc": "'Zicbom' (Cache-Block Management Instructions)." + }, + { + "name": "zicbop", + "value": 180, + "desc": "'Zicbop' (Cache-Block Prefetch Instructions)." + }, + { + "name": "zicboz", + "value": 181, + "desc": "'Zicboz' (Cache-Block Zero Instructions)." + }, + { + "name": "ziccamoa", + "value": 182, + "desc": "'Ziccamoa' (Main Memory Supports All Atomics in A)." + }, + { + "name": "ziccif", + "value": 183, + "desc": "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)." + }, + { + "name": "zicclsm", + "value": 184, + "desc": "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)." + }, + { + "name": "ziccrse", + "value": 185, + "desc": "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)." + }, + { + "name": "zicntr", + "value": 186, + "desc": "'Zicntr' (Base Counters and Timers)." + }, + { + "name": "zicond", + "value": 187, + "desc": "'Zicond' (Integer Conditional Operations)." + }, + { + "name": "zicsr", + "value": 188, + "desc": "'zicsr' (CSRs)." + }, + { + "name": "zifencei", + "value": 189, + "desc": "'Zifencei' (fence.i)." + }, + { + "name": "zihintntl", + "value": 190, + "desc": "'Zihintntl' (Non-Temporal Locality Hints)." + }, + { + "name": "zihintpause", + "value": 191, + "desc": "'Zihintpause' (Pause Hint)." + }, + { + "name": "zihpm", + "value": 192, + "desc": "'Zihpm' (Hardware Performance Counters)." + }, + { + "name": "zimop", + "value": 193, + "desc": "'Zimop' (May-Be-Operations)." + }, + { + "name": "zk", + "value": 194, + "desc": "'Zk' (Standard scalar cryptography extension)." + }, + { + "name": "zkn", + "value": 195, + "desc": "'Zkn' (NIST Algorithm Suite)." + }, + { + "name": "zknd", + "value": 196, + "desc": "'Zknd' (NIST Suite: AES Decryption)." + }, + { + "name": "zkne", + "value": 197, + "desc": "'Zkne' (NIST Suite: AES Encryption)." + }, + { + "name": "zknh", + "value": 198, + "desc": "'Zknh' (NIST Suite: Hash Function Instructions)." + }, + { + "name": "zkr", + "value": 199, + "desc": "'Zkr' (Entropy Source Extension)." + }, + { + "name": "zks", + "value": 200, + "desc": "'Zks' (ShangMi Algorithm Suite)." + }, + { + "name": "zksed", + "value": 201, + "desc": "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)." + }, + { + "name": "zksh", + "value": 202, + "desc": "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)." + }, + { + "name": "zkt", + "value": 203, + "desc": "'Zkt' (Data Independent Execution Latency)." + }, + { + "name": "zmmul", + "value": 204, + "desc": "'Zmmul' (Integer Multiplication)." + }, + { + "name": "ztso", + "value": 205, + "desc": "'Ztso' (Memory Model" + }, + { + "name": "zvbb", + "value": 206, + "desc": "'Zvbb' (Vector basic bit-manipulation instructions)." + }, + { + "name": "zvbc", + "value": 207, + "desc": "'Zvbc' (Vector Carryless Multiplication)." + }, + { + "name": "zve32f", + "value": 208, + "desc": "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)." + }, + { + "name": "zve32x", + "value": 209, + "desc": "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)." + }, + { + "name": "zve64d", + "value": 210, + "desc": "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)." + }, + { + "name": "zve64f", + "value": 211, + "desc": "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)." + }, + { + "name": "zve64x", + "value": 212, + "desc": "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)." + }, + { + "name": "zvfbfmin", + "value": 213, + "desc": "'Zvbfmin' (Vector BF16 Converts)." + }, + { + "name": "zvfbfwma", + "value": 214, + "desc": "'Zvfbfwma' (Vector BF16 widening mul-add)." + }, + { + "name": "zvfh", + "value": 215, + "desc": "'Zvfh' (Vector Half-Precision Floating-Point)." + }, + { + "name": "zvfhmin", + "value": 216, + "desc": "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)." + }, + { + "name": "zvkb", + "value": 217, + "desc": "'Zvkb' (Vector Bit-manipulation used in Cryptography)." + }, + { + "name": "zvkg", + "value": 218, + "desc": "'Zvkg' (Vector GCM instructions for Cryptography)." + }, + { + "name": "zvkn", + "value": 219, + "desc": "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')." + }, + { + "name": "zvknc", + "value": 220, + "desc": "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')." + }, + { + "name": "zvkned", + "value": 221, + "desc": "'Zvkned' (Vector AES Encryption & Decryption (Single Round))." + }, + { + "name": "zvkng", + "value": 222, + "desc": "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')." + }, + { + "name": "zvknha", + "value": 223, + "desc": "'Zvknha' (Vector SHA-2 (SHA-256 only))." + }, + { + "name": "zvknhb", + "value": 224, + "desc": "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))." + }, + { + "name": "zvks", + "value": 225, + "desc": "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')." + }, + { + "name": "zvksc", + "value": 226, + "desc": "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')." + }, + { + "name": "zvksed", + "value": 227, + "desc": "'Zvksed' (SM4 Block Cipher Instructions)." + }, + { + "name": "zvksg", + "value": 228, + "desc": "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')." + }, + { + "name": "zvksh", + "value": 229, + "desc": "'Zvksh' (SM3 Hash Function Instructions)." + }, + { + "name": "zvkt", + "value": 230, + "desc": "'Zvkt' (Vector Data-Independent Execution Latency)." + }, + { + "name": "zvl1024b", + "value": 231, + "desc": "'Zvl' (Minimum Vector Length) 1024." + }, + { + "name": "zvl128b", + "value": 232, + "desc": "'Zvl' (Minimum Vector Length) 128." + }, + { + "name": "zvl16384b", + "value": 233, + "desc": "'Zvl' (Minimum Vector Length) 16384." + }, + { + "name": "zvl2048b", + "value": 234, + "desc": "'Zvl' (Minimum Vector Length) 2048." + }, + { + "name": "zvl256b", + "value": 235, + "desc": "'Zvl' (Minimum Vector Length) 256." + }, + { + "name": "zvl32768b", + "value": 236, + "desc": "'Zvl' (Minimum Vector Length) 32768." + }, + { + "name": "zvl32b", + "value": 237, + "desc": "'Zvl' (Minimum Vector Length) 32." + }, + { + "name": "zvl4096b", + "value": 238, + "desc": "'Zvl' (Minimum Vector Length) 4096." + }, + { + "name": "zvl512b", + "value": 239, + "desc": "'Zvl' (Minimum Vector Length) 512." + }, + { + "name": "zvl64b", + "value": 240, + "desc": "'Zvl' (Minimum Vector Length) 64." + }, + { + "name": "zvl65536b", + "value": 241, + "desc": "'Zvl' (Minimum Vector Length) 65536." + }, + { + "name": "zvl8192b", + "value": 242, + "desc": "'Zvl' (Minimum Vector Length) 8192." + } + ] + }, + "architecture_categories": [ + { + "name": "unknown", + "value": 0, + "desc": "Unknown category" + }, + { + "name": "cpu", + "value": 1, + "desc": "Central processing unit" + }, + { + "name": "gpu", + "value": 2, + "desc": "Graphics processing unit" + }, + { + "name": "npu", + "value": 3, + "desc": "Neural processing unit (AI accelerator)" + } + ], + "architecture_families": { + "unknown": [ + { + "name": "generic", + "value": 0, + "desc": "Generic family" + } + ], + "cpu": [ + { + "name": "generic", + "value": 0, + "desc": "Generic CPU" + }, + { + "name": "intel", + "value": 1, + "desc": "Intel main line of CPUs" + }, + { + "name": "intel_atom", + "value": 2, + "desc": "Intel Atom/Low-power line of CPUs" + }, + { + "name": "amd", + "value": 3, + "desc": "AMD CPU" + }, + { + "name": "arm_a", + "value": 4, + "desc": "ARM Cortex-A CPU family" + }, + { + "name": "arm_m", + "value": 5, + "desc": "ARM Cortex-M CPU family" + }, + { + "name": "arm_r", + "value": 6, + "desc": "ARM Cortex-R CPU family" + }, + { + "name": "codasip_lp", + "value": 7, + "desc": "Codasip low-power cores" + }, + { + "name": "codasip_hp", + "value": 8, + "desc": "Codasip high-performance cores" + }, + { + "name": "codasip_ap", + "value": 9, + "desc": "Codasip application cores" + }, + { + "name": "sifive_e2", + "value": 10, + "desc": "SiFive Essential 2-series" + }, + { + "name": "sifive_e6", + "value": 11, + "desc": "SiFive Essential 6-series" + }, + { + "name": "sifive_e7", + "value": 12, + "desc": "SiFive Essential 7-series" + }, + { + "name": "sifive_x200", + "value": 13, + "desc": "SiFive Essential X200 Series" + }, + { + "name": "sifive_x300", + "value": 14, + "desc": "SiFive Essential X300 Series" + }, + { + "name": "sifive_xm", + "value": 15, + "desc": "SiFive Essential XM Series" + }, + { + "name": "sifive_p400", + "value": 16, + "desc": "SiFive Essential P400 Series" + }, + { + "name": "sifive_p500", + "value": 17, + "desc": "SiFive Essential P500 Series" + }, + { + "name": "sifive_p600", + "value": 18, + "desc": "SiFive Essential P600 Series" + }, + { + "name": "sifive_p800", + "value": 19, + "desc": "SiFive Essential P800 Series" + }, + { + "name": "sifive_e6a", + "value": 20, + "desc": "SiFive Essential E6-A Series" + }, + { + "name": "sifive_e7a", + "value": 21, + "desc": "SiFive Essential E7-A Series" + }, + { + "name": "sifive_s7a", + "value": 22, + "desc": "SiFive Essential S7-A Series" + } + ], + "gpu": [ + { + "name": "generic", + "value": 0, + "desc": "Generic GPU" + }, + { + "name": "intel", + "value": 1, + "desc": "Intel GPU" + }, + { + "name": "amd", + "value": 2, + "desc": "AMD GPU" + }, + { + "name": "nvidia", + "value": 3, + "desc": "NVIDIA GPU" + } + ], + "npu": [ + { + "name": "generic", + "value": 0, + "desc": "Generic NPU" + }, + { + "name": "intel", + "value": 1, + "desc": "Intel NPU" + }, + { + "name": "amd_xdna", + "value": 2, + "desc": "AMD XDNA NPU" + } + ] + }, + "architectures": { + "unknown": { + "generic": [ + { + "name": "any", + "value": 0, + "desc": "Any architecture" + } + ] + }, + "cpu": { + "generic": [ + { + "name": "any", + "value": 0, + "desc": "Any CPU" + } + ], + "intel": [ + { + "name": "any", + "value": 0, + "desc": "Any Intel CPU" + }, + { + "name": "nhm", + "value": 1, + "desc": "Intel Nehalem microarchitecture" + }, + { + "name": "wsm", + "value": 2, + "desc": "Intel Westmere microarchitecture" + }, + { + "name": "sdb", + "value": 3, + "desc": "Intel Sandy Bridge microarchitecture" + }, + { + "name": "ivb", + "value": 4, + "desc": "Intel Ivy Bridge microarchitecture" + }, + { + "name": "hsw", + "value": 5, + "desc": "Intel Haswell microarchitecture" + }, + { + "name": "bdw", + "value": 6, + "desc": "Intel Broadwell microarchitecture" + }, + { + "name": "skl", + "value": 7, + "desc": "Intel Skylake microarchitecture" + }, + { + "name": "pmc", + "value": 8, + "desc": "Intel Palm Cove microarchitecture" + }, + { + "name": "snc", + "value": 9, + "desc": "Intel Sunny Cove microarchitecture" + }, + { + "name": "wlc", + "value": 10, + "desc": "Intel Willow Cove microarchitecture" + }, + { + "name": "cpc", + "value": 11, + "desc": "Intel Cypress Cove microarchitecture" + }, + { + "name": "gdc", + "value": 12, + "desc": "Intel Golden Cove microarchitecture" + }, + { + "name": "rpc", + "value": 13, + "desc": "Intel Raptor Cove microarchitecture" + }, + { + "name": "rdc", + "value": 14, + "desc": "Intel Redwood Cove microarchitecture" + }, + { + "name": "lnc", + "value": 15, + "desc": "Intel Lion Cove microarchitecture" + } + ], + "intel_atom": [ + { + "name": "any", + "value": 0, + "desc": "Any Intel Atom/Low-power CPU" + }, + { + "name": "bnl", + "value": 1, + "desc": "Intel Bonnell microarchitecture" + }, + { + "name": "slw", + "value": 2, + "desc": "Intel Saltwell microarchitecture" + }, + { + "name": "svm", + "value": 3, + "desc": "Intel Silvermont microarchitecture" + }, + { + "name": "aim", + "value": 4, + "desc": "Intel Airmont microarchitecture" + }, + { + "name": "gdm", + "value": 5, + "desc": "Intel Goldmont microarchitecture" + }, + { + "name": "gdm_p", + "value": 6, + "desc": "Intel Goldmont Plus microarchitecture" + }, + { + "name": "trm", + "value": 7, + "desc": "Intel Tremont microarchitecture" + }, + { + "name": "gcm", + "value": 8, + "desc": "Intel Gracemont microarchitecture" + }, + { + "name": "csm", + "value": 9, + "desc": "Intel Crestmont microarchitecture" + }, + { + "name": "skm", + "value": 10, + "desc": "Intel Skymont microarchitecture" + } + ], + "amd": [ + { + "name": "any", + "value": 0, + "desc": "Any AMD CPU" + }, + { + "name": "zen", + "value": 1, + "desc": "AMD Zen microarchitecture" + }, + { + "name": "zenp", + "value": 2, + "desc": "AMD Zen+ microarchitecture" + }, + { + "name": "zen2", + "value": 3, + "desc": "AMD Zen2 microarchitecture" + }, + { + "name": "zen3", + "value": 4, + "desc": "AMD Zen3 microarchitecture" + }, + { + "name": "zen3p", + "value": 5, + "desc": "AMD Zen3+ microarchitecture" + }, + { + "name": "zen4", + "value": 6, + "desc": "AMD Zen4 microarchitecture" + }, + { + "name": "zen4c", + "value": 7, + "desc": "AMD Zen4c microarchitecture" + }, + { + "name": "zen5", + "value": 8, + "desc": "AMD Zen5 microarchitecture" + }, + { + "name": "zen5c", + "value": 9, + "desc": "AMD Zen5c microarchitecture" + } + ], + "arm_a": [ + { + "name": "any", + "value": 0, + "desc": "Any CPU microarchitecture from the ARM Cortex-A family" + }, + { + "name": "a8", + "value": 1, + "desc": "ARM Cortex-A8 (32-bit)" + }, + { + "name": "a9", + "value": 2, + "desc": "ARM Cortex-A9 (32-bit)" + }, + { + "name": "a5", + "value": 3, + "desc": "ARM Cortex-A5 (32-bit)" + }, + { + "name": "a15", + "value": 4, + "desc": "ARM Cortex-A15 (32-bit)" + }, + { + "name": "a7", + "value": 5, + "desc": "ARM Cortex-A7 (32-bit)" + }, + { + "name": "a53", + "value": 6, + "desc": "ARM Cortex-A53 (32/64-bit)" + }, + { + "name": "a57", + "value": 7, + "desc": "ARM Cortex-A57 (32/64-bit)" + }, + { + "name": "a12", + "value": 8, + "desc": "ARM Cortex-A12 (32-bit)" + }, + { + "name": "a17", + "value": 9, + "desc": "ARM Cortex-A17 (32-bit)" + }, + { + "name": "a32", + "value": 10, + "desc": "ARM Cortex-A32 (32-bit)" + }, + { + "name": "a34", + "value": 11, + "desc": "ARM Cortex-A34 (64-bit)" + }, + { + "name": "a73", + "value": 12, + "desc": "ARM Cortex-A73 (32/64-bit)" + }, + { + "name": "a55", + "value": 13, + "desc": "ARM Cortex-A55 (32/64-bit)" + }, + { + "name": "a75", + "value": 14, + "desc": "ARM Cortex-A75 (32/64-bit)" + }, + { + "name": "a65", + "value": 15, + "desc": "ARM Cortex-A65 (64-bit)" + }, + { + "name": "a76", + "value": 16, + "desc": "ARM Cortex-A76 (32/64-bit)" + }, + { + "name": "a77", + "value": 17, + "desc": "ARM Cortex-A77 (32/64-bit)" + }, + { + "name": "a78", + "value": 18, + "desc": "ARM Cortex-A78 (32/64-bit)" + }, + { + "name": "a78ae", + "value": 19, + "desc": "ARM Cortex-A78AE (32/64-bit)" + }, + { + "name": "a510", + "value": 20, + "desc": "ARM Cortex-A510 (64-bit)" + }, + { + "name": "a710", + "value": 21, + "desc": "ARM Cortex-A710 (32/64-bit)" + }, + { + "name": "a510r", + "value": 22, + "desc": "ARM Cortex-A510 (refresh) (32/64-bit)" + }, + { + "name": "a715", + "value": 23, + "desc": "ARM Cortex-A715 (64-bit)" + }, + { + "name": "a520", + "value": 24, + "desc": "ARM Cortex-A520 (64-bit)" + }, + { + "name": "a720", + "value": 25, + "desc": "ARM Cortex-A720 (64-bit)" + }, + { + "name": "a520ae", + "value": 26, + "desc": "ARM Cortex-A520AE (64-bit)" + }, + { + "name": "a720ae", + "value": 27, + "desc": "ARM Cortex-A720AE (64-bit)" + }, + { + "name": "a725", + "value": 28, + "desc": "ARM Cortex-A725 (64-bit)" + }, + { + "name": "a320", + "value": 29, + "desc": "ARM Cortex-A320 (64-bit)" + }, + { + "name": "a530", + "value": 30, + "desc": "ARM Cortex-A530 (64-bit)" + }, + { + "name": "a730", + "value": 31, + "desc": "ARM Cortex-A730 (64-bit)" + } + ], + "arm_m": [ + { + "name": "any", + "value": 0, + "desc": "Any CPU microarchitecture from the ARM Cortex-M family" + }, + { + "name": "m3", + "value": 1, + "desc": "ARM Cortex-M3" + }, + { + "name": "m1", + "value": 2, + "desc": "ARM Cortex-M1" + }, + { + "name": "m0", + "value": 3, + "desc": "ARM Cortex-M0" + }, + { + "name": "m4", + "value": 4, + "desc": "ARM Cortex-M4" + }, + { + "name": "m0p", + "value": 5, + "desc": "ARM Cortex-M0+" + }, + { + "name": "m7", + "value": 6, + "desc": "ARM Cortex-M7" + }, + { + "name": "m23", + "value": 7, + "desc": "ARM Cortex-M23" + }, + { + "name": "m33", + "value": 8, + "desc": "ARM Cortex-M33" + }, + { + "name": "m35p", + "value": 9, + "desc": "ARM Cortex-M35P" + }, + { + "name": "m55", + "value": 10, + "desc": "ARM Cortex-M55" + }, + { + "name": "m85", + "value": 11, + "desc": "ARM Cortex-M85" + }, + { + "name": "m52", + "value": 12, + "desc": "ARM Cortex-M52" + } + ], + "arm_r": [ + { + "name": "any", + "value": 0, + "desc": "Any CPU microarchitecture from the ARM Cortex-R family" + }, + { + "name": "r4", + "value": 1, + "desc": "ARM Cortex-R4 (32-bit)" + }, + { + "name": "r5", + "value": 2, + "desc": "ARM Cortex-R5 (32-bit)" + }, + { + "name": "r7", + "value": 3, + "desc": "ARM Cortex-R7 (32-bit)" + }, + { + "name": "r8", + "value": 4, + "desc": "ARM Cortex-R8 (32-bit)" + }, + { + "name": "r52", + "value": 5, + "desc": "ARM Cortex-R52 (32-bit)" + }, + { + "name": "r82", + "value": 6, + "desc": "ARM Cortex-R82 (64-bit)" + }, + { + "name": "r52p", + "value": 7, + "desc": "ARM Cortex-R52+ (32-bit)" + } + ], + "codasip_lp": [ + { + "name": "any", + "value": 0, + "desc": "Any Codasip low-power CPU" + }, + { + "name": "l110", + "value": 1, + "desc": "Codasip L110" + }, + { + "name": "l150", + "value": 2, + "desc": "Codasip L150" + }, + { + "name": "l31", + "value": 3, + "desc": "Codasip L31" + } + ], + "codasip_hp": [ + { + "name": "any", + "value": 0, + "desc": "Any Codasip high-performance CPU" + }, + { + "name": "l730", + "value": 1, + "desc": "Codasip L730" + } + ], + "codasip_ap": [ + { + "name": "any", + "value": 0, + "desc": "Any Codasip application CPU" + }, + { + "name": "a70", + "value": 1, + "desc": "Codasip A70" + }, + { + "name": "a730", + "value": 2, + "desc": "Codasip A730" + }, + { + "name": "x730", + "value": 3, + "desc": "Codasip X730" + } + ], + "sifive_e2": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential 2-series CPU" + } + ], + "sifive_e6": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential 6-series CPU" + } + ], + "sifive_e7": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential 7-series CPU" + } + ], + "sifive_x200": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential X200 Series CPU" + } + ], + "sifive_x300": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential X300 Series CPU" + } + ], + "sifive_xm": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential XM Series CPU" + } + ], + "sifive_p400": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential P400 Series CPU" + } + ], + "sifive_p500": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential P500 Series CPU" + } + ], + "sifive_p600": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential P600 Series CPU" + } + ], + "sifive_p800": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential P800 Series CPU" + } + ], + "sifive_e6a": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential E6-A Series CPU" + } + ], + "sifive_e7a": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential E7-A Series CPU" + } + ], + "sifive_s7a": [ + { + "name": "any", + "value": 0, + "desc": "Any SiFive Essential S7-A Series CPU" + } + ] + }, + "gpu": { + "generic": [ + { + "name": "any", + "value": 0, + "desc": "Any GPU" + } + ], + "intel": [ + { + "name": "any", + "value": 0, + "desc": "Any Intel GPU" + }, + { + "name": "bdw", + "value": 1, + "desc": "Broadwell Intel graphics architecture" + }, + { + "name": "v8_0_0", + "value": 1, + "desc": "Broadwell Intel graphics architecture" + }, + { + "name": "skl", + "value": 2, + "desc": "Skylake Intel graphics architecture" + }, + { + "name": "v9_0_9", + "value": 2, + "desc": "Skylake Intel graphics architecture" + }, + { + "name": "kbl", + "value": 3, + "desc": "Kaby Lake Intel graphics architecture" + }, + { + "name": "v9_1_9", + "value": 3, + "desc": "Kaby Lake Intel graphics architecture" + }, + { + "name": "cfl", + "value": 4, + "desc": "Coffee Lake Intel graphics architecture" + }, + { + "name": "v9_2_9", + "value": 4, + "desc": "Coffee Lake Intel graphics architecture" + }, + { + "name": "apl", + "value": 5, + "desc": "Apollo Lake Intel graphics architecture" + }, + { + "name": "v9_3_0", + "value": 5, + "desc": "Apollo Lake Intel graphics architecture" + }, + { + "name": "bxt", + "value": 5, + "desc": "Broxton Intel graphics architecture" + }, + { + "name": "glk", + "value": 6, + "desc": "Gemini Lake Intel graphics architecture" + }, + { + "name": "v9_4_0", + "value": 6, + "desc": "Gemini Lake Intel graphics architecture" + }, + { + "name": "whl", + "value": 7, + "desc": "Whiskey Lake Intel graphics architecture" + }, + { + "name": "v9_5_0", + "value": 7, + "desc": "Whiskey Lake Intel graphics architecture" + }, + { + "name": "aml", + "value": 8, + "desc": "Amber Lake Intel graphics architecture" + }, + { + "name": "v9_6_0", + "value": 8, + "desc": "Amber Lake Intel graphics architecture" + }, + { + "name": "cml", + "value": 9, + "desc": "Comet Lake Intel graphics architecture" + }, + { + "name": "v9_7_0", + "value": 9, + "desc": "Comet Lake Intel graphics architecture" + }, + { + "name": "icllp", + "value": 10, + "desc": "Ice Lake Intel graphics architecture" + }, + { + "name": "icl", + "value": 10, + "desc": "Ice Lake Intel graphics architecture" + }, + { + "name": "v11_0_0", + "value": 10, + "desc": "Ice Lake Intel graphics architecture" + }, + { + "name": "ehl", + "value": 11, + "desc": "Elkhart Lake Intel graphics architecture" + }, + { + "name": "v11_2_0", + "value": 11, + "desc": "Elkhart Lake Intel graphics architecture" + }, + { + "name": "jsl", + "value": 11, + "desc": "Jasper Lake Intel graphics architecture" + }, + { + "name": "tgllp", + "value": 12, + "desc": "Tiger Lake Intel graphics architecture" + }, + { + "name": "tgl", + "value": 12, + "desc": "Tiger Lake Intel graphics architecture" + }, + { + "name": "v12_0_0", + "value": 12, + "desc": "Tiger Lake Intel graphics architecture" + }, + { + "name": "rkl", + "value": 13, + "desc": "Rocket Lake Intel graphics architecture" + }, + { + "name": "v12_1_0", + "value": 13, + "desc": "Rocket Lake Intel graphics architecture" + }, + { + "name": "adl_s", + "value": 14, + "desc": "Alder Lake S Intel graphics architecture" + }, + { + "name": "v12_2_0", + "value": 14, + "desc": "Alder Lake S Intel graphics architecture" + }, + { + "name": "rpl_s", + "value": 14, + "desc": "Raptor Lake Intel graphics architecture" + }, + { + "name": "adl_p", + "value": 15, + "desc": "Alder Lake P Intel graphics architecture" + }, + { + "name": "v12_3_0", + "value": 15, + "desc": "Alder Lake P Intel graphics architecture" + }, + { + "name": "adl_n", + "value": 16, + "desc": "Alder Lake N Intel graphics architecture" + }, + { + "name": "v12_4_0", + "value": 16, + "desc": "Alder Lake N Intel graphics architecture" + }, + { + "name": "dg1", + "value": 17, + "desc": "DG1 Intel graphics architecture" + }, + { + "name": "v12_10_0", + "value": 17, + "desc": "DG1 Intel graphics architecture" + }, + { + "name": "acm_g10", + "value": 18, + "desc": "Alchemist G10 Intel graphics architecture" + }, + { + "name": "dg2_g10", + "value": 18, + "desc": "Alchemist G10 Intel graphics architecture" + }, + { + "name": "v12_55_8", + "value": 18, + "desc": "Alchemist G10 Intel graphics architecture" + }, + { + "name": "acm_g11", + "value": 19, + "desc": "Alchemist G11 Intel graphics architecture" + }, + { + "name": "dg2_g11", + "value": 19, + "desc": "Alchemist G11 Intel graphics architecture" + }, + { + "name": "v12_56_5", + "value": 19, + "desc": "Alchemist G11 Intel graphics architecture" + }, + { + "name": "acm_g12", + "value": 20, + "desc": "Alchemist G12 Intel graphics architecture" + }, + { + "name": "dg2_g12", + "value": 20, + "desc": "Alchemist G12 Intel graphics architecture" + }, + { + "name": "v12_57_0", + "value": 20, + "desc": "Alchemist G12 Intel graphics architecture" + }, + { + "name": "pvc", + "value": 21, + "desc": "Ponte Vecchio Intel graphics architecture" + }, + { + "name": "v12_60_7", + "value": 21, + "desc": "Ponte Vecchio Intel graphics architecture" + }, + { + "name": "pvc_vg", + "value": 22, + "desc": "Ponte Vecchio VG Intel graphics architecture" + }, + { + "name": "v12_61_7", + "value": 22, + "desc": "Ponte Vecchio VG Intel graphics architecture" + }, + { + "name": "mtl_u", + "value": 23, + "desc": "Meteor Lake U Intel graphics architecture" + }, + { + "name": "mtl_s", + "value": 23, + "desc": "Meteor Lake S Intel graphics architecture" + }, + { + "name": "arl_u", + "value": 23, + "desc": "Arrow Lake U Intel graphics architecture" + }, + { + "name": "arl_s", + "value": 23, + "desc": "Arrow Lake S Intel graphics architecture" + }, + { + "name": "v12_70_4", + "value": 23, + "desc": "Meteor Lake U Intel graphics architecture" + }, + { + "name": "mtl_h", + "value": 24, + "desc": "Meteor Lake H Intel graphics architecture" + }, + { + "name": "v12_71_4", + "value": 24, + "desc": "Meteor Lake H Intel graphics architecture" + }, + { + "name": "arl_h", + "value": 25, + "desc": "Arrow Lake H Intel graphics architecture" + }, + { + "name": "v12_74_4", + "value": 25, + "desc": "Arrow Lake H Intel graphics architecture" + }, + { + "name": "bmg_g21", + "value": 26, + "desc": "Battlemage G21 Intel graphics architecture" + }, + { + "name": "v20_1_4", + "value": 26, + "desc": "Battlemage G21 Intel graphics architecture" + }, + { + "name": "lnl_m", + "value": 27, + "desc": "Lunar Lake Intel graphics architecture" + }, + { + "name": "v20_4_4", + "value": 27, + "desc": "Lunar Lake Intel graphics architecture" + }, + { + "name": "ptl_h", + "value": 28, + "desc": "Panther Lake H Intel graphics architecture" + }, + { + "name": "v30_0_4", + "value": 28, + "desc": "Panther Lake H Intel graphics architecture" + }, + { + "name": "ptl_u", + "value": 29, + "desc": "Panther Lake U Intel graphics architecture" + }, + { + "name": "v30_1_1", + "value": 29, + "desc": "Panther Lake U Intel graphics architecture" + } + ], + "amd": [ + { + "name": "any", + "value": 0, + "desc": "Any AMD GPU" + }, + { + "name": "gfx700", + "value": 1, + "desc": "AMD GCN 2.0 microarchitecture" + }, + { + "name": "gfx701", + "value": 1, + "desc": "AMD GCN 2.0 microarchitecture" + }, + { + "name": "gfx702", + "value": 1, + "desc": "AMD GCN 2.0 microarchitecture" + }, + { + "name": "gfx703", + "value": 1, + "desc": "AMD GCN 2.0 microarchitecture" + }, + { + "name": "gfx704", + "value": 1, + "desc": "AMD GCN 2.0 microarchitecture" + }, + { + "name": "gfx705", + "value": 1, + "desc": "AMD GCN 2.0 microarchitecture" + }, + { + "name": "gfx801", + "value": 2, + "desc": "AMD GCN 3.0 microarchitecture" + }, + { + "name": "gfx802", + "value": 2, + "desc": "AMD GCN 3.0 microarchitecture" + }, + { + "name": "gfx803", + "value": 3, + "desc": "AMD GCN 4.0 microarchitecture" + }, + { + "name": "gfx805", + "value": 4, + "desc": "AMD GCN 3.0 microarchitecture" + }, + { + "name": "gfx810", + "value": 4, + "desc": "AMD GCN 3.0 microarchitecture" + }, + { + "name": "gfx900", + "value": 5, + "desc": "AMD GCN 5.0 microarchitecture" + }, + { + "name": "gfx902", + "value": 5, + "desc": "AMD GCN 5.0 microarchitecture" + }, + { + "name": "gfx904", + "value": 5, + "desc": "AMD GCN 5.0 microarchitecture" + }, + { + "name": "gfx906", + "value": 6, + "desc": "AMD GCN 5.1 microarchitecture" + }, + { + "name": "gfx908", + "value": 7, + "desc": "AMD CDNA 1 microarchitecture" + }, + { + "name": "gfx909", + "value": 8, + "desc": "AMD GCN 5.0 microarchitecture" + }, + { + "name": "gfx90a", + "value": 9, + "desc": "AMD CDNA 2 microarchitecture" + }, + { + "name": "gfx90c", + "value": 10, + "desc": "AMD GCN 5.1 microarchitecture" + }, + { + "name": "gfx940", + "value": 11, + "desc": "AMD CDNA 3 microarchitecture" + }, + { + "name": "gfx941", + "value": 11, + "desc": "AMD CDNA 3 microarchitecture" + }, + { + "name": "gfx942", + "value": 11, + "desc": "AMD CDNA 3 microarchitecture" + }, + { + "name": "gfx1010", + "value": 12, + "desc": "AMD RDNA 1 microarchitecture" + }, + { + "name": "gfx1011", + "value": 12, + "desc": "AMD RDNA 1 microarchitecture" + }, + { + "name": "gfx1012", + "value": 12, + "desc": "AMD RDNA 1 microarchitecture" + }, + { + "name": "gfx1013", + "value": 12, + "desc": "AMD RDNA 1 microarchitecture" + }, + { + "name": "gfx1030", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1031", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1032", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1033", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1034", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1035", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1036", + "value": 13, + "desc": "AMD RDNA 2 microarchitecture" + }, + { + "name": "gfx1100", + "value": 14, + "desc": "AMD RDNA 3 microarchitecture" + }, + { + "name": "gfx1101", + "value": 14, + "desc": "AMD RDNA 3 microarchitecture" + }, + { + "name": "gfx1102", + "value": 14, + "desc": "AMD RDNA 3 microarchitecture" + }, + { + "name": "gfx1103", + "value": 14, + "desc": "AMD RDNA 3 microarchitecture" + }, + { + "name": "gfx1150", + "value": 15, + "desc": "AMD RDNA 3.5 microarchitecture" + }, + { + "name": "gfx1151", + "value": 15, + "desc": "AMD RDNA 3.5 microarchitecture" + }, + { + "name": "gfx1200", + "value": 16, + "desc": "AMD RDNA 4 microarchitecture" + }, + { + "name": "gfx1201", + "value": 16, + "desc": "AMD RDNA 4 microarchitecture" + } + ], + "nvidia": [ + { + "name": "any", + "value": 0, + "desc": "Any NVIDIA GPU" + }, + { + "name": "sm50", + "value": 1, + "desc": "NVIDIA Maxwell microarchitecture (compute capability 5.0)" + }, + { + "name": "sm52", + "value": 2, + "desc": "NVIDIA Maxwell microarchitecture (compute capability 5.2)" + }, + { + "name": "sm53", + "value": 3, + "desc": "NVIDIA Maxwell microarchitecture (compute capability 5.3)" + }, + { + "name": "sm60", + "value": 4, + "desc": "NVIDIA Pascal microarchitecture (compute capability 6.0)" + }, + { + "name": "sm61", + "value": 5, + "desc": "NVIDIA Pascal microarchitecture (compute capability 6.1)" + }, + { + "name": "sm62", + "value": 6, + "desc": "NVIDIA Pascal microarchitecture (compute capability 6.2)" + }, + { + "name": "sm70", + "value": 6, + "desc": "NVIDIA Volta microarchitecture (compute capability 7.0)" + }, + { + "name": "sm72", + "value": 7, + "desc": "NVIDIA Volta microarchitecture (compute capability 7.2)" + }, + { + "name": "sm75", + "value": 8, + "desc": "NVIDIA Turing microarchitecture (compute capability 7.5)" + }, + { + "name": "sm80", + "value": 9, + "desc": "NVIDIA Ampere microarchitecture (compute capability 8.0)" + }, + { + "name": "sm86", + "value": 10, + "desc": "NVIDIA Ampere microarchitecture (compute capability 8.6)" + }, + { + "name": "sm87", + "value": 11, + "desc": "NVIDIA Jetson/Drive AGX Orin microarchitecture" + }, + { + "name": "sm89", + "value": 12, + "desc": "NVIDIA Ada Lovelace arhitecture" + }, + { + "name": "sm90", + "value": 13, + "desc": "NVIDIA Hopper arhitecture" + }, + { + "name": "sm90a", + "value": 13, + "desc": "NVIDIA Hopper arhitecture" + } + ] + }, + "npu": { + "generic": [ + { + "name": "any", + "value": 0, + "desc": "Any NPU" + } + ], + "intel": [ + { + "name": "any", + "value": 0, + "desc": "Any Intel NPU" + }, + { + "name": "mtl", + "value": 1, + "desc": "Intel NPU used in Meteor Lake processors" + }, + { + "name": "lnl", + "value": 2, + "desc": "Intel NPU used in Lunar Lake processors" + } + ], + "amd_xdna": [ + { + "name": "any", + "value": 0, + "desc": "Any AMD XDNA architecture" + } + ] + } + } +} \ No newline at end of file diff --git a/sycl/doc/design/spirv-extensions/targets/generate.py b/sycl/doc/design/spirv-extensions/targets/generate.py new file mode 100644 index 0000000000000..bebd9d6aeb2f0 --- /dev/null +++ b/sycl/doc/design/spirv-extensions/targets/generate.py @@ -0,0 +1,413 @@ +import io +import json +import re +from pathlib import Path + +SOURCE_JSON = "core.json" +HEADER_NAME = Path("registry.h") +TARGETS_ASCIIDOC_NAME = Path("targets.asciidoc") +ARCH_ASCIIDOC_NAME = Path("architectures.asciidoc") + +# some unique identifier: +HEADER_PREFIX = "FnVar" +HEADER_PREFIX_UPPER = "FNVAR" +HEADER_MAXVAL = 2**31 - 1 + +ASCIIDOC_COLS_W = { + "name": "8", + "value": "3", + "desc": "10", +} + +### C header + + +def _name(name: str) -> str: + replaced = re.sub(r"[^a-zA-Z0-9_]", "_", name) + return "".join([part.capitalize() for part in replaced.split("_")]) + + +def write_header_init(data: dict, outfile: io.TextIOWrapper): + outfile.write("// This header is automatically generated by generate.py.\n\n") + outfile.write(f"#define {HEADER_PREFIX_UPPER}_VERSION ({data['version']})\n") + + +def write_header_targets(data: dict, outfile: io.TextIOWrapper): + targets = data["targets"] + prefix = f"{HEADER_PREFIX}Target" + + outfile.write(f"typedef enum {prefix}_ {{\n") + + for target in targets: + outfile.write( + f" {prefix}_{_name(target['name'])} = {target['value']}, //" + f" {target['desc']}\n" + ) + + outfile.write(f" {prefix}_Max = {HEADER_MAXVAL:#08x},\n") + outfile.write(f"}} {prefix};\n") + + +def write_header_features(data: dict, outfile: io.TextIOWrapper): + at_least_one = False + + for target, features in data["features"].items(): + if at_least_one: + outfile.write("\n") + at_least_one = True + + prefix = f"{HEADER_PREFIX}Feature_{_name(target)}" + + outfile.write(f"typedef enum {prefix}_ {{\n") + + for feature in features: + outfile.write( + f" {prefix}_{_name(feature['name'])} = {feature['value']}, //" + f" {feature['desc']}\n" + ) + + outfile.write(f" {prefix}_Max = {HEADER_MAXVAL:#08x},\n") + outfile.write(f"}} {prefix};\n") + + +def write_header_architecture_categories(data: dict, outfile: io.TextIOWrapper): + arch_cats = data["architecture_categories"] + prefix = f"{HEADER_PREFIX}ArchCategory" + + outfile.write(f"typedef enum {prefix}_ {{\n") + + for arch_cat in arch_cats: + outfile.write( + f" {prefix}_{_name(arch_cat['name'])} = {arch_cat['value']}, //" + f" {arch_cat['desc']}\n" + ) + + outfile.write(f" {prefix}_Max = {HEADER_MAXVAL:#08x},\n") + outfile.write(f"}} {prefix};\n") + + +def write_header_architecture_families(data: dict, outfile: io.TextIOWrapper): + at_least_one = False + + for arch_cat, arch_fams in data["architecture_families"].items(): + if at_least_one: + outfile.write("\n") + at_least_one = True + + prefix = f"{HEADER_PREFIX}ArchFamily_{_name(arch_cat)}" + + outfile.write(f"typedef enum {prefix}_ {{\n") + + for arch_fam in arch_fams: + outfile.write( + f" {prefix}_{_name(arch_fam['name'])} = {arch_fam['value']}, //" + f" {arch_fam['desc']}\n" + ) + + outfile.write(f" {prefix}_Max = {HEADER_MAXVAL:#08x},\n") + outfile.write(f"}} {prefix};\n") + + +def write_header_architectures(data: dict, outfile: io.TextIOWrapper): + at_least_one = False + + for arch_cat, arch_fams in data["architectures"].items(): + for arch_fam, archs in arch_fams.items(): + if at_least_one: + outfile.write("\n") + at_least_one = True + + prefix = f"{HEADER_PREFIX}Arch_{_name(arch_cat)}_{_name(arch_fam)}" + + outfile.write(f"typedef enum {prefix}_ {{\n") + + for arch in archs: + outfile.write( + f" {prefix}_{_name(arch['name'])} = {arch['value']}, //" + f" {arch['desc']}\n" + ) + + outfile.write(f" {prefix}_Max = {HEADER_MAXVAL:#08x},\n") + outfile.write(f"}} {prefix};\n") + + +### asciidoc tables + + +def _write_entries_with_aliases( + entries: list, outfile: io.TextIOWrapper, extras: list = [] +): + seen_aliases = [] + for i, entry in enumerate(entries): + if entry["name"] in seen_aliases: + continue + aliases = [] + if i < len(entries) - 1: + for entry2 in entries[i + 1 :]: + if entry["value"] == entry2["value"]: + aliases.append(entry2["name"]) + seen_aliases.extend(aliases) + + outfile.write("\n") + outfile.write("a|\n") + outfile.write("[source]\n") + outfile.write("----\n") + outfile.write(f'{entry["name"]}\n') + for alias in aliases: + outfile.write(f'{alias} = {entry["name"]}\n') + outfile.write("----\n") + for val in extras: + outfile.write(f"| {val}\n") + outfile.write(f'| {entry["value"]}\n') + outfile.write(f'| {entry["desc"]}\n') + + +def _value_of_name(name: str, entries: list, in_what: str) -> int: + value = None + for entry in entries: + if name == entry["name"]: + value = entry["value"] + break + + if value is None: + raise ValueError(f"{name} not found in {in_what}.") + + return value + + +def write_asciidoc_targets(data: dict, outfile: io.TextIOWrapper): + targets = data["targets"] + + cols_w = [ + ASCIIDOC_COLS_W["name"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["desc"], + ] + cols_w_str = ",".join(cols_w) + + outfile.write(f'[%header,cols="{cols_w_str}"]\n') + outfile.write("|===\n") + outfile.write("|Name\n") + outfile.write("|Value\n") + outfile.write("|Description\n") + + _write_entries_with_aliases(targets, outfile) + + outfile.write("|===\n") + + +def write_asciidoc_features(data: dict, outfile: io.TextIOWrapper): + features = data["features"] + targets = data["targets"] + + cols_w = [ + ASCIIDOC_COLS_W["name"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["desc"], + ] + cols_w_str = ",".join(cols_w) + + outfile.write(f'[%header,cols="{cols_w_str}"]\n') + outfile.write("|===\n") + outfile.write("|Name\n") + outfile.write("|Target\n") + outfile.write("|Value\n") + outfile.write("|Description\n") + + seen_targets = {} + for target, features in features.items(): + target_value = _value_of_name(target, targets, "targets") + target_aliases = [ + tgt["name"] for tgt in targets if tgt["value"] == target_value + ] + if target_value in seen_targets: + raise ValueError( + f"Target '{target}' with value {target_value} is an alias of" + f" '{seen_targets[target_value]}' and thus cannot have its own" + " features." + ) + seen_targets[target_value] = target + + outfile.write( + f"\n{len(cols_w)}+^|*Target:" + f" {', '.join(target_aliases)} ({target_value})*\n" + ) + _write_entries_with_aliases(features, outfile, extras=[target_value]) + + outfile.write("|===\n") + + +def write_asciidoc_architecture_categories(data: dict, outfile: io.TextIOWrapper): + categories = data["architecture_categories"] + + cols_w = [ + ASCIIDOC_COLS_W["name"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["desc"], + ] + cols_w_str = ",".join(cols_w) + + outfile.write(f'[%header,cols="{cols_w_str}"]\n') + outfile.write("|===\n") + outfile.write("|Name\n") + outfile.write("|Value\n") + outfile.write("|Description\n") + + _write_entries_with_aliases(categories, outfile) + + outfile.write("|===\n") + + +def write_asciidoc_architecture_families(data: dict, outfile: io.TextIOWrapper): + families = data["architecture_families"] + categories = data["architecture_categories"] + + cols_w = [ + ASCIIDOC_COLS_W["name"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["desc"], + ] + cols_w_str = ",".join(cols_w) + + outfile.write(f'[%header,cols="{cols_w_str}"]\n') + outfile.write("|===\n") + outfile.write("|Name\n") + outfile.write("|Category\n") + outfile.write("|Value\n") + outfile.write("|Description\n") + + seen_categories = {} + for category, families in families.items(): + category_value = _value_of_name(category, categories, "categories") + category_aliases = [ + cat["name"] for cat in categories if cat["value"] == category_value + ] + if category_value in seen_categories: + raise ValueError( + f"Category '{category}' with value {category_value} is an alias of" + f" '{seen_categories[category_value]}' and thus cannot have its own" + " families." + ) + seen_categories[category_value] = category + + outfile.write( + f"\n{len(cols_w)}+^|*Category:" + f" {', '.join(category_aliases)} ({category_value})*\n" + ) + _write_entries_with_aliases(families, outfile, extras=[category_value]) + + outfile.write("|===\n") + + +def write_asciidoc_architectures(data: dict, outfile: io.TextIOWrapper): + categories = data["architecture_categories"] + families = data["architecture_families"] + architectures = data["architectures"] + + cols_w = [ + ASCIIDOC_COLS_W["name"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["value"], + ASCIIDOC_COLS_W["desc"], + ] + cols_w_str = ",".join(cols_w) + + outfile.write(f'[%header,cols="{cols_w_str}"]\n') + outfile.write("|===\n") + outfile.write("|Name\n") + outfile.write("|Category\n") + outfile.write("|Family\n") + outfile.write("|Value\n") + outfile.write("|Description\n") + + seen_categories = {} + for arch_category, arch_families in architectures.items(): + category_value = _value_of_name(arch_category, categories, "categories") + category_aliases = [ + cat["name"] for cat in categories if cat["value"] == category_value + ] + if category_value in seen_categories: + raise ValueError( + f"Category '{arch_category}' with value {category_value} is an alias of" + f" '{seen_categories[category_value]}' and thus cannot have its own" + " families or architectures." + ) + seen_categories[category_value] = arch_category + + seen_families = {} + for arch_family, arch_architectures in arch_families.items(): + family_value = _value_of_name( + arch_family, + families[arch_category], + f"families of {arch_category} category", + ) + family_aliases = [ + fam["name"] + for fam in families[arch_category] + if fam["value"] == family_value + ] + if family_value in seen_families: + raise ValueError( + f"Family '{arch_family}' with value {family_value} is an alias of" + f" '{seen_families[family_value]}' and thus cannot have its own" + " architectures." + ) + seen_families[family_value] = arch_family + + outfile.write( + f"\n{len(cols_w)}+^|*Category:" + f" {', '.join(category_aliases)} ({category_value}), Family:" + f" {', '.join(family_aliases)} ({family_value})*\n" + ) + _write_entries_with_aliases( + arch_architectures, outfile, extras=[category_value, family_value] + ) + + outfile.write("|===\n") + + +def main(): + with open(SOURCE_JSON) as rf: + data = json.load(rf) + + print(f"Writing {HEADER_NAME}") + with open(HEADER_NAME, "w") as wf: + write_header_init(data, wf) + + wf.write("\n// Targets\n\n") + write_header_targets(data, wf) + + wf.write("\n// Features\n\n") + write_header_features(data, wf) + + wf.write("\n// Architecture Categories\n\n") + write_header_architecture_categories(data, wf) + + wf.write("\n// Architecture Families\n\n") + write_header_architecture_families(data, wf) + + wf.write("\n// Architectures\n\n") + write_header_architectures(data, wf) + + print(f"Writing {TARGETS_ASCIIDOC_NAME}") + with open(TARGETS_ASCIIDOC_NAME, "w") as wf: + wf.write("\n== Targets\n\n") + write_asciidoc_targets(data, wf) + wf.write("\n== Features\n\n") + write_asciidoc_features(data, wf) + + print(f"Writing {ARCH_ASCIIDOC_NAME}") + with open(ARCH_ASCIIDOC_NAME, "w") as wf: + wf.write("\n== Architecture Categories\n\n") + write_asciidoc_architecture_categories(data, wf) + wf.write("\n== Architecture Families\n\n") + write_asciidoc_architecture_families(data, wf) + wf.write("\n== Architectures\n\n") + write_asciidoc_architectures(data, wf) + + +if __name__ == "__main__": + main() diff --git a/sycl/doc/design/spirv-extensions/targets/registry.h b/sycl/doc/design/spirv-extensions/targets/registry.h new file mode 100644 index 0000000000000..1bd7c77c6d5ab --- /dev/null +++ b/sycl/doc/design/spirv-extensions/targets/registry.h @@ -0,0 +1,1006 @@ +// This header is automatically generated by generate.py. + +#define FNVAR_VERSION (0) + +// Targets + +typedef enum FnVarTarget_ { + FnVarTarget_Unknown = 0, // Unknown target + FnVarTarget_Arm = 1, // ARM (32-bit) + FnVarTarget_Arm32 = 1, // ARM (32-bit) + FnVarTarget_Arm64 = 2, // ARM (64-bit) + FnVarTarget_Aarch64 = 2, // ARM (64-bit) + FnVarTarget_X86 = 3, // x86 (32-bit) + FnVarTarget_X8664 = 4, // x86 (64-bit) + FnVarTarget_Riscv32 = 5, // RISC-V (32-bit) + FnVarTarget_Riscv64 = 6, // RISC-V (64-bit) + FnVarTarget_Nvptx = 7, // NVIDIA PTX (32-bit) + FnVarTarget_Nvptx64 = 8, // NVIDIA PTX (64-bit) + FnVarTarget_Amdgcn = 9, // AMD GCN + FnVarTarget_Max = 0x7fffffff, +} FnVarTarget; + +// Features + +typedef enum FnVarFeature_Unknown_ { + FnVarFeature_Unknown_None = 0, // No features + FnVarFeature_Unknown_Max = 0x7fffffff, +} FnVarFeature_Unknown; + +typedef enum FnVarFeature_Arm32_ { + FnVarFeature_Arm32_None = 0, // No features + FnVarFeature_Arm32_Neon = 1, // Enable NEON instructions + FnVarFeature_Arm32_Max = 0x7fffffff, +} FnVarFeature_Arm32; + +typedef enum FnVarFeature_Arm64_ { + FnVarFeature_Arm64_None = 0, // No features + FnVarFeature_Arm64_Fp8 = 1, // Enable FP8 instructions + FnVarFeature_Arm64_Fp8dot2 = 2, // Enable FP8 2-way dot product instructions + FnVarFeature_Arm64_Fp8dot4 = 3, // Enable FP8 4-way dot product instructions + FnVarFeature_Arm64_Neon = 4, // Enable NEON instructions + FnVarFeature_Arm64_Sve = 5, // Enable SVE instructions + FnVarFeature_Arm64_Max = 0x7fffffff, +} FnVarFeature_Arm64; + +typedef enum FnVarFeature_X86_ { + FnVarFeature_X86_None = 0, // No features + FnVarFeature_X86_Fma = 1, // Enable fused three-operand multiply-add + FnVarFeature_X86_Fma4 = 2, // Enable fused four-operand multiply-add + FnVarFeature_X86_Mmx = 3, // Enable MMX instructions + FnVarFeature_X86_Sse = 4, // Enable SSE instructions + FnVarFeature_X86_Sse2 = 5, // Enable SSE2 instructions + FnVarFeature_X86_Sse3 = 6, // Enable SSE3 instructions + FnVarFeature_X86_Sse41 = 7, // Enable SSE4.1 instructions + FnVarFeature_X86_Sse42 = 8, // Enable SSE4.2 instructions + FnVarFeature_X86_Sse4a = 9, // Enable SSE4a instructions + FnVarFeature_X86_Avx = 10, // Enable AVX instructions + FnVarFeature_X86_Avx2 = 11, // Enable AVX2 instructions + FnVarFeature_X86_Avx512f = 12, // Enable AVX512 instructions + FnVarFeature_X86_Max = 0x7fffffff, +} FnVarFeature_X86; + +typedef enum FnVarFeature_X8664_ { + FnVarFeature_X8664_None = 0, // No features + FnVarFeature_X8664_Fma = 1, // Enable fused three-operand multiply-add + FnVarFeature_X8664_Fma4 = 2, // Enable fused four-operand multiply-add + FnVarFeature_X8664_Mmx = 3, // Enable MMX instructions + FnVarFeature_X8664_Sse = 4, // Enable SSE instructions + FnVarFeature_X8664_Sse2 = 5, // Enable SSE2 instructions + FnVarFeature_X8664_Sse3 = 6, // Enable SSE3 instructions + FnVarFeature_X8664_Sse41 = 7, // Enable SSE4.1 instructions + FnVarFeature_X8664_Sse42 = 8, // Enable SSE4.2 instructions + FnVarFeature_X8664_Sse4a = 9, // Enable SSE4a instructions + FnVarFeature_X8664_Avx = 10, // Enable AVX instructions + FnVarFeature_X8664_Avx2 = 11, // Enable AVX2 instructions + FnVarFeature_X8664_Avx512f = 12, // Enable AVX512 instructions + FnVarFeature_X8664_Max = 0x7fffffff, +} FnVarFeature_X8664; + +typedef enum FnVarFeature_Riscv32_ { + FnVarFeature_Riscv32_32bit = 0, // Implements RV32. + FnVarFeature_Riscv32_64bit = 1, // Implements RV64. + FnVarFeature_Riscv32_A = 2, // 'A' (Atomic Instructions). + FnVarFeature_Riscv32_AuipcAddiFusion = 3, // Enable AUIPC+ADDI macrofusion. + FnVarFeature_Riscv32_B = 4, // 'B' (the collection of the Zba, Zbb, Zbs extensions). + FnVarFeature_Riscv32_C = 5, // 'C' (Compressed Instructions). + FnVarFeature_Riscv32_ConditionalCmvFusion = 6, // Enable branch+c.mv fusion. + FnVarFeature_Riscv32_D = 7, // 'D' (Double-Precision Floating-Point). + FnVarFeature_Riscv32_DlenFactor2 = 8, // Vector unit DLEN(data path width) is half of VLEN. + FnVarFeature_Riscv32_E = 9, // Implements RV{32,64}E (provides 16 rather than 32 GPRs). + FnVarFeature_Riscv32_Experimental = 10, // Experimental intrinsics. + FnVarFeature_Riscv32_ExperimentalRva23s64 = 11, // RISC-V experimental-rva23s64 profile. + FnVarFeature_Riscv32_ExperimentalRva23u64 = 12, // RISC-V experimental-rva23u64 profile. + FnVarFeature_Riscv32_ExperimentalRvb23s64 = 13, // RISC-V experimental-rvb23s64 profile. + FnVarFeature_Riscv32_ExperimentalRvb23u64 = 14, // RISC-V experimental-rvb23u64 profile. + FnVarFeature_Riscv32_ExperimentalRvm23u32 = 15, // RISC-V experimental-rvm23u32 profile. + FnVarFeature_Riscv32_ExperimentalSmmpm = 16, // 'Smmpm' (Machine-level Pointer Masking for M-mode). + FnVarFeature_Riscv32_ExperimentalSmnpm = 17, // 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode). + FnVarFeature_Riscv32_ExperimentalSsnpm = 18, // 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode). + FnVarFeature_Riscv32_ExperimentalSspm = 19, // 'Sspm' (Indicates Supervisor-mode Pointer Masking). + FnVarFeature_Riscv32_ExperimentalSsqosid = 20, // 'Ssqosid' (Quality-of-Service (QoS) Identifiers). + FnVarFeature_Riscv32_ExperimentalSupm = 21, // 'Supm' (Indicates User-mode Pointer Masking). + FnVarFeature_Riscv32_ExperimentalZacas = 22, // 'Zacas' (Atomic Compare-And-Swap Instructions). + FnVarFeature_Riscv32_ExperimentalZalasr = 23, // 'Zalasr' (Load-Acquire and Store-Release Instructions). + FnVarFeature_Riscv32_ExperimentalZicfilp = 24, // 'Zicfilp' (Landing pad). + FnVarFeature_Riscv32_ExperimentalZicfiss = 25, // 'Zicfiss' (Shadow stack). + FnVarFeature_Riscv32_F = 26, // 'F' (Single-Precision Floating-Point). + FnVarFeature_Riscv32_ForcedAtomics = 27, // Assume that lock-free native-width atomics are available. + FnVarFeature_Riscv32_ForcedSwShadowStack = 28, // Implement shadow stack with software.. + FnVarFeature_Riscv32_H = 29, // 'H' (Hypervisor). + FnVarFeature_Riscv32_I = 30, // 'I' (Base Integer Instruction Set). + FnVarFeature_Riscv32_LdAddFusion = 31, // Enable LD+ADD macrofusion. + FnVarFeature_Riscv32_LuiAddiFusion = 32, // Enable LUI+ADDI macro fusion. + FnVarFeature_Riscv32_M = 33, // 'M' (Integer Multiplication and Division). + FnVarFeature_Riscv32_NoDefaultUnroll = 34, // Disable default unroll preference.. + FnVarFeature_Riscv32_NoRvcHints = 35, // Disable RVC Hint Instructions.. + FnVarFeature_Riscv32_NoSinkSplatOperands = 36, // Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions. + FnVarFeature_Riscv32_NoTrailingSeqCstFence = 37, // Disable trailing fence for seq-cst store.. + FnVarFeature_Riscv32_OptimizedZeroStrideLoad = 38, // Optimized (perform fewer memory operations)zero-stride vector load. + FnVarFeature_Riscv32_PredictableSelectExpensive = 39, // Prefer likely predicted branches over selects. + FnVarFeature_Riscv32_PreferWInst = 40, // Prefer instructions with W suffix. + FnVarFeature_Riscv32_Relax = 41, // Enable Linker relaxation.. + FnVarFeature_Riscv32_ReserveX1 = 42, // Reserve X1. + FnVarFeature_Riscv32_ReserveX10 = 43, // Reserve X10. + FnVarFeature_Riscv32_ReserveX11 = 44, // Reserve X11. + FnVarFeature_Riscv32_ReserveX12 = 45, // Reserve X12. + FnVarFeature_Riscv32_ReserveX13 = 46, // Reserve X13. + FnVarFeature_Riscv32_ReserveX14 = 47, // Reserve X14. + FnVarFeature_Riscv32_ReserveX15 = 48, // Reserve X15. + FnVarFeature_Riscv32_ReserveX16 = 49, // Reserve X16. + FnVarFeature_Riscv32_ReserveX17 = 50, // Reserve X17. + FnVarFeature_Riscv32_ReserveX18 = 51, // Reserve X18. + FnVarFeature_Riscv32_ReserveX19 = 52, // Reserve X19. + FnVarFeature_Riscv32_ReserveX2 = 53, // Reserve X2. + FnVarFeature_Riscv32_ReserveX20 = 54, // Reserve X20. + FnVarFeature_Riscv32_ReserveX21 = 55, // Reserve X21. + FnVarFeature_Riscv32_ReserveX22 = 56, // Reserve X22. + FnVarFeature_Riscv32_ReserveX23 = 57, // Reserve X23. + FnVarFeature_Riscv32_ReserveX24 = 58, // Reserve X24. + FnVarFeature_Riscv32_ReserveX25 = 59, // Reserve X25. + FnVarFeature_Riscv32_ReserveX26 = 60, // Reserve X26. + FnVarFeature_Riscv32_ReserveX27 = 61, // Reserve X27. + FnVarFeature_Riscv32_ReserveX28 = 62, // Reserve X28. + FnVarFeature_Riscv32_ReserveX29 = 63, // Reserve X29. + FnVarFeature_Riscv32_ReserveX3 = 64, // Reserve X3. + FnVarFeature_Riscv32_ReserveX30 = 65, // Reserve X30. + FnVarFeature_Riscv32_ReserveX31 = 66, // Reserve X31. + FnVarFeature_Riscv32_ReserveX4 = 67, // Reserve X4. + FnVarFeature_Riscv32_ReserveX5 = 68, // Reserve X5. + FnVarFeature_Riscv32_ReserveX6 = 69, // Reserve X6. + FnVarFeature_Riscv32_ReserveX7 = 70, // Reserve X7. + FnVarFeature_Riscv32_ReserveX8 = 71, // Reserve X8. + FnVarFeature_Riscv32_ReserveX9 = 72, // Reserve X9. + FnVarFeature_Riscv32_Rva20s64 = 73, // RISC-V rva20s64 profile. + FnVarFeature_Riscv32_Rva20u64 = 74, // RISC-V rva20u64 profile. + FnVarFeature_Riscv32_Rva22s64 = 75, // RISC-V rva22s64 profile. + FnVarFeature_Riscv32_Rva22u64 = 76, // RISC-V rva22u64 profile. + FnVarFeature_Riscv32_Rvi20u32 = 77, // RISC-V rvi20u32 profile. + FnVarFeature_Riscv32_Rvi20u64 = 78, // RISC-V rvi20u64 profile. + FnVarFeature_Riscv32_SaveRestore = 79, // Enable save/restore.. + FnVarFeature_Riscv32_Shcounterenw = 80, // 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero). + FnVarFeature_Riscv32_Shgatpa = 81, // 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). + FnVarFeature_Riscv32_ShiftedZextwFusion = 82, // Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. + FnVarFeature_Riscv32_ShortForwardBranchOpt = 83, // Enable short forward branch optimization. + FnVarFeature_Riscv32_Shtvala = 84, // 'Shtvala' (htval provides all needed values). + FnVarFeature_Riscv32_Shvsatpa = 85, // 'Svsatpa' (vsatp supports all modes supported by satp). + FnVarFeature_Riscv32_Shvstvala = 86, // 'Shvstvala' (vstval provides all needed values). + FnVarFeature_Riscv32_Shvstvecd = 87, // 'Shvstvecd' (vstvec supports Direct mode). + FnVarFeature_Riscv32_Sifive7 = 88, // SiFive 7-Series processors. + FnVarFeature_Riscv32_Smaia = 89, // 'Smaia' (Advanced Interrupt Architecture Machine Level). + FnVarFeature_Riscv32_Smcdeleg = 90, // 'Smcdeleg' (Counter Delegation Machine Level). + FnVarFeature_Riscv32_Smcsrind = 91, // 'Smcsrind' (Indirect CSR Access Machine Level). + FnVarFeature_Riscv32_Smepmp = 92, // 'Smepmp' (Enhanced Physical Memory Protection). + FnVarFeature_Riscv32_Smstateen = 93, // 'Smstateen' (Machine-mode view of the state-enable extension). + FnVarFeature_Riscv32_Ssaia = 94, // 'Ssaia' (Advanced Interrupt Architecture Supervisor Level). + FnVarFeature_Riscv32_Ssccfg = 95, // 'Ssccfg' (Counter Configuration Supervisor Level). + FnVarFeature_Riscv32_Ssccptr = 96, // 'Ssccptr' (Main memory supports page table reads). + FnVarFeature_Riscv32_Sscofpmf = 97, // 'Sscofpmf' (Count Overflow and Mode-Based Filtering). + FnVarFeature_Riscv32_Sscounterenw = 98, // 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero). + FnVarFeature_Riscv32_Sscsrind = 99, // 'Sscsrind' (Indirect CSR Access Supervisor Level). + FnVarFeature_Riscv32_Ssstateen = 100, // 'Ssstateen' (Supervisor-mode view of the state-enable extension). + FnVarFeature_Riscv32_Ssstrict = 101, // 'Ssstrict' (No non-conforming extensions are present). + FnVarFeature_Riscv32_Sstc = 102, // 'Sstc' (Supervisor-mode timer interrupts). + FnVarFeature_Riscv32_Sstvala = 103, // 'Sstvala' (stval provides all needed values). + FnVarFeature_Riscv32_Sstvecd = 104, // 'Sstvecd' (stvec supports Direct mode). + FnVarFeature_Riscv32_Ssu64xl = 105, // 'Ssu64xl' (UXLEN=64 supported). + FnVarFeature_Riscv32_Svade = 106, // 'Svade' (Raise exceptions on improper A/D bits). + FnVarFeature_Riscv32_Svadu = 107, // 'Svadu' (Hardware A/D updates). + FnVarFeature_Riscv32_Svbare = 108, // 'Svbare' $(satp mode Bare supported). + FnVarFeature_Riscv32_Svinval = 109, // 'Svinval' (Fine-Grained Address-Translation Cache Invalidation). + FnVarFeature_Riscv32_Svnapot = 110, // 'Svnapot' (NAPOT Translation Contiguity). + FnVarFeature_Riscv32_Svpbmt = 111, // 'Svpbmt' (Page-Based Memory Types). + FnVarFeature_Riscv32_TaggedGlobals = 112, // Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. + FnVarFeature_Riscv32_UnalignedScalarMem = 113, // Has reasonably performant unaligned scalar loads and stores. + FnVarFeature_Riscv32_UnalignedVectorMem = 114, // Has reasonably performant unaligned vector loads and stores. + FnVarFeature_Riscv32_UsePostraScheduler = 115, // Schedule again after register allocation. + FnVarFeature_Riscv32_V = 116, // 'V' (Vector Extension for Application Processors). + FnVarFeature_Riscv32_VentanaVeyron = 117, // Ventana Veyron-Series processors. + FnVarFeature_Riscv32_Xcvalu = 118, // 'XCValu' (CORE-V ALU Operations). + FnVarFeature_Riscv32_Xcvbi = 119, // 'XCVbi' (CORE-V Immediate Branching). + FnVarFeature_Riscv32_Xcvbitmanip = 120, // 'XCVbitmanip' (CORE-V Bit Manipulation). + FnVarFeature_Riscv32_Xcvelw = 121, // 'XCVelw' (CORE-V Event Load Word). + FnVarFeature_Riscv32_Xcvmac = 122, // 'XCVmac' (CORE-V Multiply-Accumulate). + FnVarFeature_Riscv32_Xcvmem = 123, // 'XCVmem' (CORE-V Post-incrementing Load & Store). + FnVarFeature_Riscv32_Xcvsimd = 124, // 'XCVsimd' (CORE-V SIMD ALU). + FnVarFeature_Riscv32_Xsfcease = 125, // 'XSfcease' (SiFive sf.cease Instruction). + FnVarFeature_Riscv32_Xsfvcp = 126, // 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions). + FnVarFeature_Riscv32_Xsfvfnrclipxfqf = 127, // 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions). + FnVarFeature_Riscv32_Xsfvfwmaccqqq = 128, // 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4)). + FnVarFeature_Riscv32_Xsfvqmaccdod = 129, // 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)). + FnVarFeature_Riscv32_Xsfvqmaccqoq = 130, // 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)). + FnVarFeature_Riscv32_Xsifivecdiscarddlone = 131, // 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). + FnVarFeature_Riscv32_Xsifivecflushdlone = 132, // 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). + FnVarFeature_Riscv32_Xtheadba = 133, // 'XTHeadBa' (T-Head address calculation instructions). + FnVarFeature_Riscv32_Xtheadbb = 134, // 'XTHeadBb' (T-Head basic bit-manipulation instructions). + FnVarFeature_Riscv32_Xtheadbs = 135, // 'XTHeadBs' (T-Head single-bit instructions). + FnVarFeature_Riscv32_Xtheadcmo = 136, // 'XTHeadCmo' (T-Head cache management instructions). + FnVarFeature_Riscv32_Xtheadcondmov = 137, // 'XTHeadCondMov' (T-Head conditional move instructions). + FnVarFeature_Riscv32_Xtheadfmemidx = 138, // 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations). + FnVarFeature_Riscv32_Xtheadmac = 139, // 'XTHeadMac' (T-Head Multiply-Accumulate Instructions). + FnVarFeature_Riscv32_Xtheadmemidx = 140, // 'XTHeadMemIdx' (T-Head Indexed Memory Operations). + FnVarFeature_Riscv32_Xtheadmempair = 141, // 'XTHeadMemPair' (T-Head two-GPR Memory Operations). + FnVarFeature_Riscv32_Xtheadsync = 142, // 'XTHeadSync' (T-Head multicore synchronization instructions). + FnVarFeature_Riscv32_Xtheadvdot = 143, // 'XTHeadVdot' (T-Head Vector Extensions for Dot). + FnVarFeature_Riscv32_Xventanacondops = 144, // 'XVentanaCondOps' (Ventana Conditional Ops). + FnVarFeature_Riscv32_Xwchc = 145, // 'Xwchc' (WCH/QingKe additional compressed opcodes). + FnVarFeature_Riscv32_Za128rs = 146, // 'Za128rs' (Reservation Set Size of at Most 128 Bytes). + FnVarFeature_Riscv32_Za64rs = 147, // 'Za64rs' (Reservation Set Size of at Most 64 Bytes). + FnVarFeature_Riscv32_Zaamo = 148, // 'Zaamo' (Atomic Memory Operations). + FnVarFeature_Riscv32_Zabha = 149, // 'Zabha' (Byte and Halfword Atomic Memory Operations). + FnVarFeature_Riscv32_Zalrsc = 150, // 'Zalrsc' (Load-Reserved/Store-Conditional). + FnVarFeature_Riscv32_Zama16b = 151, // 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs). + FnVarFeature_Riscv32_Zawrs = 152, // 'Zawrs' (Wait on Reservation Set). + FnVarFeature_Riscv32_Zba = 153, // 'Zba' (Address Generation Instructions). + FnVarFeature_Riscv32_Zbb = 154, // 'Zbb' (Basic Bit-Manipulation). + FnVarFeature_Riscv32_Zbc = 155, // 'Zbc' (Carry-Less Multiplication). + FnVarFeature_Riscv32_Zbkb = 156, // 'Zbkb' (Bitmanip instructions for Cryptography). + FnVarFeature_Riscv32_Zbkc = 157, // 'Zbkc' (Carry-less multiply instructions for Cryptography). + FnVarFeature_Riscv32_Zbkx = 158, // 'Zbkx' (Crossbar permutation instructions). + FnVarFeature_Riscv32_Zbs = 159, // 'Zbs' (Single-Bit Instructions). + FnVarFeature_Riscv32_Zca = 160, // 'Zca' (part of the C extension, excluding compressed floating point loads/stores). + FnVarFeature_Riscv32_Zcb = 161, // 'Zcb' (Compressed basic bit manipulation instructions). + FnVarFeature_Riscv32_Zcd = 162, // 'Zcd' (Compressed Double-Precision Floating-Point Instructions). + FnVarFeature_Riscv32_Zce = 163, // 'Zce' (Compressed extensions for microcontrollers). + FnVarFeature_Riscv32_Zcf = 164, // 'Zcf' (Compressed Single-Precision Floating-Point Instructions). + FnVarFeature_Riscv32_Zcmop = 165, // 'Zcmop' (Compressed May-Be-Operations). + FnVarFeature_Riscv32_Zcmp = 166, // 'Zcmp' (sequenced instructions for code-size reduction). + FnVarFeature_Riscv32_Zcmt = 167, // 'Zcmt' (table jump instructions for code-size reduction). + FnVarFeature_Riscv32_Zdinx = 168, // 'Zdinx' (Double in Integer). + FnVarFeature_Riscv32_ZexthFusion = 169, // Enable SLLI+SRLI to be fused to zero extension of halfword. + FnVarFeature_Riscv32_ZextwFusion = 170, // Enable SLLI+SRLI to be fused to zero extension of word. + FnVarFeature_Riscv32_Zfa = 171, // 'Zfa' (Additional Floating-Point). + FnVarFeature_Riscv32_Zfbfmin = 172, // 'Zfbfmin' (Scalar BF16 Converts). + FnVarFeature_Riscv32_Zfh = 173, // 'Zfh' (Half-Precision Floating-Point). + FnVarFeature_Riscv32_Zfhmin = 174, // 'Zfhmin' (Half-Precision Floating-Point Minimal). + FnVarFeature_Riscv32_Zfinx = 175, // 'Zfinx' (Float in Integer). + FnVarFeature_Riscv32_Zhinx = 176, // 'Zhinx' (Half Float in Integer). + FnVarFeature_Riscv32_Zhinxmin = 177, // 'Zhinxmin' (Half Float in Integer Minimal). + FnVarFeature_Riscv32_Zic64b = 178, // 'Zic64b' (Cache Block Size Is 64 Bytes). + FnVarFeature_Riscv32_Zicbom = 179, // 'Zicbom' (Cache-Block Management Instructions). + FnVarFeature_Riscv32_Zicbop = 180, // 'Zicbop' (Cache-Block Prefetch Instructions). + FnVarFeature_Riscv32_Zicboz = 181, // 'Zicboz' (Cache-Block Zero Instructions). + FnVarFeature_Riscv32_Ziccamoa = 182, // 'Ziccamoa' (Main Memory Supports All Atomics in A). + FnVarFeature_Riscv32_Ziccif = 183, // 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement). + FnVarFeature_Riscv32_Zicclsm = 184, // 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores). + FnVarFeature_Riscv32_Ziccrse = 185, // 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences). + FnVarFeature_Riscv32_Zicntr = 186, // 'Zicntr' (Base Counters and Timers). + FnVarFeature_Riscv32_Zicond = 187, // 'Zicond' (Integer Conditional Operations). + FnVarFeature_Riscv32_Zicsr = 188, // 'zicsr' (CSRs). + FnVarFeature_Riscv32_Zifencei = 189, // 'Zifencei' (fence.i). + FnVarFeature_Riscv32_Zihintntl = 190, // 'Zihintntl' (Non-Temporal Locality Hints). + FnVarFeature_Riscv32_Zihintpause = 191, // 'Zihintpause' (Pause Hint). + FnVarFeature_Riscv32_Zihpm = 192, // 'Zihpm' (Hardware Performance Counters). + FnVarFeature_Riscv32_Zimop = 193, // 'Zimop' (May-Be-Operations). + FnVarFeature_Riscv32_Zk = 194, // 'Zk' (Standard scalar cryptography extension). + FnVarFeature_Riscv32_Zkn = 195, // 'Zkn' (NIST Algorithm Suite). + FnVarFeature_Riscv32_Zknd = 196, // 'Zknd' (NIST Suite: AES Decryption). + FnVarFeature_Riscv32_Zkne = 197, // 'Zkne' (NIST Suite: AES Encryption). + FnVarFeature_Riscv32_Zknh = 198, // 'Zknh' (NIST Suite: Hash Function Instructions). + FnVarFeature_Riscv32_Zkr = 199, // 'Zkr' (Entropy Source Extension). + FnVarFeature_Riscv32_Zks = 200, // 'Zks' (ShangMi Algorithm Suite). + FnVarFeature_Riscv32_Zksed = 201, // 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions). + FnVarFeature_Riscv32_Zksh = 202, // 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions). + FnVarFeature_Riscv32_Zkt = 203, // 'Zkt' (Data Independent Execution Latency). + FnVarFeature_Riscv32_Zmmul = 204, // 'Zmmul' (Integer Multiplication). + FnVarFeature_Riscv32_Ztso = 205, // 'Ztso' (Memory Model + FnVarFeature_Riscv32_Zvbb = 206, // 'Zvbb' (Vector basic bit-manipulation instructions). + FnVarFeature_Riscv32_Zvbc = 207, // 'Zvbc' (Vector Carryless Multiplication). + FnVarFeature_Riscv32_Zve32f = 208, // 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension). + FnVarFeature_Riscv32_Zve32x = 209, // 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW). + FnVarFeature_Riscv32_Zve64d = 210, // 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension). + FnVarFeature_Riscv32_Zve64f = 211, // 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension). + FnVarFeature_Riscv32_Zve64x = 212, // 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW). + FnVarFeature_Riscv32_Zvfbfmin = 213, // 'Zvbfmin' (Vector BF16 Converts). + FnVarFeature_Riscv32_Zvfbfwma = 214, // 'Zvfbfwma' (Vector BF16 widening mul-add). + FnVarFeature_Riscv32_Zvfh = 215, // 'Zvfh' (Vector Half-Precision Floating-Point). + FnVarFeature_Riscv32_Zvfhmin = 216, // 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal). + FnVarFeature_Riscv32_Zvkb = 217, // 'Zvkb' (Vector Bit-manipulation used in Cryptography). + FnVarFeature_Riscv32_Zvkg = 218, // 'Zvkg' (Vector GCM instructions for Cryptography). + FnVarFeature_Riscv32_Zvkn = 219, // 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'). + FnVarFeature_Riscv32_Zvknc = 220, // 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc'). + FnVarFeature_Riscv32_Zvkned = 221, // 'Zvkned' (Vector AES Encryption & Decryption (Single Round)). + FnVarFeature_Riscv32_Zvkng = 222, // 'zvkng' (shorthand for 'Zvkn' and 'Zvkg'). + FnVarFeature_Riscv32_Zvknha = 223, // 'Zvknha' (Vector SHA-2 (SHA-256 only)). + FnVarFeature_Riscv32_Zvknhb = 224, // 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)). + FnVarFeature_Riscv32_Zvks = 225, // 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'). + FnVarFeature_Riscv32_Zvksc = 226, // 'Zvksc' (shorthand for 'Zvks' and 'Zvbc'). + FnVarFeature_Riscv32_Zvksed = 227, // 'Zvksed' (SM4 Block Cipher Instructions). + FnVarFeature_Riscv32_Zvksg = 228, // 'Zvksg' (shorthand for 'Zvks' and 'Zvkg'). + FnVarFeature_Riscv32_Zvksh = 229, // 'Zvksh' (SM3 Hash Function Instructions). + FnVarFeature_Riscv32_Zvkt = 230, // 'Zvkt' (Vector Data-Independent Execution Latency). + FnVarFeature_Riscv32_Zvl1024b = 231, // 'Zvl' (Minimum Vector Length) 1024. + FnVarFeature_Riscv32_Zvl128b = 232, // 'Zvl' (Minimum Vector Length) 128. + FnVarFeature_Riscv32_Zvl16384b = 233, // 'Zvl' (Minimum Vector Length) 16384. + FnVarFeature_Riscv32_Zvl2048b = 234, // 'Zvl' (Minimum Vector Length) 2048. + FnVarFeature_Riscv32_Zvl256b = 235, // 'Zvl' (Minimum Vector Length) 256. + FnVarFeature_Riscv32_Zvl32768b = 236, // 'Zvl' (Minimum Vector Length) 32768. + FnVarFeature_Riscv32_Zvl32b = 237, // 'Zvl' (Minimum Vector Length) 32. + FnVarFeature_Riscv32_Zvl4096b = 238, // 'Zvl' (Minimum Vector Length) 4096. + FnVarFeature_Riscv32_Zvl512b = 239, // 'Zvl' (Minimum Vector Length) 512. + FnVarFeature_Riscv32_Zvl64b = 240, // 'Zvl' (Minimum Vector Length) 64. + FnVarFeature_Riscv32_Zvl65536b = 241, // 'Zvl' (Minimum Vector Length) 65536. + FnVarFeature_Riscv32_Zvl8192b = 242, // 'Zvl' (Minimum Vector Length) 8192. + FnVarFeature_Riscv32_Max = 0x7fffffff, +} FnVarFeature_Riscv32; + +typedef enum FnVarFeature_Riscv64_ { + FnVarFeature_Riscv64_32bit = 0, // Implements RV32. + FnVarFeature_Riscv64_64bit = 1, // Implements RV64. + FnVarFeature_Riscv64_A = 2, // 'A' (Atomic Instructions). + FnVarFeature_Riscv64_AuipcAddiFusion = 3, // Enable AUIPC+ADDI macrofusion. + FnVarFeature_Riscv64_B = 4, // 'B' (the collection of the Zba, Zbb, Zbs extensions). + FnVarFeature_Riscv64_C = 5, // 'C' (Compressed Instructions). + FnVarFeature_Riscv64_ConditionalCmvFusion = 6, // Enable branch+c.mv fusion. + FnVarFeature_Riscv64_D = 7, // 'D' (Double-Precision Floating-Point). + FnVarFeature_Riscv64_DlenFactor2 = 8, // Vector unit DLEN(data path width) is half of VLEN. + FnVarFeature_Riscv64_E = 9, // Implements RV{32,64}E (provides 16 rather than 32 GPRs). + FnVarFeature_Riscv64_Experimental = 10, // Experimental intrinsics. + FnVarFeature_Riscv64_ExperimentalRva23s64 = 11, // RISC-V experimental-rva23s64 profile. + FnVarFeature_Riscv64_ExperimentalRva23u64 = 12, // RISC-V experimental-rva23u64 profile. + FnVarFeature_Riscv64_ExperimentalRvb23s64 = 13, // RISC-V experimental-rvb23s64 profile. + FnVarFeature_Riscv64_ExperimentalRvb23u64 = 14, // RISC-V experimental-rvb23u64 profile. + FnVarFeature_Riscv64_ExperimentalRvm23u32 = 15, // RISC-V experimental-rvm23u32 profile. + FnVarFeature_Riscv64_ExperimentalSmmpm = 16, // 'Smmpm' (Machine-level Pointer Masking for M-mode). + FnVarFeature_Riscv64_ExperimentalSmnpm = 17, // 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode). + FnVarFeature_Riscv64_ExperimentalSsnpm = 18, // 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode). + FnVarFeature_Riscv64_ExperimentalSspm = 19, // 'Sspm' (Indicates Supervisor-mode Pointer Masking). + FnVarFeature_Riscv64_ExperimentalSsqosid = 20, // 'Ssqosid' (Quality-of-Service (QoS) Identifiers). + FnVarFeature_Riscv64_ExperimentalSupm = 21, // 'Supm' (Indicates User-mode Pointer Masking). + FnVarFeature_Riscv64_ExperimentalZacas = 22, // 'Zacas' (Atomic Compare-And-Swap Instructions). + FnVarFeature_Riscv64_ExperimentalZalasr = 23, // 'Zalasr' (Load-Acquire and Store-Release Instructions). + FnVarFeature_Riscv64_ExperimentalZicfilp = 24, // 'Zicfilp' (Landing pad). + FnVarFeature_Riscv64_ExperimentalZicfiss = 25, // 'Zicfiss' (Shadow stack). + FnVarFeature_Riscv64_F = 26, // 'F' (Single-Precision Floating-Point). + FnVarFeature_Riscv64_ForcedAtomics = 27, // Assume that lock-free native-width atomics are available. + FnVarFeature_Riscv64_ForcedSwShadowStack = 28, // Implement shadow stack with software.. + FnVarFeature_Riscv64_H = 29, // 'H' (Hypervisor). + FnVarFeature_Riscv64_I = 30, // 'I' (Base Integer Instruction Set). + FnVarFeature_Riscv64_LdAddFusion = 31, // Enable LD+ADD macrofusion. + FnVarFeature_Riscv64_LuiAddiFusion = 32, // Enable LUI+ADDI macro fusion. + FnVarFeature_Riscv64_M = 33, // 'M' (Integer Multiplication and Division). + FnVarFeature_Riscv64_NoDefaultUnroll = 34, // Disable default unroll preference.. + FnVarFeature_Riscv64_NoRvcHints = 35, // Disable RVC Hint Instructions.. + FnVarFeature_Riscv64_NoSinkSplatOperands = 36, // Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions. + FnVarFeature_Riscv64_NoTrailingSeqCstFence = 37, // Disable trailing fence for seq-cst store.. + FnVarFeature_Riscv64_OptimizedZeroStrideLoad = 38, // Optimized (perform fewer memory operations)zero-stride vector load. + FnVarFeature_Riscv64_PredictableSelectExpensive = 39, // Prefer likely predicted branches over selects. + FnVarFeature_Riscv64_PreferWInst = 40, // Prefer instructions with W suffix. + FnVarFeature_Riscv64_Relax = 41, // Enable Linker relaxation.. + FnVarFeature_Riscv64_ReserveX1 = 42, // Reserve X1. + FnVarFeature_Riscv64_ReserveX10 = 43, // Reserve X10. + FnVarFeature_Riscv64_ReserveX11 = 44, // Reserve X11. + FnVarFeature_Riscv64_ReserveX12 = 45, // Reserve X12. + FnVarFeature_Riscv64_ReserveX13 = 46, // Reserve X13. + FnVarFeature_Riscv64_ReserveX14 = 47, // Reserve X14. + FnVarFeature_Riscv64_ReserveX15 = 48, // Reserve X15. + FnVarFeature_Riscv64_ReserveX16 = 49, // Reserve X16. + FnVarFeature_Riscv64_ReserveX17 = 50, // Reserve X17. + FnVarFeature_Riscv64_ReserveX18 = 51, // Reserve X18. + FnVarFeature_Riscv64_ReserveX19 = 52, // Reserve X19. + FnVarFeature_Riscv64_ReserveX2 = 53, // Reserve X2. + FnVarFeature_Riscv64_ReserveX20 = 54, // Reserve X20. + FnVarFeature_Riscv64_ReserveX21 = 55, // Reserve X21. + FnVarFeature_Riscv64_ReserveX22 = 56, // Reserve X22. + FnVarFeature_Riscv64_ReserveX23 = 57, // Reserve X23. + FnVarFeature_Riscv64_ReserveX24 = 58, // Reserve X24. + FnVarFeature_Riscv64_ReserveX25 = 59, // Reserve X25. + FnVarFeature_Riscv64_ReserveX26 = 60, // Reserve X26. + FnVarFeature_Riscv64_ReserveX27 = 61, // Reserve X27. + FnVarFeature_Riscv64_ReserveX28 = 62, // Reserve X28. + FnVarFeature_Riscv64_ReserveX29 = 63, // Reserve X29. + FnVarFeature_Riscv64_ReserveX3 = 64, // Reserve X3. + FnVarFeature_Riscv64_ReserveX30 = 65, // Reserve X30. + FnVarFeature_Riscv64_ReserveX31 = 66, // Reserve X31. + FnVarFeature_Riscv64_ReserveX4 = 67, // Reserve X4. + FnVarFeature_Riscv64_ReserveX5 = 68, // Reserve X5. + FnVarFeature_Riscv64_ReserveX6 = 69, // Reserve X6. + FnVarFeature_Riscv64_ReserveX7 = 70, // Reserve X7. + FnVarFeature_Riscv64_ReserveX8 = 71, // Reserve X8. + FnVarFeature_Riscv64_ReserveX9 = 72, // Reserve X9. + FnVarFeature_Riscv64_Rva20s64 = 73, // RISC-V rva20s64 profile. + FnVarFeature_Riscv64_Rva20u64 = 74, // RISC-V rva20u64 profile. + FnVarFeature_Riscv64_Rva22s64 = 75, // RISC-V rva22s64 profile. + FnVarFeature_Riscv64_Rva22u64 = 76, // RISC-V rva22u64 profile. + FnVarFeature_Riscv64_Rvi20u32 = 77, // RISC-V rvi20u32 profile. + FnVarFeature_Riscv64_Rvi20u64 = 78, // RISC-V rvi20u64 profile. + FnVarFeature_Riscv64_SaveRestore = 79, // Enable save/restore.. + FnVarFeature_Riscv64_Shcounterenw = 80, // 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero). + FnVarFeature_Riscv64_Shgatpa = 81, // 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). + FnVarFeature_Riscv64_ShiftedZextwFusion = 82, // Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. + FnVarFeature_Riscv64_ShortForwardBranchOpt = 83, // Enable short forward branch optimization. + FnVarFeature_Riscv64_Shtvala = 84, // 'Shtvala' (htval provides all needed values). + FnVarFeature_Riscv64_Shvsatpa = 85, // 'Svsatpa' (vsatp supports all modes supported by satp). + FnVarFeature_Riscv64_Shvstvala = 86, // 'Shvstvala' (vstval provides all needed values). + FnVarFeature_Riscv64_Shvstvecd = 87, // 'Shvstvecd' (vstvec supports Direct mode). + FnVarFeature_Riscv64_Sifive7 = 88, // SiFive 7-Series processors. + FnVarFeature_Riscv64_Smaia = 89, // 'Smaia' (Advanced Interrupt Architecture Machine Level). + FnVarFeature_Riscv64_Smcdeleg = 90, // 'Smcdeleg' (Counter Delegation Machine Level). + FnVarFeature_Riscv64_Smcsrind = 91, // 'Smcsrind' (Indirect CSR Access Machine Level). + FnVarFeature_Riscv64_Smepmp = 92, // 'Smepmp' (Enhanced Physical Memory Protection). + FnVarFeature_Riscv64_Smstateen = 93, // 'Smstateen' (Machine-mode view of the state-enable extension). + FnVarFeature_Riscv64_Ssaia = 94, // 'Ssaia' (Advanced Interrupt Architecture Supervisor Level). + FnVarFeature_Riscv64_Ssccfg = 95, // 'Ssccfg' (Counter Configuration Supervisor Level). + FnVarFeature_Riscv64_Ssccptr = 96, // 'Ssccptr' (Main memory supports page table reads). + FnVarFeature_Riscv64_Sscofpmf = 97, // 'Sscofpmf' (Count Overflow and Mode-Based Filtering). + FnVarFeature_Riscv64_Sscounterenw = 98, // 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero). + FnVarFeature_Riscv64_Sscsrind = 99, // 'Sscsrind' (Indirect CSR Access Supervisor Level). + FnVarFeature_Riscv64_Ssstateen = 100, // 'Ssstateen' (Supervisor-mode view of the state-enable extension). + FnVarFeature_Riscv64_Ssstrict = 101, // 'Ssstrict' (No non-conforming extensions are present). + FnVarFeature_Riscv64_Sstc = 102, // 'Sstc' (Supervisor-mode timer interrupts). + FnVarFeature_Riscv64_Sstvala = 103, // 'Sstvala' (stval provides all needed values). + FnVarFeature_Riscv64_Sstvecd = 104, // 'Sstvecd' (stvec supports Direct mode). + FnVarFeature_Riscv64_Ssu64xl = 105, // 'Ssu64xl' (UXLEN=64 supported). + FnVarFeature_Riscv64_Svade = 106, // 'Svade' (Raise exceptions on improper A/D bits). + FnVarFeature_Riscv64_Svadu = 107, // 'Svadu' (Hardware A/D updates). + FnVarFeature_Riscv64_Svbare = 108, // 'Svbare' $(satp mode Bare supported). + FnVarFeature_Riscv64_Svinval = 109, // 'Svinval' (Fine-Grained Address-Translation Cache Invalidation). + FnVarFeature_Riscv64_Svnapot = 110, // 'Svnapot' (NAPOT Translation Contiguity). + FnVarFeature_Riscv64_Svpbmt = 111, // 'Svpbmt' (Page-Based Memory Types). + FnVarFeature_Riscv64_TaggedGlobals = 112, // Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. + FnVarFeature_Riscv64_UnalignedScalarMem = 113, // Has reasonably performant unaligned scalar loads and stores. + FnVarFeature_Riscv64_UnalignedVectorMem = 114, // Has reasonably performant unaligned vector loads and stores. + FnVarFeature_Riscv64_UsePostraScheduler = 115, // Schedule again after register allocation. + FnVarFeature_Riscv64_V = 116, // 'V' (Vector Extension for Application Processors). + FnVarFeature_Riscv64_VentanaVeyron = 117, // Ventana Veyron-Series processors. + FnVarFeature_Riscv64_Xcvalu = 118, // 'XCValu' (CORE-V ALU Operations). + FnVarFeature_Riscv64_Xcvbi = 119, // 'XCVbi' (CORE-V Immediate Branching). + FnVarFeature_Riscv64_Xcvbitmanip = 120, // 'XCVbitmanip' (CORE-V Bit Manipulation). + FnVarFeature_Riscv64_Xcvelw = 121, // 'XCVelw' (CORE-V Event Load Word). + FnVarFeature_Riscv64_Xcvmac = 122, // 'XCVmac' (CORE-V Multiply-Accumulate). + FnVarFeature_Riscv64_Xcvmem = 123, // 'XCVmem' (CORE-V Post-incrementing Load & Store). + FnVarFeature_Riscv64_Xcvsimd = 124, // 'XCVsimd' (CORE-V SIMD ALU). + FnVarFeature_Riscv64_Xsfcease = 125, // 'XSfcease' (SiFive sf.cease Instruction). + FnVarFeature_Riscv64_Xsfvcp = 126, // 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions). + FnVarFeature_Riscv64_Xsfvfnrclipxfqf = 127, // 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions). + FnVarFeature_Riscv64_Xsfvfwmaccqqq = 128, // 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4)). + FnVarFeature_Riscv64_Xsfvqmaccdod = 129, // 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)). + FnVarFeature_Riscv64_Xsfvqmaccqoq = 130, // 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)). + FnVarFeature_Riscv64_Xsifivecdiscarddlone = 131, // 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). + FnVarFeature_Riscv64_Xsifivecflushdlone = 132, // 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). + FnVarFeature_Riscv64_Xtheadba = 133, // 'XTHeadBa' (T-Head address calculation instructions). + FnVarFeature_Riscv64_Xtheadbb = 134, // 'XTHeadBb' (T-Head basic bit-manipulation instructions). + FnVarFeature_Riscv64_Xtheadbs = 135, // 'XTHeadBs' (T-Head single-bit instructions). + FnVarFeature_Riscv64_Xtheadcmo = 136, // 'XTHeadCmo' (T-Head cache management instructions). + FnVarFeature_Riscv64_Xtheadcondmov = 137, // 'XTHeadCondMov' (T-Head conditional move instructions). + FnVarFeature_Riscv64_Xtheadfmemidx = 138, // 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations). + FnVarFeature_Riscv64_Xtheadmac = 139, // 'XTHeadMac' (T-Head Multiply-Accumulate Instructions). + FnVarFeature_Riscv64_Xtheadmemidx = 140, // 'XTHeadMemIdx' (T-Head Indexed Memory Operations). + FnVarFeature_Riscv64_Xtheadmempair = 141, // 'XTHeadMemPair' (T-Head two-GPR Memory Operations). + FnVarFeature_Riscv64_Xtheadsync = 142, // 'XTHeadSync' (T-Head multicore synchronization instructions). + FnVarFeature_Riscv64_Xtheadvdot = 143, // 'XTHeadVdot' (T-Head Vector Extensions for Dot). + FnVarFeature_Riscv64_Xventanacondops = 144, // 'XVentanaCondOps' (Ventana Conditional Ops). + FnVarFeature_Riscv64_Xwchc = 145, // 'Xwchc' (WCH/QingKe additional compressed opcodes). + FnVarFeature_Riscv64_Za128rs = 146, // 'Za128rs' (Reservation Set Size of at Most 128 Bytes). + FnVarFeature_Riscv64_Za64rs = 147, // 'Za64rs' (Reservation Set Size of at Most 64 Bytes). + FnVarFeature_Riscv64_Zaamo = 148, // 'Zaamo' (Atomic Memory Operations). + FnVarFeature_Riscv64_Zabha = 149, // 'Zabha' (Byte and Halfword Atomic Memory Operations). + FnVarFeature_Riscv64_Zalrsc = 150, // 'Zalrsc' (Load-Reserved/Store-Conditional). + FnVarFeature_Riscv64_Zama16b = 151, // 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs). + FnVarFeature_Riscv64_Zawrs = 152, // 'Zawrs' (Wait on Reservation Set). + FnVarFeature_Riscv64_Zba = 153, // 'Zba' (Address Generation Instructions). + FnVarFeature_Riscv64_Zbb = 154, // 'Zbb' (Basic Bit-Manipulation). + FnVarFeature_Riscv64_Zbc = 155, // 'Zbc' (Carry-Less Multiplication). + FnVarFeature_Riscv64_Zbkb = 156, // 'Zbkb' (Bitmanip instructions for Cryptography). + FnVarFeature_Riscv64_Zbkc = 157, // 'Zbkc' (Carry-less multiply instructions for Cryptography). + FnVarFeature_Riscv64_Zbkx = 158, // 'Zbkx' (Crossbar permutation instructions). + FnVarFeature_Riscv64_Zbs = 159, // 'Zbs' (Single-Bit Instructions). + FnVarFeature_Riscv64_Zca = 160, // 'Zca' (part of the C extension, excluding compressed floating point loads/stores). + FnVarFeature_Riscv64_Zcb = 161, // 'Zcb' (Compressed basic bit manipulation instructions). + FnVarFeature_Riscv64_Zcd = 162, // 'Zcd' (Compressed Double-Precision Floating-Point Instructions). + FnVarFeature_Riscv64_Zce = 163, // 'Zce' (Compressed extensions for microcontrollers). + FnVarFeature_Riscv64_Zcf = 164, // 'Zcf' (Compressed Single-Precision Floating-Point Instructions). + FnVarFeature_Riscv64_Zcmop = 165, // 'Zcmop' (Compressed May-Be-Operations). + FnVarFeature_Riscv64_Zcmp = 166, // 'Zcmp' (sequenced instructions for code-size reduction). + FnVarFeature_Riscv64_Zcmt = 167, // 'Zcmt' (table jump instructions for code-size reduction). + FnVarFeature_Riscv64_Zdinx = 168, // 'Zdinx' (Double in Integer). + FnVarFeature_Riscv64_ZexthFusion = 169, // Enable SLLI+SRLI to be fused to zero extension of halfword. + FnVarFeature_Riscv64_ZextwFusion = 170, // Enable SLLI+SRLI to be fused to zero extension of word. + FnVarFeature_Riscv64_Zfa = 171, // 'Zfa' (Additional Floating-Point). + FnVarFeature_Riscv64_Zfbfmin = 172, // 'Zfbfmin' (Scalar BF16 Converts). + FnVarFeature_Riscv64_Zfh = 173, // 'Zfh' (Half-Precision Floating-Point). + FnVarFeature_Riscv64_Zfhmin = 174, // 'Zfhmin' (Half-Precision Floating-Point Minimal). + FnVarFeature_Riscv64_Zfinx = 175, // 'Zfinx' (Float in Integer). + FnVarFeature_Riscv64_Zhinx = 176, // 'Zhinx' (Half Float in Integer). + FnVarFeature_Riscv64_Zhinxmin = 177, // 'Zhinxmin' (Half Float in Integer Minimal). + FnVarFeature_Riscv64_Zic64b = 178, // 'Zic64b' (Cache Block Size Is 64 Bytes). + FnVarFeature_Riscv64_Zicbom = 179, // 'Zicbom' (Cache-Block Management Instructions). + FnVarFeature_Riscv64_Zicbop = 180, // 'Zicbop' (Cache-Block Prefetch Instructions). + FnVarFeature_Riscv64_Zicboz = 181, // 'Zicboz' (Cache-Block Zero Instructions). + FnVarFeature_Riscv64_Ziccamoa = 182, // 'Ziccamoa' (Main Memory Supports All Atomics in A). + FnVarFeature_Riscv64_Ziccif = 183, // 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement). + FnVarFeature_Riscv64_Zicclsm = 184, // 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores). + FnVarFeature_Riscv64_Ziccrse = 185, // 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences). + FnVarFeature_Riscv64_Zicntr = 186, // 'Zicntr' (Base Counters and Timers). + FnVarFeature_Riscv64_Zicond = 187, // 'Zicond' (Integer Conditional Operations). + FnVarFeature_Riscv64_Zicsr = 188, // 'zicsr' (CSRs). + FnVarFeature_Riscv64_Zifencei = 189, // 'Zifencei' (fence.i). + FnVarFeature_Riscv64_Zihintntl = 190, // 'Zihintntl' (Non-Temporal Locality Hints). + FnVarFeature_Riscv64_Zihintpause = 191, // 'Zihintpause' (Pause Hint). + FnVarFeature_Riscv64_Zihpm = 192, // 'Zihpm' (Hardware Performance Counters). + FnVarFeature_Riscv64_Zimop = 193, // 'Zimop' (May-Be-Operations). + FnVarFeature_Riscv64_Zk = 194, // 'Zk' (Standard scalar cryptography extension). + FnVarFeature_Riscv64_Zkn = 195, // 'Zkn' (NIST Algorithm Suite). + FnVarFeature_Riscv64_Zknd = 196, // 'Zknd' (NIST Suite: AES Decryption). + FnVarFeature_Riscv64_Zkne = 197, // 'Zkne' (NIST Suite: AES Encryption). + FnVarFeature_Riscv64_Zknh = 198, // 'Zknh' (NIST Suite: Hash Function Instructions). + FnVarFeature_Riscv64_Zkr = 199, // 'Zkr' (Entropy Source Extension). + FnVarFeature_Riscv64_Zks = 200, // 'Zks' (ShangMi Algorithm Suite). + FnVarFeature_Riscv64_Zksed = 201, // 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions). + FnVarFeature_Riscv64_Zksh = 202, // 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions). + FnVarFeature_Riscv64_Zkt = 203, // 'Zkt' (Data Independent Execution Latency). + FnVarFeature_Riscv64_Zmmul = 204, // 'Zmmul' (Integer Multiplication). + FnVarFeature_Riscv64_Ztso = 205, // 'Ztso' (Memory Model + FnVarFeature_Riscv64_Zvbb = 206, // 'Zvbb' (Vector basic bit-manipulation instructions). + FnVarFeature_Riscv64_Zvbc = 207, // 'Zvbc' (Vector Carryless Multiplication). + FnVarFeature_Riscv64_Zve32f = 208, // 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension). + FnVarFeature_Riscv64_Zve32x = 209, // 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW). + FnVarFeature_Riscv64_Zve64d = 210, // 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension). + FnVarFeature_Riscv64_Zve64f = 211, // 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension). + FnVarFeature_Riscv64_Zve64x = 212, // 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW). + FnVarFeature_Riscv64_Zvfbfmin = 213, // 'Zvbfmin' (Vector BF16 Converts). + FnVarFeature_Riscv64_Zvfbfwma = 214, // 'Zvfbfwma' (Vector BF16 widening mul-add). + FnVarFeature_Riscv64_Zvfh = 215, // 'Zvfh' (Vector Half-Precision Floating-Point). + FnVarFeature_Riscv64_Zvfhmin = 216, // 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal). + FnVarFeature_Riscv64_Zvkb = 217, // 'Zvkb' (Vector Bit-manipulation used in Cryptography). + FnVarFeature_Riscv64_Zvkg = 218, // 'Zvkg' (Vector GCM instructions for Cryptography). + FnVarFeature_Riscv64_Zvkn = 219, // 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'). + FnVarFeature_Riscv64_Zvknc = 220, // 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc'). + FnVarFeature_Riscv64_Zvkned = 221, // 'Zvkned' (Vector AES Encryption & Decryption (Single Round)). + FnVarFeature_Riscv64_Zvkng = 222, // 'zvkng' (shorthand for 'Zvkn' and 'Zvkg'). + FnVarFeature_Riscv64_Zvknha = 223, // 'Zvknha' (Vector SHA-2 (SHA-256 only)). + FnVarFeature_Riscv64_Zvknhb = 224, // 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)). + FnVarFeature_Riscv64_Zvks = 225, // 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'). + FnVarFeature_Riscv64_Zvksc = 226, // 'Zvksc' (shorthand for 'Zvks' and 'Zvbc'). + FnVarFeature_Riscv64_Zvksed = 227, // 'Zvksed' (SM4 Block Cipher Instructions). + FnVarFeature_Riscv64_Zvksg = 228, // 'Zvksg' (shorthand for 'Zvks' and 'Zvkg'). + FnVarFeature_Riscv64_Zvksh = 229, // 'Zvksh' (SM3 Hash Function Instructions). + FnVarFeature_Riscv64_Zvkt = 230, // 'Zvkt' (Vector Data-Independent Execution Latency). + FnVarFeature_Riscv64_Zvl1024b = 231, // 'Zvl' (Minimum Vector Length) 1024. + FnVarFeature_Riscv64_Zvl128b = 232, // 'Zvl' (Minimum Vector Length) 128. + FnVarFeature_Riscv64_Zvl16384b = 233, // 'Zvl' (Minimum Vector Length) 16384. + FnVarFeature_Riscv64_Zvl2048b = 234, // 'Zvl' (Minimum Vector Length) 2048. + FnVarFeature_Riscv64_Zvl256b = 235, // 'Zvl' (Minimum Vector Length) 256. + FnVarFeature_Riscv64_Zvl32768b = 236, // 'Zvl' (Minimum Vector Length) 32768. + FnVarFeature_Riscv64_Zvl32b = 237, // 'Zvl' (Minimum Vector Length) 32. + FnVarFeature_Riscv64_Zvl4096b = 238, // 'Zvl' (Minimum Vector Length) 4096. + FnVarFeature_Riscv64_Zvl512b = 239, // 'Zvl' (Minimum Vector Length) 512. + FnVarFeature_Riscv64_Zvl64b = 240, // 'Zvl' (Minimum Vector Length) 64. + FnVarFeature_Riscv64_Zvl65536b = 241, // 'Zvl' (Minimum Vector Length) 65536. + FnVarFeature_Riscv64_Zvl8192b = 242, // 'Zvl' (Minimum Vector Length) 8192. + FnVarFeature_Riscv64_Max = 0x7fffffff, +} FnVarFeature_Riscv64; + +// Architecture Categories + +typedef enum FnVarArchCategory_ { + FnVarArchCategory_Unknown = 0, // Unknown category + FnVarArchCategory_Cpu = 1, // Central processing unit + FnVarArchCategory_Gpu = 2, // Graphics processing unit + FnVarArchCategory_Npu = 3, // Neural processing unit (AI accelerator) + FnVarArchCategory_Max = 0x7fffffff, +} FnVarArchCategory; + +// Architecture Families + +typedef enum FnVarArchFamily_Unknown_ { + FnVarArchFamily_Unknown_Generic = 0, // Generic family + FnVarArchFamily_Unknown_Max = 0x7fffffff, +} FnVarArchFamily_Unknown; + +typedef enum FnVarArchFamily_Cpu_ { + FnVarArchFamily_Cpu_Generic = 0, // Generic CPU + FnVarArchFamily_Cpu_Intel = 1, // Intel main line of CPUs + FnVarArchFamily_Cpu_IntelAtom = 2, // Intel Atom/Low-power line of CPUs + FnVarArchFamily_Cpu_Amd = 3, // AMD CPU + FnVarArchFamily_Cpu_ArmA = 4, // ARM Cortex-A CPU family + FnVarArchFamily_Cpu_ArmM = 5, // ARM Cortex-M CPU family + FnVarArchFamily_Cpu_ArmR = 6, // ARM Cortex-R CPU family + FnVarArchFamily_Cpu_CodasipLp = 7, // Codasip low-power cores + FnVarArchFamily_Cpu_CodasipHp = 8, // Codasip high-performance cores + FnVarArchFamily_Cpu_CodasipAp = 9, // Codasip application cores + FnVarArchFamily_Cpu_SifiveE2 = 10, // SiFive Essential 2-series + FnVarArchFamily_Cpu_SifiveE6 = 11, // SiFive Essential 6-series + FnVarArchFamily_Cpu_SifiveE7 = 12, // SiFive Essential 7-series + FnVarArchFamily_Cpu_SifiveX200 = 13, // SiFive Essential X200 Series + FnVarArchFamily_Cpu_SifiveX300 = 14, // SiFive Essential X300 Series + FnVarArchFamily_Cpu_SifiveXm = 15, // SiFive Essential XM Series + FnVarArchFamily_Cpu_SifiveP400 = 16, // SiFive Essential P400 Series + FnVarArchFamily_Cpu_SifiveP500 = 17, // SiFive Essential P500 Series + FnVarArchFamily_Cpu_SifiveP600 = 18, // SiFive Essential P600 Series + FnVarArchFamily_Cpu_SifiveP800 = 19, // SiFive Essential P800 Series + FnVarArchFamily_Cpu_SifiveE6a = 20, // SiFive Essential E6-A Series + FnVarArchFamily_Cpu_SifiveE7a = 21, // SiFive Essential E7-A Series + FnVarArchFamily_Cpu_SifiveS7a = 22, // SiFive Essential S7-A Series + FnVarArchFamily_Cpu_Max = 0x7fffffff, +} FnVarArchFamily_Cpu; + +typedef enum FnVarArchFamily_Gpu_ { + FnVarArchFamily_Gpu_Generic = 0, // Generic GPU + FnVarArchFamily_Gpu_Intel = 1, // Intel GPU + FnVarArchFamily_Gpu_Amd = 2, // AMD GPU + FnVarArchFamily_Gpu_Nvidia = 3, // NVIDIA GPU + FnVarArchFamily_Gpu_Max = 0x7fffffff, +} FnVarArchFamily_Gpu; + +typedef enum FnVarArchFamily_Npu_ { + FnVarArchFamily_Npu_Generic = 0, // Generic NPU + FnVarArchFamily_Npu_Intel = 1, // Intel NPU + FnVarArchFamily_Npu_AmdXdna = 2, // AMD XDNA NPU + FnVarArchFamily_Npu_Max = 0x7fffffff, +} FnVarArchFamily_Npu; + +// Architectures + +typedef enum FnVarArch_Unknown_Generic_ { + FnVarArch_Unknown_Generic_Any = 0, // Any architecture + FnVarArch_Unknown_Generic_Max = 0x7fffffff, +} FnVarArch_Unknown_Generic; + +typedef enum FnVarArch_Cpu_Generic_ { + FnVarArch_Cpu_Generic_Any = 0, // Any CPU + FnVarArch_Cpu_Generic_Max = 0x7fffffff, +} FnVarArch_Cpu_Generic; + +typedef enum FnVarArch_Cpu_Intel_ { + FnVarArch_Cpu_Intel_Any = 0, // Any Intel CPU + FnVarArch_Cpu_Intel_Nhm = 1, // Intel Nehalem microarchitecture + FnVarArch_Cpu_Intel_Wsm = 2, // Intel Westmere microarchitecture + FnVarArch_Cpu_Intel_Sdb = 3, // Intel Sandy Bridge microarchitecture + FnVarArch_Cpu_Intel_Ivb = 4, // Intel Ivy Bridge microarchitecture + FnVarArch_Cpu_Intel_Hsw = 5, // Intel Haswell microarchitecture + FnVarArch_Cpu_Intel_Bdw = 6, // Intel Broadwell microarchitecture + FnVarArch_Cpu_Intel_Skl = 7, // Intel Skylake microarchitecture + FnVarArch_Cpu_Intel_Pmc = 8, // Intel Palm Cove microarchitecture + FnVarArch_Cpu_Intel_Snc = 9, // Intel Sunny Cove microarchitecture + FnVarArch_Cpu_Intel_Wlc = 10, // Intel Willow Cove microarchitecture + FnVarArch_Cpu_Intel_Cpc = 11, // Intel Cypress Cove microarchitecture + FnVarArch_Cpu_Intel_Gdc = 12, // Intel Golden Cove microarchitecture + FnVarArch_Cpu_Intel_Rpc = 13, // Intel Raptor Cove microarchitecture + FnVarArch_Cpu_Intel_Rdc = 14, // Intel Redwood Cove microarchitecture + FnVarArch_Cpu_Intel_Lnc = 15, // Intel Lion Cove microarchitecture + FnVarArch_Cpu_Intel_Max = 0x7fffffff, +} FnVarArch_Cpu_Intel; + +typedef enum FnVarArch_Cpu_IntelAtom_ { + FnVarArch_Cpu_IntelAtom_Any = 0, // Any Intel Atom/Low-power CPU + FnVarArch_Cpu_IntelAtom_Bnl = 1, // Intel Bonnell microarchitecture + FnVarArch_Cpu_IntelAtom_Slw = 2, // Intel Saltwell microarchitecture + FnVarArch_Cpu_IntelAtom_Svm = 3, // Intel Silvermont microarchitecture + FnVarArch_Cpu_IntelAtom_Aim = 4, // Intel Airmont microarchitecture + FnVarArch_Cpu_IntelAtom_Gdm = 5, // Intel Goldmont microarchitecture + FnVarArch_Cpu_IntelAtom_GdmP = 6, // Intel Goldmont Plus microarchitecture + FnVarArch_Cpu_IntelAtom_Trm = 7, // Intel Tremont microarchitecture + FnVarArch_Cpu_IntelAtom_Gcm = 8, // Intel Gracemont microarchitecture + FnVarArch_Cpu_IntelAtom_Csm = 9, // Intel Crestmont microarchitecture + FnVarArch_Cpu_IntelAtom_Skm = 10, // Intel Skymont microarchitecture + FnVarArch_Cpu_IntelAtom_Max = 0x7fffffff, +} FnVarArch_Cpu_IntelAtom; + +typedef enum FnVarArch_Cpu_Amd_ { + FnVarArch_Cpu_Amd_Any = 0, // Any AMD CPU + FnVarArch_Cpu_Amd_Zen = 1, // AMD Zen microarchitecture + FnVarArch_Cpu_Amd_Zenp = 2, // AMD Zen+ microarchitecture + FnVarArch_Cpu_Amd_Zen2 = 3, // AMD Zen2 microarchitecture + FnVarArch_Cpu_Amd_Zen3 = 4, // AMD Zen3 microarchitecture + FnVarArch_Cpu_Amd_Zen3p = 5, // AMD Zen3+ microarchitecture + FnVarArch_Cpu_Amd_Zen4 = 6, // AMD Zen4 microarchitecture + FnVarArch_Cpu_Amd_Zen4c = 7, // AMD Zen4c microarchitecture + FnVarArch_Cpu_Amd_Zen5 = 8, // AMD Zen5 microarchitecture + FnVarArch_Cpu_Amd_Zen5c = 9, // AMD Zen5c microarchitecture + FnVarArch_Cpu_Amd_Max = 0x7fffffff, +} FnVarArch_Cpu_Amd; + +typedef enum FnVarArch_Cpu_ArmA_ { + FnVarArch_Cpu_ArmA_Any = 0, // Any CPU microarchitecture from the ARM Cortex-A family + FnVarArch_Cpu_ArmA_A8 = 1, // ARM Cortex-A8 (32-bit) + FnVarArch_Cpu_ArmA_A9 = 2, // ARM Cortex-A9 (32-bit) + FnVarArch_Cpu_ArmA_A5 = 3, // ARM Cortex-A5 (32-bit) + FnVarArch_Cpu_ArmA_A15 = 4, // ARM Cortex-A15 (32-bit) + FnVarArch_Cpu_ArmA_A7 = 5, // ARM Cortex-A7 (32-bit) + FnVarArch_Cpu_ArmA_A53 = 6, // ARM Cortex-A53 (32/64-bit) + FnVarArch_Cpu_ArmA_A57 = 7, // ARM Cortex-A57 (32/64-bit) + FnVarArch_Cpu_ArmA_A12 = 8, // ARM Cortex-A12 (32-bit) + FnVarArch_Cpu_ArmA_A17 = 9, // ARM Cortex-A17 (32-bit) + FnVarArch_Cpu_ArmA_A32 = 10, // ARM Cortex-A32 (32-bit) + FnVarArch_Cpu_ArmA_A34 = 11, // ARM Cortex-A34 (64-bit) + FnVarArch_Cpu_ArmA_A73 = 12, // ARM Cortex-A73 (32/64-bit) + FnVarArch_Cpu_ArmA_A55 = 13, // ARM Cortex-A55 (32/64-bit) + FnVarArch_Cpu_ArmA_A75 = 14, // ARM Cortex-A75 (32/64-bit) + FnVarArch_Cpu_ArmA_A65 = 15, // ARM Cortex-A65 (64-bit) + FnVarArch_Cpu_ArmA_A76 = 16, // ARM Cortex-A76 (32/64-bit) + FnVarArch_Cpu_ArmA_A77 = 17, // ARM Cortex-A77 (32/64-bit) + FnVarArch_Cpu_ArmA_A78 = 18, // ARM Cortex-A78 (32/64-bit) + FnVarArch_Cpu_ArmA_A78ae = 19, // ARM Cortex-A78AE (32/64-bit) + FnVarArch_Cpu_ArmA_A510 = 20, // ARM Cortex-A510 (64-bit) + FnVarArch_Cpu_ArmA_A710 = 21, // ARM Cortex-A710 (32/64-bit) + FnVarArch_Cpu_ArmA_A510r = 22, // ARM Cortex-A510 (refresh) (32/64-bit) + FnVarArch_Cpu_ArmA_A715 = 23, // ARM Cortex-A715 (64-bit) + FnVarArch_Cpu_ArmA_A520 = 24, // ARM Cortex-A520 (64-bit) + FnVarArch_Cpu_ArmA_A720 = 25, // ARM Cortex-A720 (64-bit) + FnVarArch_Cpu_ArmA_A520ae = 26, // ARM Cortex-A520AE (64-bit) + FnVarArch_Cpu_ArmA_A720ae = 27, // ARM Cortex-A720AE (64-bit) + FnVarArch_Cpu_ArmA_A725 = 28, // ARM Cortex-A725 (64-bit) + FnVarArch_Cpu_ArmA_A320 = 29, // ARM Cortex-A320 (64-bit) + FnVarArch_Cpu_ArmA_A530 = 30, // ARM Cortex-A530 (64-bit) + FnVarArch_Cpu_ArmA_A730 = 31, // ARM Cortex-A730 (64-bit) + FnVarArch_Cpu_ArmA_Max = 0x7fffffff, +} FnVarArch_Cpu_ArmA; + +typedef enum FnVarArch_Cpu_ArmM_ { + FnVarArch_Cpu_ArmM_Any = 0, // Any CPU microarchitecture from the ARM Cortex-M family + FnVarArch_Cpu_ArmM_M3 = 1, // ARM Cortex-M3 + FnVarArch_Cpu_ArmM_M1 = 2, // ARM Cortex-M1 + FnVarArch_Cpu_ArmM_M0 = 3, // ARM Cortex-M0 + FnVarArch_Cpu_ArmM_M4 = 4, // ARM Cortex-M4 + FnVarArch_Cpu_ArmM_M0p = 5, // ARM Cortex-M0+ + FnVarArch_Cpu_ArmM_M7 = 6, // ARM Cortex-M7 + FnVarArch_Cpu_ArmM_M23 = 7, // ARM Cortex-M23 + FnVarArch_Cpu_ArmM_M33 = 8, // ARM Cortex-M33 + FnVarArch_Cpu_ArmM_M35p = 9, // ARM Cortex-M35P + FnVarArch_Cpu_ArmM_M55 = 10, // ARM Cortex-M55 + FnVarArch_Cpu_ArmM_M85 = 11, // ARM Cortex-M85 + FnVarArch_Cpu_ArmM_M52 = 12, // ARM Cortex-M52 + FnVarArch_Cpu_ArmM_Max = 0x7fffffff, +} FnVarArch_Cpu_ArmM; + +typedef enum FnVarArch_Cpu_ArmR_ { + FnVarArch_Cpu_ArmR_Any = 0, // Any CPU microarchitecture from the ARM Cortex-R family + FnVarArch_Cpu_ArmR_R4 = 1, // ARM Cortex-R4 (32-bit) + FnVarArch_Cpu_ArmR_R5 = 2, // ARM Cortex-R5 (32-bit) + FnVarArch_Cpu_ArmR_R7 = 3, // ARM Cortex-R7 (32-bit) + FnVarArch_Cpu_ArmR_R8 = 4, // ARM Cortex-R8 (32-bit) + FnVarArch_Cpu_ArmR_R52 = 5, // ARM Cortex-R52 (32-bit) + FnVarArch_Cpu_ArmR_R82 = 6, // ARM Cortex-R82 (64-bit) + FnVarArch_Cpu_ArmR_R52p = 7, // ARM Cortex-R52+ (32-bit) + FnVarArch_Cpu_ArmR_Max = 0x7fffffff, +} FnVarArch_Cpu_ArmR; + +typedef enum FnVarArch_Cpu_CodasipLp_ { + FnVarArch_Cpu_CodasipLp_Any = 0, // Any Codasip low-power CPU + FnVarArch_Cpu_CodasipLp_L110 = 1, // Codasip L110 + FnVarArch_Cpu_CodasipLp_L150 = 2, // Codasip L150 + FnVarArch_Cpu_CodasipLp_L31 = 3, // Codasip L31 + FnVarArch_Cpu_CodasipLp_Max = 0x7fffffff, +} FnVarArch_Cpu_CodasipLp; + +typedef enum FnVarArch_Cpu_CodasipHp_ { + FnVarArch_Cpu_CodasipHp_Any = 0, // Any Codasip high-performance CPU + FnVarArch_Cpu_CodasipHp_L730 = 1, // Codasip L730 + FnVarArch_Cpu_CodasipHp_Max = 0x7fffffff, +} FnVarArch_Cpu_CodasipHp; + +typedef enum FnVarArch_Cpu_CodasipAp_ { + FnVarArch_Cpu_CodasipAp_Any = 0, // Any Codasip application CPU + FnVarArch_Cpu_CodasipAp_A70 = 1, // Codasip A70 + FnVarArch_Cpu_CodasipAp_A730 = 2, // Codasip A730 + FnVarArch_Cpu_CodasipAp_X730 = 3, // Codasip X730 + FnVarArch_Cpu_CodasipAp_Max = 0x7fffffff, +} FnVarArch_Cpu_CodasipAp; + +typedef enum FnVarArch_Cpu_SifiveE2_ { + FnVarArch_Cpu_SifiveE2_Any = 0, // Any SiFive Essential 2-series CPU + FnVarArch_Cpu_SifiveE2_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveE2; + +typedef enum FnVarArch_Cpu_SifiveE6_ { + FnVarArch_Cpu_SifiveE6_Any = 0, // Any SiFive Essential 6-series CPU + FnVarArch_Cpu_SifiveE6_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveE6; + +typedef enum FnVarArch_Cpu_SifiveE7_ { + FnVarArch_Cpu_SifiveE7_Any = 0, // Any SiFive Essential 7-series CPU + FnVarArch_Cpu_SifiveE7_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveE7; + +typedef enum FnVarArch_Cpu_SifiveX200_ { + FnVarArch_Cpu_SifiveX200_Any = 0, // Any SiFive Essential X200 Series CPU + FnVarArch_Cpu_SifiveX200_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveX200; + +typedef enum FnVarArch_Cpu_SifiveX300_ { + FnVarArch_Cpu_SifiveX300_Any = 0, // Any SiFive Essential X300 Series CPU + FnVarArch_Cpu_SifiveX300_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveX300; + +typedef enum FnVarArch_Cpu_SifiveXm_ { + FnVarArch_Cpu_SifiveXm_Any = 0, // Any SiFive Essential XM Series CPU + FnVarArch_Cpu_SifiveXm_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveXm; + +typedef enum FnVarArch_Cpu_SifiveP400_ { + FnVarArch_Cpu_SifiveP400_Any = 0, // Any SiFive Essential P400 Series CPU + FnVarArch_Cpu_SifiveP400_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveP400; + +typedef enum FnVarArch_Cpu_SifiveP500_ { + FnVarArch_Cpu_SifiveP500_Any = 0, // Any SiFive Essential P500 Series CPU + FnVarArch_Cpu_SifiveP500_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveP500; + +typedef enum FnVarArch_Cpu_SifiveP600_ { + FnVarArch_Cpu_SifiveP600_Any = 0, // Any SiFive Essential P600 Series CPU + FnVarArch_Cpu_SifiveP600_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveP600; + +typedef enum FnVarArch_Cpu_SifiveP800_ { + FnVarArch_Cpu_SifiveP800_Any = 0, // Any SiFive Essential P800 Series CPU + FnVarArch_Cpu_SifiveP800_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveP800; + +typedef enum FnVarArch_Cpu_SifiveE6a_ { + FnVarArch_Cpu_SifiveE6a_Any = 0, // Any SiFive Essential E6-A Series CPU + FnVarArch_Cpu_SifiveE6a_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveE6a; + +typedef enum FnVarArch_Cpu_SifiveE7a_ { + FnVarArch_Cpu_SifiveE7a_Any = 0, // Any SiFive Essential E7-A Series CPU + FnVarArch_Cpu_SifiveE7a_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveE7a; + +typedef enum FnVarArch_Cpu_SifiveS7a_ { + FnVarArch_Cpu_SifiveS7a_Any = 0, // Any SiFive Essential S7-A Series CPU + FnVarArch_Cpu_SifiveS7a_Max = 0x7fffffff, +} FnVarArch_Cpu_SifiveS7a; + +typedef enum FnVarArch_Gpu_Generic_ { + FnVarArch_Gpu_Generic_Any = 0, // Any GPU + FnVarArch_Gpu_Generic_Max = 0x7fffffff, +} FnVarArch_Gpu_Generic; + +typedef enum FnVarArch_Gpu_Intel_ { + FnVarArch_Gpu_Intel_Any = 0, // Any Intel GPU + FnVarArch_Gpu_Intel_Bdw = 1, // Broadwell Intel graphics architecture + FnVarArch_Gpu_Intel_V800 = 1, // Broadwell Intel graphics architecture + FnVarArch_Gpu_Intel_Skl = 2, // Skylake Intel graphics architecture + FnVarArch_Gpu_Intel_V909 = 2, // Skylake Intel graphics architecture + FnVarArch_Gpu_Intel_Kbl = 3, // Kaby Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V919 = 3, // Kaby Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Cfl = 4, // Coffee Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V929 = 4, // Coffee Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Apl = 5, // Apollo Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V930 = 5, // Apollo Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Bxt = 5, // Broxton Intel graphics architecture + FnVarArch_Gpu_Intel_Glk = 6, // Gemini Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V940 = 6, // Gemini Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Whl = 7, // Whiskey Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V950 = 7, // Whiskey Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Aml = 8, // Amber Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V960 = 8, // Amber Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Cml = 9, // Comet Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V970 = 9, // Comet Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Icllp = 10, // Ice Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Icl = 10, // Ice Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V1100 = 10, // Ice Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Ehl = 11, // Elkhart Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V1120 = 11, // Elkhart Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Jsl = 11, // Jasper Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Tgllp = 12, // Tiger Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Tgl = 12, // Tiger Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V1200 = 12, // Tiger Lake Intel graphics architecture + FnVarArch_Gpu_Intel_Rkl = 13, // Rocket Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V1210 = 13, // Rocket Lake Intel graphics architecture + FnVarArch_Gpu_Intel_AdlS = 14, // Alder Lake S Intel graphics architecture + FnVarArch_Gpu_Intel_V1220 = 14, // Alder Lake S Intel graphics architecture + FnVarArch_Gpu_Intel_RplS = 14, // Raptor Lake Intel graphics architecture + FnVarArch_Gpu_Intel_AdlP = 15, // Alder Lake P Intel graphics architecture + FnVarArch_Gpu_Intel_V1230 = 15, // Alder Lake P Intel graphics architecture + FnVarArch_Gpu_Intel_AdlN = 16, // Alder Lake N Intel graphics architecture + FnVarArch_Gpu_Intel_V1240 = 16, // Alder Lake N Intel graphics architecture + FnVarArch_Gpu_Intel_Dg1 = 17, // DG1 Intel graphics architecture + FnVarArch_Gpu_Intel_V12100 = 17, // DG1 Intel graphics architecture + FnVarArch_Gpu_Intel_AcmG10 = 18, // Alchemist G10 Intel graphics architecture + FnVarArch_Gpu_Intel_Dg2G10 = 18, // Alchemist G10 Intel graphics architecture + FnVarArch_Gpu_Intel_V12558 = 18, // Alchemist G10 Intel graphics architecture + FnVarArch_Gpu_Intel_AcmG11 = 19, // Alchemist G11 Intel graphics architecture + FnVarArch_Gpu_Intel_Dg2G11 = 19, // Alchemist G11 Intel graphics architecture + FnVarArch_Gpu_Intel_V12565 = 19, // Alchemist G11 Intel graphics architecture + FnVarArch_Gpu_Intel_AcmG12 = 20, // Alchemist G12 Intel graphics architecture + FnVarArch_Gpu_Intel_Dg2G12 = 20, // Alchemist G12 Intel graphics architecture + FnVarArch_Gpu_Intel_V12570 = 20, // Alchemist G12 Intel graphics architecture + FnVarArch_Gpu_Intel_Pvc = 21, // Ponte Vecchio Intel graphics architecture + FnVarArch_Gpu_Intel_V12607 = 21, // Ponte Vecchio Intel graphics architecture + FnVarArch_Gpu_Intel_PvcVg = 22, // Ponte Vecchio VG Intel graphics architecture + FnVarArch_Gpu_Intel_V12617 = 22, // Ponte Vecchio VG Intel graphics architecture + FnVarArch_Gpu_Intel_MtlU = 23, // Meteor Lake U Intel graphics architecture + FnVarArch_Gpu_Intel_MtlS = 23, // Meteor Lake S Intel graphics architecture + FnVarArch_Gpu_Intel_ArlU = 23, // Arrow Lake U Intel graphics architecture + FnVarArch_Gpu_Intel_ArlS = 23, // Arrow Lake S Intel graphics architecture + FnVarArch_Gpu_Intel_V12704 = 23, // Meteor Lake U Intel graphics architecture + FnVarArch_Gpu_Intel_MtlH = 24, // Meteor Lake H Intel graphics architecture + FnVarArch_Gpu_Intel_V12714 = 24, // Meteor Lake H Intel graphics architecture + FnVarArch_Gpu_Intel_ArlH = 25, // Arrow Lake H Intel graphics architecture + FnVarArch_Gpu_Intel_V12744 = 25, // Arrow Lake H Intel graphics architecture + FnVarArch_Gpu_Intel_BmgG21 = 26, // Battlemage G21 Intel graphics architecture + FnVarArch_Gpu_Intel_V2014 = 26, // Battlemage G21 Intel graphics architecture + FnVarArch_Gpu_Intel_LnlM = 27, // Lunar Lake Intel graphics architecture + FnVarArch_Gpu_Intel_V2044 = 27, // Lunar Lake Intel graphics architecture + FnVarArch_Gpu_Intel_PtlH = 28, // Panther Lake H Intel graphics architecture + FnVarArch_Gpu_Intel_V3004 = 28, // Panther Lake H Intel graphics architecture + FnVarArch_Gpu_Intel_PtlU = 29, // Panther Lake U Intel graphics architecture + FnVarArch_Gpu_Intel_V3011 = 29, // Panther Lake U Intel graphics architecture + FnVarArch_Gpu_Intel_Max = 0x7fffffff, +} FnVarArch_Gpu_Intel; + +typedef enum FnVarArch_Gpu_Amd_ { + FnVarArch_Gpu_Amd_Any = 0, // Any AMD GPU + FnVarArch_Gpu_Amd_Gfx700 = 1, // AMD GCN 2.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx701 = 1, // AMD GCN 2.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx702 = 1, // AMD GCN 2.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx703 = 1, // AMD GCN 2.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx704 = 1, // AMD GCN 2.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx705 = 1, // AMD GCN 2.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx801 = 2, // AMD GCN 3.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx802 = 2, // AMD GCN 3.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx803 = 3, // AMD GCN 4.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx805 = 4, // AMD GCN 3.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx810 = 4, // AMD GCN 3.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx900 = 5, // AMD GCN 5.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx902 = 5, // AMD GCN 5.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx904 = 5, // AMD GCN 5.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx906 = 6, // AMD GCN 5.1 microarchitecture + FnVarArch_Gpu_Amd_Gfx908 = 7, // AMD CDNA 1 microarchitecture + FnVarArch_Gpu_Amd_Gfx909 = 8, // AMD GCN 5.0 microarchitecture + FnVarArch_Gpu_Amd_Gfx90a = 9, // AMD CDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx90c = 10, // AMD GCN 5.1 microarchitecture + FnVarArch_Gpu_Amd_Gfx940 = 11, // AMD CDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx941 = 11, // AMD CDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx942 = 11, // AMD CDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx1010 = 12, // AMD RDNA 1 microarchitecture + FnVarArch_Gpu_Amd_Gfx1011 = 12, // AMD RDNA 1 microarchitecture + FnVarArch_Gpu_Amd_Gfx1012 = 12, // AMD RDNA 1 microarchitecture + FnVarArch_Gpu_Amd_Gfx1013 = 12, // AMD RDNA 1 microarchitecture + FnVarArch_Gpu_Amd_Gfx1030 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1031 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1032 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1033 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1034 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1035 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1036 = 13, // AMD RDNA 2 microarchitecture + FnVarArch_Gpu_Amd_Gfx1100 = 14, // AMD RDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx1101 = 14, // AMD RDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx1102 = 14, // AMD RDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx1103 = 14, // AMD RDNA 3 microarchitecture + FnVarArch_Gpu_Amd_Gfx1150 = 15, // AMD RDNA 3.5 microarchitecture + FnVarArch_Gpu_Amd_Gfx1151 = 15, // AMD RDNA 3.5 microarchitecture + FnVarArch_Gpu_Amd_Gfx1200 = 16, // AMD RDNA 4 microarchitecture + FnVarArch_Gpu_Amd_Gfx1201 = 16, // AMD RDNA 4 microarchitecture + FnVarArch_Gpu_Amd_Max = 0x7fffffff, +} FnVarArch_Gpu_Amd; + +typedef enum FnVarArch_Gpu_Nvidia_ { + FnVarArch_Gpu_Nvidia_Any = 0, // Any NVIDIA GPU + FnVarArch_Gpu_Nvidia_Sm50 = 1, // NVIDIA Maxwell microarchitecture (compute capability 5.0) + FnVarArch_Gpu_Nvidia_Sm52 = 2, // NVIDIA Maxwell microarchitecture (compute capability 5.2) + FnVarArch_Gpu_Nvidia_Sm53 = 3, // NVIDIA Maxwell microarchitecture (compute capability 5.3) + FnVarArch_Gpu_Nvidia_Sm60 = 4, // NVIDIA Pascal microarchitecture (compute capability 6.0) + FnVarArch_Gpu_Nvidia_Sm61 = 5, // NVIDIA Pascal microarchitecture (compute capability 6.1) + FnVarArch_Gpu_Nvidia_Sm62 = 6, // NVIDIA Pascal microarchitecture (compute capability 6.2) + FnVarArch_Gpu_Nvidia_Sm70 = 6, // NVIDIA Volta microarchitecture (compute capability 7.0) + FnVarArch_Gpu_Nvidia_Sm72 = 7, // NVIDIA Volta microarchitecture (compute capability 7.2) + FnVarArch_Gpu_Nvidia_Sm75 = 8, // NVIDIA Turing microarchitecture (compute capability 7.5) + FnVarArch_Gpu_Nvidia_Sm80 = 9, // NVIDIA Ampere microarchitecture (compute capability 8.0) + FnVarArch_Gpu_Nvidia_Sm86 = 10, // NVIDIA Ampere microarchitecture (compute capability 8.6) + FnVarArch_Gpu_Nvidia_Sm87 = 11, // NVIDIA Jetson/Drive AGX Orin microarchitecture + FnVarArch_Gpu_Nvidia_Sm89 = 12, // NVIDIA Ada Lovelace arhitecture + FnVarArch_Gpu_Nvidia_Sm90 = 13, // NVIDIA Hopper arhitecture + FnVarArch_Gpu_Nvidia_Sm90a = 13, // NVIDIA Hopper arhitecture + FnVarArch_Gpu_Nvidia_Max = 0x7fffffff, +} FnVarArch_Gpu_Nvidia; + +typedef enum FnVarArch_Npu_Generic_ { + FnVarArch_Npu_Generic_Any = 0, // Any NPU + FnVarArch_Npu_Generic_Max = 0x7fffffff, +} FnVarArch_Npu_Generic; + +typedef enum FnVarArch_Npu_Intel_ { + FnVarArch_Npu_Intel_Any = 0, // Any Intel NPU + FnVarArch_Npu_Intel_Mtl = 1, // Intel NPU used in Meteor Lake processors + FnVarArch_Npu_Intel_Lnl = 2, // Intel NPU used in Lunar Lake processors + FnVarArch_Npu_Intel_Max = 0x7fffffff, +} FnVarArch_Npu_Intel; + +typedef enum FnVarArch_Npu_AmdXdna_ { + FnVarArch_Npu_AmdXdna_Any = 0, // Any AMD XDNA architecture + FnVarArch_Npu_AmdXdna_Max = 0x7fffffff, +} FnVarArch_Npu_AmdXdna; diff --git a/sycl/doc/design/spirv-extensions/targets/targets.asciidoc b/sycl/doc/design/spirv-extensions/targets/targets.asciidoc new file mode 100644 index 0000000000000..7ed72d35f36c9 --- /dev/null +++ b/sycl/doc/design/spirv-extensions/targets/targets.asciidoc @@ -0,0 +1,4804 @@ + +== Targets + +[%header,cols="8,3,10"] +|=== +|Name +|Value +|Description + +a| +[source] +---- +unknown +---- +| 0 +| Unknown target + +a| +[source] +---- +arm +arm32 = arm +---- +| 1 +| ARM (32-bit) + +a| +[source] +---- +arm64 +aarch64 = arm64 +---- +| 2 +| ARM (64-bit) + +a| +[source] +---- +x86 +---- +| 3 +| x86 (32-bit) + +a| +[source] +---- +x86_64 +---- +| 4 +| x86 (64-bit) + +a| +[source] +---- +riscv32 +---- +| 5 +| RISC-V (32-bit) + +a| +[source] +---- +riscv64 +---- +| 6 +| RISC-V (64-bit) + +a| +[source] +---- +nvptx +---- +| 7 +| NVIDIA PTX (32-bit) + +a| +[source] +---- +nvptx64 +---- +| 8 +| NVIDIA PTX (64-bit) + +a| +[source] +---- +amdgcn +---- +| 9 +| AMD GCN +|=== + +== Features + +[%header,cols="8,3,3,10"] +|=== +|Name +|Target +|Value +|Description + +4+^|*Target: unknown (0)* + +a| +[source] +---- +none +---- +| 0 +| 0 +| No features + +4+^|*Target: arm, arm32 (1)* + +a| +[source] +---- +none +---- +| 1 +| 0 +| No features + +a| +[source] +---- +neon +---- +| 1 +| 1 +| Enable NEON instructions + +4+^|*Target: arm64, aarch64 (2)* + +a| +[source] +---- +none +---- +| 2 +| 0 +| No features + +a| +[source] +---- +fp8 +---- +| 2 +| 1 +| Enable FP8 instructions + +a| +[source] +---- +fp8dot2 +---- +| 2 +| 2 +| Enable FP8 2-way dot product instructions + +a| +[source] +---- +fp8dot4 +---- +| 2 +| 3 +| Enable FP8 4-way dot product instructions + +a| +[source] +---- +neon +---- +| 2 +| 4 +| Enable NEON instructions + +a| +[source] +---- +sve +---- +| 2 +| 5 +| Enable SVE instructions + +4+^|*Target: x86 (3)* + +a| +[source] +---- +none +---- +| 3 +| 0 +| No features + +a| +[source] +---- +fma +---- +| 3 +| 1 +| Enable fused three-operand multiply-add + +a| +[source] +---- +fma4 +---- +| 3 +| 2 +| Enable fused four-operand multiply-add + +a| +[source] +---- +mmx +---- +| 3 +| 3 +| Enable MMX instructions + +a| +[source] +---- +sse +---- +| 3 +| 4 +| Enable SSE instructions + +a| +[source] +---- +sse2 +---- +| 3 +| 5 +| Enable SSE2 instructions + +a| +[source] +---- +sse3 +---- +| 3 +| 6 +| Enable SSE3 instructions + +a| +[source] +---- +sse4.1 +---- +| 3 +| 7 +| Enable SSE4.1 instructions + +a| +[source] +---- +sse4.2 +---- +| 3 +| 8 +| Enable SSE4.2 instructions + +a| +[source] +---- +sse4a +---- +| 3 +| 9 +| Enable SSE4a instructions + +a| +[source] +---- +avx +---- +| 3 +| 10 +| Enable AVX instructions + +a| +[source] +---- +avx2 +---- +| 3 +| 11 +| Enable AVX2 instructions + +a| +[source] +---- +avx512f +---- +| 3 +| 12 +| Enable AVX512 instructions + +4+^|*Target: x86_64 (4)* + +a| +[source] +---- +none +---- +| 4 +| 0 +| No features + +a| +[source] +---- +fma +---- +| 4 +| 1 +| Enable fused three-operand multiply-add + +a| +[source] +---- +fma4 +---- +| 4 +| 2 +| Enable fused four-operand multiply-add + +a| +[source] +---- +mmx +---- +| 4 +| 3 +| Enable MMX instructions + +a| +[source] +---- +sse +---- +| 4 +| 4 +| Enable SSE instructions + +a| +[source] +---- +sse2 +---- +| 4 +| 5 +| Enable SSE2 instructions + +a| +[source] +---- +sse3 +---- +| 4 +| 6 +| Enable SSE3 instructions + +a| +[source] +---- +sse4.1 +---- +| 4 +| 7 +| Enable SSE4.1 instructions + +a| +[source] +---- +sse4.2 +---- +| 4 +| 8 +| Enable SSE4.2 instructions + +a| +[source] +---- +sse4a +---- +| 4 +| 9 +| Enable SSE4a instructions + +a| +[source] +---- +avx +---- +| 4 +| 10 +| Enable AVX instructions + +a| +[source] +---- +avx2 +---- +| 4 +| 11 +| Enable AVX2 instructions + +a| +[source] +---- +avx512f +---- +| 4 +| 12 +| Enable AVX512 instructions + +4+^|*Target: riscv32 (5)* + +a| +[source] +---- +32bit +---- +| 5 +| 0 +| Implements RV32. + +a| +[source] +---- +64bit +---- +| 5 +| 1 +| Implements RV64. + +a| +[source] +---- +a +---- +| 5 +| 2 +| 'A' (Atomic Instructions). + +a| +[source] +---- +auipc-addi-fusion +---- +| 5 +| 3 +| Enable AUIPC+ADDI macrofusion. + +a| +[source] +---- +b +---- +| 5 +| 4 +| 'B' (the collection of the Zba, Zbb, Zbs extensions). + +a| +[source] +---- +c +---- +| 5 +| 5 +| 'C' (Compressed Instructions). + +a| +[source] +---- +conditional-cmv-fusion +---- +| 5 +| 6 +| Enable branch+c.mv fusion. + +a| +[source] +---- +d +---- +| 5 +| 7 +| 'D' (Double-Precision Floating-Point). + +a| +[source] +---- +dlen-factor-2 +---- +| 5 +| 8 +| Vector unit DLEN(data path width) is half of VLEN. + +a| +[source] +---- +e +---- +| 5 +| 9 +| Implements RV{32,64}E (provides 16 rather than 32 GPRs). + +a| +[source] +---- +experimental +---- +| 5 +| 10 +| Experimental intrinsics. + +a| +[source] +---- +experimental-rva23s64 +---- +| 5 +| 11 +| RISC-V experimental-rva23s64 profile. + +a| +[source] +---- +experimental-rva23u64 +---- +| 5 +| 12 +| RISC-V experimental-rva23u64 profile. + +a| +[source] +---- +experimental-rvb23s64 +---- +| 5 +| 13 +| RISC-V experimental-rvb23s64 profile. + +a| +[source] +---- +experimental-rvb23u64 +---- +| 5 +| 14 +| RISC-V experimental-rvb23u64 profile. + +a| +[source] +---- +experimental-rvm23u32 +---- +| 5 +| 15 +| RISC-V experimental-rvm23u32 profile. + +a| +[source] +---- +experimental-smmpm +---- +| 5 +| 16 +| 'Smmpm' (Machine-level Pointer Masking for M-mode). + +a| +[source] +---- +experimental-smnpm +---- +| 5 +| 17 +| 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode). + +a| +[source] +---- +experimental-ssnpm +---- +| 5 +| 18 +| 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode). + +a| +[source] +---- +experimental-sspm +---- +| 5 +| 19 +| 'Sspm' (Indicates Supervisor-mode Pointer Masking). + +a| +[source] +---- +experimental-ssqosid +---- +| 5 +| 20 +| 'Ssqosid' (Quality-of-Service (QoS) Identifiers). + +a| +[source] +---- +experimental-supm +---- +| 5 +| 21 +| 'Supm' (Indicates User-mode Pointer Masking). + +a| +[source] +---- +experimental-zacas +---- +| 5 +| 22 +| 'Zacas' (Atomic Compare-And-Swap Instructions). + +a| +[source] +---- +experimental-zalasr +---- +| 5 +| 23 +| 'Zalasr' (Load-Acquire and Store-Release Instructions). + +a| +[source] +---- +experimental-zicfilp +---- +| 5 +| 24 +| 'Zicfilp' (Landing pad). + +a| +[source] +---- +experimental-zicfiss +---- +| 5 +| 25 +| 'Zicfiss' (Shadow stack). + +a| +[source] +---- +f +---- +| 5 +| 26 +| 'F' (Single-Precision Floating-Point). + +a| +[source] +---- +forced-atomics +---- +| 5 +| 27 +| Assume that lock-free native-width atomics are available. + +a| +[source] +---- +forced-sw-shadow-stack +---- +| 5 +| 28 +| Implement shadow stack with software.. + +a| +[source] +---- +h +---- +| 5 +| 29 +| 'H' (Hypervisor). + +a| +[source] +---- +i +---- +| 5 +| 30 +| 'I' (Base Integer Instruction Set). + +a| +[source] +---- +ld-add-fusion +---- +| 5 +| 31 +| Enable LD+ADD macrofusion. + +a| +[source] +---- +lui-addi-fusion +---- +| 5 +| 32 +| Enable LUI+ADDI macro fusion. + +a| +[source] +---- +m +---- +| 5 +| 33 +| 'M' (Integer Multiplication and Division). + +a| +[source] +---- +no-default-unroll +---- +| 5 +| 34 +| Disable default unroll preference.. + +a| +[source] +---- +no-rvc-hints +---- +| 5 +| 35 +| Disable RVC Hint Instructions.. + +a| +[source] +---- +no-sink-splat-operands +---- +| 5 +| 36 +| Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions. + +a| +[source] +---- +no-trailing-seq-cst-fence +---- +| 5 +| 37 +| Disable trailing fence for seq-cst store.. + +a| +[source] +---- +optimized-zero-stride-load +---- +| 5 +| 38 +| Optimized (perform fewer memory operations)zero-stride vector load. + +a| +[source] +---- +predictable-select-expensive +---- +| 5 +| 39 +| Prefer likely predicted branches over selects. + +a| +[source] +---- +prefer-w-inst +---- +| 5 +| 40 +| Prefer instructions with W suffix. + +a| +[source] +---- +relax +---- +| 5 +| 41 +| Enable Linker relaxation.. + +a| +[source] +---- +reserve-x1 +---- +| 5 +| 42 +| Reserve X1. + +a| +[source] +---- +reserve-x10 +---- +| 5 +| 43 +| Reserve X10. + +a| +[source] +---- +reserve-x11 +---- +| 5 +| 44 +| Reserve X11. + +a| +[source] +---- +reserve-x12 +---- +| 5 +| 45 +| Reserve X12. + +a| +[source] +---- +reserve-x13 +---- +| 5 +| 46 +| Reserve X13. + +a| +[source] +---- +reserve-x14 +---- +| 5 +| 47 +| Reserve X14. + +a| +[source] +---- +reserve-x15 +---- +| 5 +| 48 +| Reserve X15. + +a| +[source] +---- +reserve-x16 +---- +| 5 +| 49 +| Reserve X16. + +a| +[source] +---- +reserve-x17 +---- +| 5 +| 50 +| Reserve X17. + +a| +[source] +---- +reserve-x18 +---- +| 5 +| 51 +| Reserve X18. + +a| +[source] +---- +reserve-x19 +---- +| 5 +| 52 +| Reserve X19. + +a| +[source] +---- +reserve-x2 +---- +| 5 +| 53 +| Reserve X2. + +a| +[source] +---- +reserve-x20 +---- +| 5 +| 54 +| Reserve X20. + +a| +[source] +---- +reserve-x21 +---- +| 5 +| 55 +| Reserve X21. + +a| +[source] +---- +reserve-x22 +---- +| 5 +| 56 +| Reserve X22. + +a| +[source] +---- +reserve-x23 +---- +| 5 +| 57 +| Reserve X23. + +a| +[source] +---- +reserve-x24 +---- +| 5 +| 58 +| Reserve X24. + +a| +[source] +---- +reserve-x25 +---- +| 5 +| 59 +| Reserve X25. + +a| +[source] +---- +reserve-x26 +---- +| 5 +| 60 +| Reserve X26. + +a| +[source] +---- +reserve-x27 +---- +| 5 +| 61 +| Reserve X27. + +a| +[source] +---- +reserve-x28 +---- +| 5 +| 62 +| Reserve X28. + +a| +[source] +---- +reserve-x29 +---- +| 5 +| 63 +| Reserve X29. + +a| +[source] +---- +reserve-x3 +---- +| 5 +| 64 +| Reserve X3. + +a| +[source] +---- +reserve-x30 +---- +| 5 +| 65 +| Reserve X30. + +a| +[source] +---- +reserve-x31 +---- +| 5 +| 66 +| Reserve X31. + +a| +[source] +---- +reserve-x4 +---- +| 5 +| 67 +| Reserve X4. + +a| +[source] +---- +reserve-x5 +---- +| 5 +| 68 +| Reserve X5. + +a| +[source] +---- +reserve-x6 +---- +| 5 +| 69 +| Reserve X6. + +a| +[source] +---- +reserve-x7 +---- +| 5 +| 70 +| Reserve X7. + +a| +[source] +---- +reserve-x8 +---- +| 5 +| 71 +| Reserve X8. + +a| +[source] +---- +reserve-x9 +---- +| 5 +| 72 +| Reserve X9. + +a| +[source] +---- +rva20s64 +---- +| 5 +| 73 +| RISC-V rva20s64 profile. + +a| +[source] +---- +rva20u64 +---- +| 5 +| 74 +| RISC-V rva20u64 profile. + +a| +[source] +---- +rva22s64 +---- +| 5 +| 75 +| RISC-V rva22s64 profile. + +a| +[source] +---- +rva22u64 +---- +| 5 +| 76 +| RISC-V rva22u64 profile. + +a| +[source] +---- +rvi20u32 +---- +| 5 +| 77 +| RISC-V rvi20u32 profile. + +a| +[source] +---- +rvi20u64 +---- +| 5 +| 78 +| RISC-V rvi20u64 profile. + +a| +[source] +---- +save-restore +---- +| 5 +| 79 +| Enable save/restore.. + +a| +[source] +---- +shcounterenw +---- +| 5 +| 80 +| 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero). + +a| +[source] +---- +shgatpa +---- +| 5 +| 81 +| 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). + +a| +[source] +---- +shifted-zextw-fusion +---- +| 5 +| 82 +| Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. + +a| +[source] +---- +short-forward-branch-opt +---- +| 5 +| 83 +| Enable short forward branch optimization. + +a| +[source] +---- +shtvala +---- +| 5 +| 84 +| 'Shtvala' (htval provides all needed values). + +a| +[source] +---- +shvsatpa +---- +| 5 +| 85 +| 'Svsatpa' (vsatp supports all modes supported by satp). + +a| +[source] +---- +shvstvala +---- +| 5 +| 86 +| 'Shvstvala' (vstval provides all needed values). + +a| +[source] +---- +shvstvecd +---- +| 5 +| 87 +| 'Shvstvecd' (vstvec supports Direct mode). + +a| +[source] +---- +sifive7 +---- +| 5 +| 88 +| SiFive 7-Series processors. + +a| +[source] +---- +smaia +---- +| 5 +| 89 +| 'Smaia' (Advanced Interrupt Architecture Machine Level). + +a| +[source] +---- +smcdeleg +---- +| 5 +| 90 +| 'Smcdeleg' (Counter Delegation Machine Level). + +a| +[source] +---- +smcsrind +---- +| 5 +| 91 +| 'Smcsrind' (Indirect CSR Access Machine Level). + +a| +[source] +---- +smepmp +---- +| 5 +| 92 +| 'Smepmp' (Enhanced Physical Memory Protection). + +a| +[source] +---- +smstateen +---- +| 5 +| 93 +| 'Smstateen' (Machine-mode view of the state-enable extension). + +a| +[source] +---- +ssaia +---- +| 5 +| 94 +| 'Ssaia' (Advanced Interrupt Architecture Supervisor Level). + +a| +[source] +---- +ssccfg +---- +| 5 +| 95 +| 'Ssccfg' (Counter Configuration Supervisor Level). + +a| +[source] +---- +ssccptr +---- +| 5 +| 96 +| 'Ssccptr' (Main memory supports page table reads). + +a| +[source] +---- +sscofpmf +---- +| 5 +| 97 +| 'Sscofpmf' (Count Overflow and Mode-Based Filtering). + +a| +[source] +---- +sscounterenw +---- +| 5 +| 98 +| 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero). + +a| +[source] +---- +sscsrind +---- +| 5 +| 99 +| 'Sscsrind' (Indirect CSR Access Supervisor Level). + +a| +[source] +---- +ssstateen +---- +| 5 +| 100 +| 'Ssstateen' (Supervisor-mode view of the state-enable extension). + +a| +[source] +---- +ssstrict +---- +| 5 +| 101 +| 'Ssstrict' (No non-conforming extensions are present). + +a| +[source] +---- +sstc +---- +| 5 +| 102 +| 'Sstc' (Supervisor-mode timer interrupts). + +a| +[source] +---- +sstvala +---- +| 5 +| 103 +| 'Sstvala' (stval provides all needed values). + +a| +[source] +---- +sstvecd +---- +| 5 +| 104 +| 'Sstvecd' (stvec supports Direct mode). + +a| +[source] +---- +ssu64xl +---- +| 5 +| 105 +| 'Ssu64xl' (UXLEN=64 supported). + +a| +[source] +---- +svade +---- +| 5 +| 106 +| 'Svade' (Raise exceptions on improper A/D bits). + +a| +[source] +---- +svadu +---- +| 5 +| 107 +| 'Svadu' (Hardware A/D updates). + +a| +[source] +---- +svbare +---- +| 5 +| 108 +| 'Svbare' $(satp mode Bare supported). + +a| +[source] +---- +svinval +---- +| 5 +| 109 +| 'Svinval' (Fine-Grained Address-Translation Cache Invalidation). + +a| +[source] +---- +svnapot +---- +| 5 +| 110 +| 'Svnapot' (NAPOT Translation Contiguity). + +a| +[source] +---- +svpbmt +---- +| 5 +| 111 +| 'Svpbmt' (Page-Based Memory Types). + +a| +[source] +---- +tagged-globals +---- +| 5 +| 112 +| Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. + +a| +[source] +---- +unaligned-scalar-mem +---- +| 5 +| 113 +| Has reasonably performant unaligned scalar loads and stores. + +a| +[source] +---- +unaligned-vector-mem +---- +| 5 +| 114 +| Has reasonably performant unaligned vector loads and stores. + +a| +[source] +---- +use-postra-scheduler +---- +| 5 +| 115 +| Schedule again after register allocation. + +a| +[source] +---- +v +---- +| 5 +| 116 +| 'V' (Vector Extension for Application Processors). + +a| +[source] +---- +ventana-veyron +---- +| 5 +| 117 +| Ventana Veyron-Series processors. + +a| +[source] +---- +xcvalu +---- +| 5 +| 118 +| 'XCValu' (CORE-V ALU Operations). + +a| +[source] +---- +xcvbi +---- +| 5 +| 119 +| 'XCVbi' (CORE-V Immediate Branching). + +a| +[source] +---- +xcvbitmanip +---- +| 5 +| 120 +| 'XCVbitmanip' (CORE-V Bit Manipulation). + +a| +[source] +---- +xcvelw +---- +| 5 +| 121 +| 'XCVelw' (CORE-V Event Load Word). + +a| +[source] +---- +xcvmac +---- +| 5 +| 122 +| 'XCVmac' (CORE-V Multiply-Accumulate). + +a| +[source] +---- +xcvmem +---- +| 5 +| 123 +| 'XCVmem' (CORE-V Post-incrementing Load & Store). + +a| +[source] +---- +xcvsimd +---- +| 5 +| 124 +| 'XCVsimd' (CORE-V SIMD ALU). + +a| +[source] +---- +xsfcease +---- +| 5 +| 125 +| 'XSfcease' (SiFive sf.cease Instruction). + +a| +[source] +---- +xsfvcp +---- +| 5 +| 126 +| 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions). + +a| +[source] +---- +xsfvfnrclipxfqf +---- +| 5 +| 127 +| 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions). + +a| +[source] +---- +xsfvfwmaccqqq +---- +| 5 +| 128 +| 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4)). + +a| +[source] +---- +xsfvqmaccdod +---- +| 5 +| 129 +| 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)). + +a| +[source] +---- +xsfvqmaccqoq +---- +| 5 +| 130 +| 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)). + +a| +[source] +---- +xsifivecdiscarddlone +---- +| 5 +| 131 +| 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). + +a| +[source] +---- +xsifivecflushdlone +---- +| 5 +| 132 +| 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). + +a| +[source] +---- +xtheadba +---- +| 5 +| 133 +| 'XTHeadBa' (T-Head address calculation instructions). + +a| +[source] +---- +xtheadbb +---- +| 5 +| 134 +| 'XTHeadBb' (T-Head basic bit-manipulation instructions). + +a| +[source] +---- +xtheadbs +---- +| 5 +| 135 +| 'XTHeadBs' (T-Head single-bit instructions). + +a| +[source] +---- +xtheadcmo +---- +| 5 +| 136 +| 'XTHeadCmo' (T-Head cache management instructions). + +a| +[source] +---- +xtheadcondmov +---- +| 5 +| 137 +| 'XTHeadCondMov' (T-Head conditional move instructions). + +a| +[source] +---- +xtheadfmemidx +---- +| 5 +| 138 +| 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations). + +a| +[source] +---- +xtheadmac +---- +| 5 +| 139 +| 'XTHeadMac' (T-Head Multiply-Accumulate Instructions). + +a| +[source] +---- +xtheadmemidx +---- +| 5 +| 140 +| 'XTHeadMemIdx' (T-Head Indexed Memory Operations). + +a| +[source] +---- +xtheadmempair +---- +| 5 +| 141 +| 'XTHeadMemPair' (T-Head two-GPR Memory Operations). + +a| +[source] +---- +xtheadsync +---- +| 5 +| 142 +| 'XTHeadSync' (T-Head multicore synchronization instructions). + +a| +[source] +---- +xtheadvdot +---- +| 5 +| 143 +| 'XTHeadVdot' (T-Head Vector Extensions for Dot). + +a| +[source] +---- +xventanacondops +---- +| 5 +| 144 +| 'XVentanaCondOps' (Ventana Conditional Ops). + +a| +[source] +---- +xwchc +---- +| 5 +| 145 +| 'Xwchc' (WCH/QingKe additional compressed opcodes). + +a| +[source] +---- +za128rs +---- +| 5 +| 146 +| 'Za128rs' (Reservation Set Size of at Most 128 Bytes). + +a| +[source] +---- +za64rs +---- +| 5 +| 147 +| 'Za64rs' (Reservation Set Size of at Most 64 Bytes). + +a| +[source] +---- +zaamo +---- +| 5 +| 148 +| 'Zaamo' (Atomic Memory Operations). + +a| +[source] +---- +zabha +---- +| 5 +| 149 +| 'Zabha' (Byte and Halfword Atomic Memory Operations). + +a| +[source] +---- +zalrsc +---- +| 5 +| 150 +| 'Zalrsc' (Load-Reserved/Store-Conditional). + +a| +[source] +---- +zama16b +---- +| 5 +| 151 +| 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs). + +a| +[source] +---- +zawrs +---- +| 5 +| 152 +| 'Zawrs' (Wait on Reservation Set). + +a| +[source] +---- +zba +---- +| 5 +| 153 +| 'Zba' (Address Generation Instructions). + +a| +[source] +---- +zbb +---- +| 5 +| 154 +| 'Zbb' (Basic Bit-Manipulation). + +a| +[source] +---- +zbc +---- +| 5 +| 155 +| 'Zbc' (Carry-Less Multiplication). + +a| +[source] +---- +zbkb +---- +| 5 +| 156 +| 'Zbkb' (Bitmanip instructions for Cryptography). + +a| +[source] +---- +zbkc +---- +| 5 +| 157 +| 'Zbkc' (Carry-less multiply instructions for Cryptography). + +a| +[source] +---- +zbkx +---- +| 5 +| 158 +| 'Zbkx' (Crossbar permutation instructions). + +a| +[source] +---- +zbs +---- +| 5 +| 159 +| 'Zbs' (Single-Bit Instructions). + +a| +[source] +---- +zca +---- +| 5 +| 160 +| 'Zca' (part of the C extension, excluding compressed floating point loads/stores). + +a| +[source] +---- +zcb +---- +| 5 +| 161 +| 'Zcb' (Compressed basic bit manipulation instructions). + +a| +[source] +---- +zcd +---- +| 5 +| 162 +| 'Zcd' (Compressed Double-Precision Floating-Point Instructions). + +a| +[source] +---- +zce +---- +| 5 +| 163 +| 'Zce' (Compressed extensions for microcontrollers). + +a| +[source] +---- +zcf +---- +| 5 +| 164 +| 'Zcf' (Compressed Single-Precision Floating-Point Instructions). + +a| +[source] +---- +zcmop +---- +| 5 +| 165 +| 'Zcmop' (Compressed May-Be-Operations). + +a| +[source] +---- +zcmp +---- +| 5 +| 166 +| 'Zcmp' (sequenced instructions for code-size reduction). + +a| +[source] +---- +zcmt +---- +| 5 +| 167 +| 'Zcmt' (table jump instructions for code-size reduction). + +a| +[source] +---- +zdinx +---- +| 5 +| 168 +| 'Zdinx' (Double in Integer). + +a| +[source] +---- +zexth-fusion +---- +| 5 +| 169 +| Enable SLLI+SRLI to be fused to zero extension of halfword. + +a| +[source] +---- +zextw-fusion +---- +| 5 +| 170 +| Enable SLLI+SRLI to be fused to zero extension of word. + +a| +[source] +---- +zfa +---- +| 5 +| 171 +| 'Zfa' (Additional Floating-Point). + +a| +[source] +---- +zfbfmin +---- +| 5 +| 172 +| 'Zfbfmin' (Scalar BF16 Converts). + +a| +[source] +---- +zfh +---- +| 5 +| 173 +| 'Zfh' (Half-Precision Floating-Point). + +a| +[source] +---- +zfhmin +---- +| 5 +| 174 +| 'Zfhmin' (Half-Precision Floating-Point Minimal). + +a| +[source] +---- +zfinx +---- +| 5 +| 175 +| 'Zfinx' (Float in Integer). + +a| +[source] +---- +zhinx +---- +| 5 +| 176 +| 'Zhinx' (Half Float in Integer). + +a| +[source] +---- +zhinxmin +---- +| 5 +| 177 +| 'Zhinxmin' (Half Float in Integer Minimal). + +a| +[source] +---- +zic64b +---- +| 5 +| 178 +| 'Zic64b' (Cache Block Size Is 64 Bytes). + +a| +[source] +---- +zicbom +---- +| 5 +| 179 +| 'Zicbom' (Cache-Block Management Instructions). + +a| +[source] +---- +zicbop +---- +| 5 +| 180 +| 'Zicbop' (Cache-Block Prefetch Instructions). + +a| +[source] +---- +zicboz +---- +| 5 +| 181 +| 'Zicboz' (Cache-Block Zero Instructions). + +a| +[source] +---- +ziccamoa +---- +| 5 +| 182 +| 'Ziccamoa' (Main Memory Supports All Atomics in A). + +a| +[source] +---- +ziccif +---- +| 5 +| 183 +| 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement). + +a| +[source] +---- +zicclsm +---- +| 5 +| 184 +| 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores). + +a| +[source] +---- +ziccrse +---- +| 5 +| 185 +| 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences). + +a| +[source] +---- +zicntr +---- +| 5 +| 186 +| 'Zicntr' (Base Counters and Timers). + +a| +[source] +---- +zicond +---- +| 5 +| 187 +| 'Zicond' (Integer Conditional Operations). + +a| +[source] +---- +zicsr +---- +| 5 +| 188 +| 'zicsr' (CSRs). + +a| +[source] +---- +zifencei +---- +| 5 +| 189 +| 'Zifencei' (fence.i). + +a| +[source] +---- +zihintntl +---- +| 5 +| 190 +| 'Zihintntl' (Non-Temporal Locality Hints). + +a| +[source] +---- +zihintpause +---- +| 5 +| 191 +| 'Zihintpause' (Pause Hint). + +a| +[source] +---- +zihpm +---- +| 5 +| 192 +| 'Zihpm' (Hardware Performance Counters). + +a| +[source] +---- +zimop +---- +| 5 +| 193 +| 'Zimop' (May-Be-Operations). + +a| +[source] +---- +zk +---- +| 5 +| 194 +| 'Zk' (Standard scalar cryptography extension). + +a| +[source] +---- +zkn +---- +| 5 +| 195 +| 'Zkn' (NIST Algorithm Suite). + +a| +[source] +---- +zknd +---- +| 5 +| 196 +| 'Zknd' (NIST Suite: AES Decryption). + +a| +[source] +---- +zkne +---- +| 5 +| 197 +| 'Zkne' (NIST Suite: AES Encryption). + +a| +[source] +---- +zknh +---- +| 5 +| 198 +| 'Zknh' (NIST Suite: Hash Function Instructions). + +a| +[source] +---- +zkr +---- +| 5 +| 199 +| 'Zkr' (Entropy Source Extension). + +a| +[source] +---- +zks +---- +| 5 +| 200 +| 'Zks' (ShangMi Algorithm Suite). + +a| +[source] +---- +zksed +---- +| 5 +| 201 +| 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions). + +a| +[source] +---- +zksh +---- +| 5 +| 202 +| 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions). + +a| +[source] +---- +zkt +---- +| 5 +| 203 +| 'Zkt' (Data Independent Execution Latency). + +a| +[source] +---- +zmmul +---- +| 5 +| 204 +| 'Zmmul' (Integer Multiplication). + +a| +[source] +---- +ztso +---- +| 5 +| 205 +| 'Ztso' (Memory Model + +a| +[source] +---- +zvbb +---- +| 5 +| 206 +| 'Zvbb' (Vector basic bit-manipulation instructions). + +a| +[source] +---- +zvbc +---- +| 5 +| 207 +| 'Zvbc' (Vector Carryless Multiplication). + +a| +[source] +---- +zve32f +---- +| 5 +| 208 +| 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension). + +a| +[source] +---- +zve32x +---- +| 5 +| 209 +| 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW). + +a| +[source] +---- +zve64d +---- +| 5 +| 210 +| 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension). + +a| +[source] +---- +zve64f +---- +| 5 +| 211 +| 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension). + +a| +[source] +---- +zve64x +---- +| 5 +| 212 +| 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW). + +a| +[source] +---- +zvfbfmin +---- +| 5 +| 213 +| 'Zvbfmin' (Vector BF16 Converts). + +a| +[source] +---- +zvfbfwma +---- +| 5 +| 214 +| 'Zvfbfwma' (Vector BF16 widening mul-add). + +a| +[source] +---- +zvfh +---- +| 5 +| 215 +| 'Zvfh' (Vector Half-Precision Floating-Point). + +a| +[source] +---- +zvfhmin +---- +| 5 +| 216 +| 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal). + +a| +[source] +---- +zvkb +---- +| 5 +| 217 +| 'Zvkb' (Vector Bit-manipulation used in Cryptography). + +a| +[source] +---- +zvkg +---- +| 5 +| 218 +| 'Zvkg' (Vector GCM instructions for Cryptography). + +a| +[source] +---- +zvkn +---- +| 5 +| 219 +| 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'). + +a| +[source] +---- +zvknc +---- +| 5 +| 220 +| 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc'). + +a| +[source] +---- +zvkned +---- +| 5 +| 221 +| 'Zvkned' (Vector AES Encryption & Decryption (Single Round)). + +a| +[source] +---- +zvkng +---- +| 5 +| 222 +| 'zvkng' (shorthand for 'Zvkn' and 'Zvkg'). + +a| +[source] +---- +zvknha +---- +| 5 +| 223 +| 'Zvknha' (Vector SHA-2 (SHA-256 only)). + +a| +[source] +---- +zvknhb +---- +| 5 +| 224 +| 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)). + +a| +[source] +---- +zvks +---- +| 5 +| 225 +| 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'). + +a| +[source] +---- +zvksc +---- +| 5 +| 226 +| 'Zvksc' (shorthand for 'Zvks' and 'Zvbc'). + +a| +[source] +---- +zvksed +---- +| 5 +| 227 +| 'Zvksed' (SM4 Block Cipher Instructions). + +a| +[source] +---- +zvksg +---- +| 5 +| 228 +| 'Zvksg' (shorthand for 'Zvks' and 'Zvkg'). + +a| +[source] +---- +zvksh +---- +| 5 +| 229 +| 'Zvksh' (SM3 Hash Function Instructions). + +a| +[source] +---- +zvkt +---- +| 5 +| 230 +| 'Zvkt' (Vector Data-Independent Execution Latency). + +a| +[source] +---- +zvl1024b +---- +| 5 +| 231 +| 'Zvl' (Minimum Vector Length) 1024. + +a| +[source] +---- +zvl128b +---- +| 5 +| 232 +| 'Zvl' (Minimum Vector Length) 128. + +a| +[source] +---- +zvl16384b +---- +| 5 +| 233 +| 'Zvl' (Minimum Vector Length) 16384. + +a| +[source] +---- +zvl2048b +---- +| 5 +| 234 +| 'Zvl' (Minimum Vector Length) 2048. + +a| +[source] +---- +zvl256b +---- +| 5 +| 235 +| 'Zvl' (Minimum Vector Length) 256. + +a| +[source] +---- +zvl32768b +---- +| 5 +| 236 +| 'Zvl' (Minimum Vector Length) 32768. + +a| +[source] +---- +zvl32b +---- +| 5 +| 237 +| 'Zvl' (Minimum Vector Length) 32. + +a| +[source] +---- +zvl4096b +---- +| 5 +| 238 +| 'Zvl' (Minimum Vector Length) 4096. + +a| +[source] +---- +zvl512b +---- +| 5 +| 239 +| 'Zvl' (Minimum Vector Length) 512. + +a| +[source] +---- +zvl64b +---- +| 5 +| 240 +| 'Zvl' (Minimum Vector Length) 64. + +a| +[source] +---- +zvl65536b +---- +| 5 +| 241 +| 'Zvl' (Minimum Vector Length) 65536. + +a| +[source] +---- +zvl8192b +---- +| 5 +| 242 +| 'Zvl' (Minimum Vector Length) 8192. + +4+^|*Target: riscv64 (6)* + +a| +[source] +---- +32bit +---- +| 6 +| 0 +| Implements RV32. + +a| +[source] +---- +64bit +---- +| 6 +| 1 +| Implements RV64. + +a| +[source] +---- +a +---- +| 6 +| 2 +| 'A' (Atomic Instructions). + +a| +[source] +---- +auipc-addi-fusion +---- +| 6 +| 3 +| Enable AUIPC+ADDI macrofusion. + +a| +[source] +---- +b +---- +| 6 +| 4 +| 'B' (the collection of the Zba, Zbb, Zbs extensions). + +a| +[source] +---- +c +---- +| 6 +| 5 +| 'C' (Compressed Instructions). + +a| +[source] +---- +conditional-cmv-fusion +---- +| 6 +| 6 +| Enable branch+c.mv fusion. + +a| +[source] +---- +d +---- +| 6 +| 7 +| 'D' (Double-Precision Floating-Point). + +a| +[source] +---- +dlen-factor-2 +---- +| 6 +| 8 +| Vector unit DLEN(data path width) is half of VLEN. + +a| +[source] +---- +e +---- +| 6 +| 9 +| Implements RV{32,64}E (provides 16 rather than 32 GPRs). + +a| +[source] +---- +experimental +---- +| 6 +| 10 +| Experimental intrinsics. + +a| +[source] +---- +experimental-rva23s64 +---- +| 6 +| 11 +| RISC-V experimental-rva23s64 profile. + +a| +[source] +---- +experimental-rva23u64 +---- +| 6 +| 12 +| RISC-V experimental-rva23u64 profile. + +a| +[source] +---- +experimental-rvb23s64 +---- +| 6 +| 13 +| RISC-V experimental-rvb23s64 profile. + +a| +[source] +---- +experimental-rvb23u64 +---- +| 6 +| 14 +| RISC-V experimental-rvb23u64 profile. + +a| +[source] +---- +experimental-rvm23u32 +---- +| 6 +| 15 +| RISC-V experimental-rvm23u32 profile. + +a| +[source] +---- +experimental-smmpm +---- +| 6 +| 16 +| 'Smmpm' (Machine-level Pointer Masking for M-mode). + +a| +[source] +---- +experimental-smnpm +---- +| 6 +| 17 +| 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode). + +a| +[source] +---- +experimental-ssnpm +---- +| 6 +| 18 +| 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode). + +a| +[source] +---- +experimental-sspm +---- +| 6 +| 19 +| 'Sspm' (Indicates Supervisor-mode Pointer Masking). + +a| +[source] +---- +experimental-ssqosid +---- +| 6 +| 20 +| 'Ssqosid' (Quality-of-Service (QoS) Identifiers). + +a| +[source] +---- +experimental-supm +---- +| 6 +| 21 +| 'Supm' (Indicates User-mode Pointer Masking). + +a| +[source] +---- +experimental-zacas +---- +| 6 +| 22 +| 'Zacas' (Atomic Compare-And-Swap Instructions). + +a| +[source] +---- +experimental-zalasr +---- +| 6 +| 23 +| 'Zalasr' (Load-Acquire and Store-Release Instructions). + +a| +[source] +---- +experimental-zicfilp +---- +| 6 +| 24 +| 'Zicfilp' (Landing pad). + +a| +[source] +---- +experimental-zicfiss +---- +| 6 +| 25 +| 'Zicfiss' (Shadow stack). + +a| +[source] +---- +f +---- +| 6 +| 26 +| 'F' (Single-Precision Floating-Point). + +a| +[source] +---- +forced-atomics +---- +| 6 +| 27 +| Assume that lock-free native-width atomics are available. + +a| +[source] +---- +forced-sw-shadow-stack +---- +| 6 +| 28 +| Implement shadow stack with software.. + +a| +[source] +---- +h +---- +| 6 +| 29 +| 'H' (Hypervisor). + +a| +[source] +---- +i +---- +| 6 +| 30 +| 'I' (Base Integer Instruction Set). + +a| +[source] +---- +ld-add-fusion +---- +| 6 +| 31 +| Enable LD+ADD macrofusion. + +a| +[source] +---- +lui-addi-fusion +---- +| 6 +| 32 +| Enable LUI+ADDI macro fusion. + +a| +[source] +---- +m +---- +| 6 +| 33 +| 'M' (Integer Multiplication and Division). + +a| +[source] +---- +no-default-unroll +---- +| 6 +| 34 +| Disable default unroll preference.. + +a| +[source] +---- +no-rvc-hints +---- +| 6 +| 35 +| Disable RVC Hint Instructions.. + +a| +[source] +---- +no-sink-splat-operands +---- +| 6 +| 36 +| Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions. + +a| +[source] +---- +no-trailing-seq-cst-fence +---- +| 6 +| 37 +| Disable trailing fence for seq-cst store.. + +a| +[source] +---- +optimized-zero-stride-load +---- +| 6 +| 38 +| Optimized (perform fewer memory operations)zero-stride vector load. + +a| +[source] +---- +predictable-select-expensive +---- +| 6 +| 39 +| Prefer likely predicted branches over selects. + +a| +[source] +---- +prefer-w-inst +---- +| 6 +| 40 +| Prefer instructions with W suffix. + +a| +[source] +---- +relax +---- +| 6 +| 41 +| Enable Linker relaxation.. + +a| +[source] +---- +reserve-x1 +---- +| 6 +| 42 +| Reserve X1. + +a| +[source] +---- +reserve-x10 +---- +| 6 +| 43 +| Reserve X10. + +a| +[source] +---- +reserve-x11 +---- +| 6 +| 44 +| Reserve X11. + +a| +[source] +---- +reserve-x12 +---- +| 6 +| 45 +| Reserve X12. + +a| +[source] +---- +reserve-x13 +---- +| 6 +| 46 +| Reserve X13. + +a| +[source] +---- +reserve-x14 +---- +| 6 +| 47 +| Reserve X14. + +a| +[source] +---- +reserve-x15 +---- +| 6 +| 48 +| Reserve X15. + +a| +[source] +---- +reserve-x16 +---- +| 6 +| 49 +| Reserve X16. + +a| +[source] +---- +reserve-x17 +---- +| 6 +| 50 +| Reserve X17. + +a| +[source] +---- +reserve-x18 +---- +| 6 +| 51 +| Reserve X18. + +a| +[source] +---- +reserve-x19 +---- +| 6 +| 52 +| Reserve X19. + +a| +[source] +---- +reserve-x2 +---- +| 6 +| 53 +| Reserve X2. + +a| +[source] +---- +reserve-x20 +---- +| 6 +| 54 +| Reserve X20. + +a| +[source] +---- +reserve-x21 +---- +| 6 +| 55 +| Reserve X21. + +a| +[source] +---- +reserve-x22 +---- +| 6 +| 56 +| Reserve X22. + +a| +[source] +---- +reserve-x23 +---- +| 6 +| 57 +| Reserve X23. + +a| +[source] +---- +reserve-x24 +---- +| 6 +| 58 +| Reserve X24. + +a| +[source] +---- +reserve-x25 +---- +| 6 +| 59 +| Reserve X25. + +a| +[source] +---- +reserve-x26 +---- +| 6 +| 60 +| Reserve X26. + +a| +[source] +---- +reserve-x27 +---- +| 6 +| 61 +| Reserve X27. + +a| +[source] +---- +reserve-x28 +---- +| 6 +| 62 +| Reserve X28. + +a| +[source] +---- +reserve-x29 +---- +| 6 +| 63 +| Reserve X29. + +a| +[source] +---- +reserve-x3 +---- +| 6 +| 64 +| Reserve X3. + +a| +[source] +---- +reserve-x30 +---- +| 6 +| 65 +| Reserve X30. + +a| +[source] +---- +reserve-x31 +---- +| 6 +| 66 +| Reserve X31. + +a| +[source] +---- +reserve-x4 +---- +| 6 +| 67 +| Reserve X4. + +a| +[source] +---- +reserve-x5 +---- +| 6 +| 68 +| Reserve X5. + +a| +[source] +---- +reserve-x6 +---- +| 6 +| 69 +| Reserve X6. + +a| +[source] +---- +reserve-x7 +---- +| 6 +| 70 +| Reserve X7. + +a| +[source] +---- +reserve-x8 +---- +| 6 +| 71 +| Reserve X8. + +a| +[source] +---- +reserve-x9 +---- +| 6 +| 72 +| Reserve X9. + +a| +[source] +---- +rva20s64 +---- +| 6 +| 73 +| RISC-V rva20s64 profile. + +a| +[source] +---- +rva20u64 +---- +| 6 +| 74 +| RISC-V rva20u64 profile. + +a| +[source] +---- +rva22s64 +---- +| 6 +| 75 +| RISC-V rva22s64 profile. + +a| +[source] +---- +rva22u64 +---- +| 6 +| 76 +| RISC-V rva22u64 profile. + +a| +[source] +---- +rvi20u32 +---- +| 6 +| 77 +| RISC-V rvi20u32 profile. + +a| +[source] +---- +rvi20u64 +---- +| 6 +| 78 +| RISC-V rvi20u64 profile. + +a| +[source] +---- +save-restore +---- +| 6 +| 79 +| Enable save/restore.. + +a| +[source] +---- +shcounterenw +---- +| 6 +| 80 +| 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero). + +a| +[source] +---- +shgatpa +---- +| 6 +| 81 +| 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). + +a| +[source] +---- +shifted-zextw-fusion +---- +| 6 +| 82 +| Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. + +a| +[source] +---- +short-forward-branch-opt +---- +| 6 +| 83 +| Enable short forward branch optimization. + +a| +[source] +---- +shtvala +---- +| 6 +| 84 +| 'Shtvala' (htval provides all needed values). + +a| +[source] +---- +shvsatpa +---- +| 6 +| 85 +| 'Svsatpa' (vsatp supports all modes supported by satp). + +a| +[source] +---- +shvstvala +---- +| 6 +| 86 +| 'Shvstvala' (vstval provides all needed values). + +a| +[source] +---- +shvstvecd +---- +| 6 +| 87 +| 'Shvstvecd' (vstvec supports Direct mode). + +a| +[source] +---- +sifive7 +---- +| 6 +| 88 +| SiFive 7-Series processors. + +a| +[source] +---- +smaia +---- +| 6 +| 89 +| 'Smaia' (Advanced Interrupt Architecture Machine Level). + +a| +[source] +---- +smcdeleg +---- +| 6 +| 90 +| 'Smcdeleg' (Counter Delegation Machine Level). + +a| +[source] +---- +smcsrind +---- +| 6 +| 91 +| 'Smcsrind' (Indirect CSR Access Machine Level). + +a| +[source] +---- +smepmp +---- +| 6 +| 92 +| 'Smepmp' (Enhanced Physical Memory Protection). + +a| +[source] +---- +smstateen +---- +| 6 +| 93 +| 'Smstateen' (Machine-mode view of the state-enable extension). + +a| +[source] +---- +ssaia +---- +| 6 +| 94 +| 'Ssaia' (Advanced Interrupt Architecture Supervisor Level). + +a| +[source] +---- +ssccfg +---- +| 6 +| 95 +| 'Ssccfg' (Counter Configuration Supervisor Level). + +a| +[source] +---- +ssccptr +---- +| 6 +| 96 +| 'Ssccptr' (Main memory supports page table reads). + +a| +[source] +---- +sscofpmf +---- +| 6 +| 97 +| 'Sscofpmf' (Count Overflow and Mode-Based Filtering). + +a| +[source] +---- +sscounterenw +---- +| 6 +| 98 +| 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero). + +a| +[source] +---- +sscsrind +---- +| 6 +| 99 +| 'Sscsrind' (Indirect CSR Access Supervisor Level). + +a| +[source] +---- +ssstateen +---- +| 6 +| 100 +| 'Ssstateen' (Supervisor-mode view of the state-enable extension). + +a| +[source] +---- +ssstrict +---- +| 6 +| 101 +| 'Ssstrict' (No non-conforming extensions are present). + +a| +[source] +---- +sstc +---- +| 6 +| 102 +| 'Sstc' (Supervisor-mode timer interrupts). + +a| +[source] +---- +sstvala +---- +| 6 +| 103 +| 'Sstvala' (stval provides all needed values). + +a| +[source] +---- +sstvecd +---- +| 6 +| 104 +| 'Sstvecd' (stvec supports Direct mode). + +a| +[source] +---- +ssu64xl +---- +| 6 +| 105 +| 'Ssu64xl' (UXLEN=64 supported). + +a| +[source] +---- +svade +---- +| 6 +| 106 +| 'Svade' (Raise exceptions on improper A/D bits). + +a| +[source] +---- +svadu +---- +| 6 +| 107 +| 'Svadu' (Hardware A/D updates). + +a| +[source] +---- +svbare +---- +| 6 +| 108 +| 'Svbare' $(satp mode Bare supported). + +a| +[source] +---- +svinval +---- +| 6 +| 109 +| 'Svinval' (Fine-Grained Address-Translation Cache Invalidation). + +a| +[source] +---- +svnapot +---- +| 6 +| 110 +| 'Svnapot' (NAPOT Translation Contiguity). + +a| +[source] +---- +svpbmt +---- +| 6 +| 111 +| 'Svpbmt' (Page-Based Memory Types). + +a| +[source] +---- +tagged-globals +---- +| 6 +| 112 +| Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. + +a| +[source] +---- +unaligned-scalar-mem +---- +| 6 +| 113 +| Has reasonably performant unaligned scalar loads and stores. + +a| +[source] +---- +unaligned-vector-mem +---- +| 6 +| 114 +| Has reasonably performant unaligned vector loads and stores. + +a| +[source] +---- +use-postra-scheduler +---- +| 6 +| 115 +| Schedule again after register allocation. + +a| +[source] +---- +v +---- +| 6 +| 116 +| 'V' (Vector Extension for Application Processors). + +a| +[source] +---- +ventana-veyron +---- +| 6 +| 117 +| Ventana Veyron-Series processors. + +a| +[source] +---- +xcvalu +---- +| 6 +| 118 +| 'XCValu' (CORE-V ALU Operations). + +a| +[source] +---- +xcvbi +---- +| 6 +| 119 +| 'XCVbi' (CORE-V Immediate Branching). + +a| +[source] +---- +xcvbitmanip +---- +| 6 +| 120 +| 'XCVbitmanip' (CORE-V Bit Manipulation). + +a| +[source] +---- +xcvelw +---- +| 6 +| 121 +| 'XCVelw' (CORE-V Event Load Word). + +a| +[source] +---- +xcvmac +---- +| 6 +| 122 +| 'XCVmac' (CORE-V Multiply-Accumulate). + +a| +[source] +---- +xcvmem +---- +| 6 +| 123 +| 'XCVmem' (CORE-V Post-incrementing Load & Store). + +a| +[source] +---- +xcvsimd +---- +| 6 +| 124 +| 'XCVsimd' (CORE-V SIMD ALU). + +a| +[source] +---- +xsfcease +---- +| 6 +| 125 +| 'XSfcease' (SiFive sf.cease Instruction). + +a| +[source] +---- +xsfvcp +---- +| 6 +| 126 +| 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions). + +a| +[source] +---- +xsfvfnrclipxfqf +---- +| 6 +| 127 +| 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions). + +a| +[source] +---- +xsfvfwmaccqqq +---- +| 6 +| 128 +| 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4)). + +a| +[source] +---- +xsfvqmaccdod +---- +| 6 +| 129 +| 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)). + +a| +[source] +---- +xsfvqmaccqoq +---- +| 6 +| 130 +| 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)). + +a| +[source] +---- +xsifivecdiscarddlone +---- +| 6 +| 131 +| 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). + +a| +[source] +---- +xsifivecflushdlone +---- +| 6 +| 132 +| 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). + +a| +[source] +---- +xtheadba +---- +| 6 +| 133 +| 'XTHeadBa' (T-Head address calculation instructions). + +a| +[source] +---- +xtheadbb +---- +| 6 +| 134 +| 'XTHeadBb' (T-Head basic bit-manipulation instructions). + +a| +[source] +---- +xtheadbs +---- +| 6 +| 135 +| 'XTHeadBs' (T-Head single-bit instructions). + +a| +[source] +---- +xtheadcmo +---- +| 6 +| 136 +| 'XTHeadCmo' (T-Head cache management instructions). + +a| +[source] +---- +xtheadcondmov +---- +| 6 +| 137 +| 'XTHeadCondMov' (T-Head conditional move instructions). + +a| +[source] +---- +xtheadfmemidx +---- +| 6 +| 138 +| 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations). + +a| +[source] +---- +xtheadmac +---- +| 6 +| 139 +| 'XTHeadMac' (T-Head Multiply-Accumulate Instructions). + +a| +[source] +---- +xtheadmemidx +---- +| 6 +| 140 +| 'XTHeadMemIdx' (T-Head Indexed Memory Operations). + +a| +[source] +---- +xtheadmempair +---- +| 6 +| 141 +| 'XTHeadMemPair' (T-Head two-GPR Memory Operations). + +a| +[source] +---- +xtheadsync +---- +| 6 +| 142 +| 'XTHeadSync' (T-Head multicore synchronization instructions). + +a| +[source] +---- +xtheadvdot +---- +| 6 +| 143 +| 'XTHeadVdot' (T-Head Vector Extensions for Dot). + +a| +[source] +---- +xventanacondops +---- +| 6 +| 144 +| 'XVentanaCondOps' (Ventana Conditional Ops). + +a| +[source] +---- +xwchc +---- +| 6 +| 145 +| 'Xwchc' (WCH/QingKe additional compressed opcodes). + +a| +[source] +---- +za128rs +---- +| 6 +| 146 +| 'Za128rs' (Reservation Set Size of at Most 128 Bytes). + +a| +[source] +---- +za64rs +---- +| 6 +| 147 +| 'Za64rs' (Reservation Set Size of at Most 64 Bytes). + +a| +[source] +---- +zaamo +---- +| 6 +| 148 +| 'Zaamo' (Atomic Memory Operations). + +a| +[source] +---- +zabha +---- +| 6 +| 149 +| 'Zabha' (Byte and Halfword Atomic Memory Operations). + +a| +[source] +---- +zalrsc +---- +| 6 +| 150 +| 'Zalrsc' (Load-Reserved/Store-Conditional). + +a| +[source] +---- +zama16b +---- +| 6 +| 151 +| 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs). + +a| +[source] +---- +zawrs +---- +| 6 +| 152 +| 'Zawrs' (Wait on Reservation Set). + +a| +[source] +---- +zba +---- +| 6 +| 153 +| 'Zba' (Address Generation Instructions). + +a| +[source] +---- +zbb +---- +| 6 +| 154 +| 'Zbb' (Basic Bit-Manipulation). + +a| +[source] +---- +zbc +---- +| 6 +| 155 +| 'Zbc' (Carry-Less Multiplication). + +a| +[source] +---- +zbkb +---- +| 6 +| 156 +| 'Zbkb' (Bitmanip instructions for Cryptography). + +a| +[source] +---- +zbkc +---- +| 6 +| 157 +| 'Zbkc' (Carry-less multiply instructions for Cryptography). + +a| +[source] +---- +zbkx +---- +| 6 +| 158 +| 'Zbkx' (Crossbar permutation instructions). + +a| +[source] +---- +zbs +---- +| 6 +| 159 +| 'Zbs' (Single-Bit Instructions). + +a| +[source] +---- +zca +---- +| 6 +| 160 +| 'Zca' (part of the C extension, excluding compressed floating point loads/stores). + +a| +[source] +---- +zcb +---- +| 6 +| 161 +| 'Zcb' (Compressed basic bit manipulation instructions). + +a| +[source] +---- +zcd +---- +| 6 +| 162 +| 'Zcd' (Compressed Double-Precision Floating-Point Instructions). + +a| +[source] +---- +zce +---- +| 6 +| 163 +| 'Zce' (Compressed extensions for microcontrollers). + +a| +[source] +---- +zcf +---- +| 6 +| 164 +| 'Zcf' (Compressed Single-Precision Floating-Point Instructions). + +a| +[source] +---- +zcmop +---- +| 6 +| 165 +| 'Zcmop' (Compressed May-Be-Operations). + +a| +[source] +---- +zcmp +---- +| 6 +| 166 +| 'Zcmp' (sequenced instructions for code-size reduction). + +a| +[source] +---- +zcmt +---- +| 6 +| 167 +| 'Zcmt' (table jump instructions for code-size reduction). + +a| +[source] +---- +zdinx +---- +| 6 +| 168 +| 'Zdinx' (Double in Integer). + +a| +[source] +---- +zexth-fusion +---- +| 6 +| 169 +| Enable SLLI+SRLI to be fused to zero extension of halfword. + +a| +[source] +---- +zextw-fusion +---- +| 6 +| 170 +| Enable SLLI+SRLI to be fused to zero extension of word. + +a| +[source] +---- +zfa +---- +| 6 +| 171 +| 'Zfa' (Additional Floating-Point). + +a| +[source] +---- +zfbfmin +---- +| 6 +| 172 +| 'Zfbfmin' (Scalar BF16 Converts). + +a| +[source] +---- +zfh +---- +| 6 +| 173 +| 'Zfh' (Half-Precision Floating-Point). + +a| +[source] +---- +zfhmin +---- +| 6 +| 174 +| 'Zfhmin' (Half-Precision Floating-Point Minimal). + +a| +[source] +---- +zfinx +---- +| 6 +| 175 +| 'Zfinx' (Float in Integer). + +a| +[source] +---- +zhinx +---- +| 6 +| 176 +| 'Zhinx' (Half Float in Integer). + +a| +[source] +---- +zhinxmin +---- +| 6 +| 177 +| 'Zhinxmin' (Half Float in Integer Minimal). + +a| +[source] +---- +zic64b +---- +| 6 +| 178 +| 'Zic64b' (Cache Block Size Is 64 Bytes). + +a| +[source] +---- +zicbom +---- +| 6 +| 179 +| 'Zicbom' (Cache-Block Management Instructions). + +a| +[source] +---- +zicbop +---- +| 6 +| 180 +| 'Zicbop' (Cache-Block Prefetch Instructions). + +a| +[source] +---- +zicboz +---- +| 6 +| 181 +| 'Zicboz' (Cache-Block Zero Instructions). + +a| +[source] +---- +ziccamoa +---- +| 6 +| 182 +| 'Ziccamoa' (Main Memory Supports All Atomics in A). + +a| +[source] +---- +ziccif +---- +| 6 +| 183 +| 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement). + +a| +[source] +---- +zicclsm +---- +| 6 +| 184 +| 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores). + +a| +[source] +---- +ziccrse +---- +| 6 +| 185 +| 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences). + +a| +[source] +---- +zicntr +---- +| 6 +| 186 +| 'Zicntr' (Base Counters and Timers). + +a| +[source] +---- +zicond +---- +| 6 +| 187 +| 'Zicond' (Integer Conditional Operations). + +a| +[source] +---- +zicsr +---- +| 6 +| 188 +| 'zicsr' (CSRs). + +a| +[source] +---- +zifencei +---- +| 6 +| 189 +| 'Zifencei' (fence.i). + +a| +[source] +---- +zihintntl +---- +| 6 +| 190 +| 'Zihintntl' (Non-Temporal Locality Hints). + +a| +[source] +---- +zihintpause +---- +| 6 +| 191 +| 'Zihintpause' (Pause Hint). + +a| +[source] +---- +zihpm +---- +| 6 +| 192 +| 'Zihpm' (Hardware Performance Counters). + +a| +[source] +---- +zimop +---- +| 6 +| 193 +| 'Zimop' (May-Be-Operations). + +a| +[source] +---- +zk +---- +| 6 +| 194 +| 'Zk' (Standard scalar cryptography extension). + +a| +[source] +---- +zkn +---- +| 6 +| 195 +| 'Zkn' (NIST Algorithm Suite). + +a| +[source] +---- +zknd +---- +| 6 +| 196 +| 'Zknd' (NIST Suite: AES Decryption). + +a| +[source] +---- +zkne +---- +| 6 +| 197 +| 'Zkne' (NIST Suite: AES Encryption). + +a| +[source] +---- +zknh +---- +| 6 +| 198 +| 'Zknh' (NIST Suite: Hash Function Instructions). + +a| +[source] +---- +zkr +---- +| 6 +| 199 +| 'Zkr' (Entropy Source Extension). + +a| +[source] +---- +zks +---- +| 6 +| 200 +| 'Zks' (ShangMi Algorithm Suite). + +a| +[source] +---- +zksed +---- +| 6 +| 201 +| 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions). + +a| +[source] +---- +zksh +---- +| 6 +| 202 +| 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions). + +a| +[source] +---- +zkt +---- +| 6 +| 203 +| 'Zkt' (Data Independent Execution Latency). + +a| +[source] +---- +zmmul +---- +| 6 +| 204 +| 'Zmmul' (Integer Multiplication). + +a| +[source] +---- +ztso +---- +| 6 +| 205 +| 'Ztso' (Memory Model + +a| +[source] +---- +zvbb +---- +| 6 +| 206 +| 'Zvbb' (Vector basic bit-manipulation instructions). + +a| +[source] +---- +zvbc +---- +| 6 +| 207 +| 'Zvbc' (Vector Carryless Multiplication). + +a| +[source] +---- +zve32f +---- +| 6 +| 208 +| 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension). + +a| +[source] +---- +zve32x +---- +| 6 +| 209 +| 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW). + +a| +[source] +---- +zve64d +---- +| 6 +| 210 +| 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension). + +a| +[source] +---- +zve64f +---- +| 6 +| 211 +| 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension). + +a| +[source] +---- +zve64x +---- +| 6 +| 212 +| 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW). + +a| +[source] +---- +zvfbfmin +---- +| 6 +| 213 +| 'Zvbfmin' (Vector BF16 Converts). + +a| +[source] +---- +zvfbfwma +---- +| 6 +| 214 +| 'Zvfbfwma' (Vector BF16 widening mul-add). + +a| +[source] +---- +zvfh +---- +| 6 +| 215 +| 'Zvfh' (Vector Half-Precision Floating-Point). + +a| +[source] +---- +zvfhmin +---- +| 6 +| 216 +| 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal). + +a| +[source] +---- +zvkb +---- +| 6 +| 217 +| 'Zvkb' (Vector Bit-manipulation used in Cryptography). + +a| +[source] +---- +zvkg +---- +| 6 +| 218 +| 'Zvkg' (Vector GCM instructions for Cryptography). + +a| +[source] +---- +zvkn +---- +| 6 +| 219 +| 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'). + +a| +[source] +---- +zvknc +---- +| 6 +| 220 +| 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc'). + +a| +[source] +---- +zvkned +---- +| 6 +| 221 +| 'Zvkned' (Vector AES Encryption & Decryption (Single Round)). + +a| +[source] +---- +zvkng +---- +| 6 +| 222 +| 'zvkng' (shorthand for 'Zvkn' and 'Zvkg'). + +a| +[source] +---- +zvknha +---- +| 6 +| 223 +| 'Zvknha' (Vector SHA-2 (SHA-256 only)). + +a| +[source] +---- +zvknhb +---- +| 6 +| 224 +| 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)). + +a| +[source] +---- +zvks +---- +| 6 +| 225 +| 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'). + +a| +[source] +---- +zvksc +---- +| 6 +| 226 +| 'Zvksc' (shorthand for 'Zvks' and 'Zvbc'). + +a| +[source] +---- +zvksed +---- +| 6 +| 227 +| 'Zvksed' (SM4 Block Cipher Instructions). + +a| +[source] +---- +zvksg +---- +| 6 +| 228 +| 'Zvksg' (shorthand for 'Zvks' and 'Zvkg'). + +a| +[source] +---- +zvksh +---- +| 6 +| 229 +| 'Zvksh' (SM3 Hash Function Instructions). + +a| +[source] +---- +zvkt +---- +| 6 +| 230 +| 'Zvkt' (Vector Data-Independent Execution Latency). + +a| +[source] +---- +zvl1024b +---- +| 6 +| 231 +| 'Zvl' (Minimum Vector Length) 1024. + +a| +[source] +---- +zvl128b +---- +| 6 +| 232 +| 'Zvl' (Minimum Vector Length) 128. + +a| +[source] +---- +zvl16384b +---- +| 6 +| 233 +| 'Zvl' (Minimum Vector Length) 16384. + +a| +[source] +---- +zvl2048b +---- +| 6 +| 234 +| 'Zvl' (Minimum Vector Length) 2048. + +a| +[source] +---- +zvl256b +---- +| 6 +| 235 +| 'Zvl' (Minimum Vector Length) 256. + +a| +[source] +---- +zvl32768b +---- +| 6 +| 236 +| 'Zvl' (Minimum Vector Length) 32768. + +a| +[source] +---- +zvl32b +---- +| 6 +| 237 +| 'Zvl' (Minimum Vector Length) 32. + +a| +[source] +---- +zvl4096b +---- +| 6 +| 238 +| 'Zvl' (Minimum Vector Length) 4096. + +a| +[source] +---- +zvl512b +---- +| 6 +| 239 +| 'Zvl' (Minimum Vector Length) 512. + +a| +[source] +---- +zvl64b +---- +| 6 +| 240 +| 'Zvl' (Minimum Vector Length) 64. + +a| +[source] +---- +zvl65536b +---- +| 6 +| 241 +| 'Zvl' (Minimum Vector Length) 65536. + +a| +[source] +---- +zvl8192b +---- +| 6 +| 242 +| 'Zvl' (Minimum Vector Length) 8192. +|===