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[RISCV] Add an OperandType for ordering for atomic pseudos. (#171744)
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3 files changed

+19
-6
lines changed

3 files changed

+19
-6
lines changed

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

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@@ -433,6 +433,8 @@ enum OperandType : unsigned {
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OPERAND_RTZARG,
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// Condition code used by select and short forward branch pseudos.
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OPERAND_COND_CODE,
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// Ordering for atomic pseudos.
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OPERAND_ATOMIC_ORDERING,
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// Vector policy operand.
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OPERAND_VEC_POLICY,
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// Vector SEW operand. Stores in log2(SEW).

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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@@ -3025,6 +3025,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
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case RISCVOp::OPERAND_COND_CODE:
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Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID;
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break;
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case RISCVOp::OPERAND_ATOMIC_ORDERING:
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Ok = isValidAtomicOrdering(Imm);
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break;
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case RISCVOp::OPERAND_VEC_POLICY:
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Ok = (Imm & (RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC)) ==
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Imm;

llvm/lib/Target/RISCV/RISCVInstrInfoA.td

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@@ -11,6 +11,14 @@
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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def ordering : RISCVOp {
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let OperandType = "OPERAND_ATOMIC_ORDERING";
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}
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
@@ -244,7 +252,7 @@ defm : AMOPat<"atomic_load_umin_i64", "AMOMINU_D", i64, [IsRV64]>;
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/// Pseudo AMOs
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class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$incr, ixlenimm:$ordering), []> {
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(ins GPR:$addr, GPR:$incr, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
@@ -253,7 +261,7 @@ class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
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class PseudoMaskedAMO
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: Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
@@ -263,7 +271,7 @@ class PseudoMaskedAMO
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class PseudoMaskedAMOMinMax
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: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$sextshamt,
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ixlenimm:$ordering), []> {
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ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
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"@earlyclobber $scratch2";
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let mayLoad = 1;
@@ -273,7 +281,7 @@ class PseudoMaskedAMOMinMax
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class PseudoMaskedAMOUMinUMax
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: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
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"@earlyclobber $scratch2";
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let mayLoad = 1;
@@ -419,7 +427,7 @@ defm : PseudoAMOPat<"atomic_load_nand_i64", PseudoAtomicLoadNand64, i64>;
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class PseudoCmpXchg
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: Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$cmpval, GPR:$newval, ixlenimm:$ordering), []> {
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(ins GPR:$addr, GPR:$cmpval, GPR:$newval, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
@@ -457,7 +465,7 @@ let Predicates = [HasStdExtZalrsc] in {
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def PseudoMaskedCmpXchg32
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: Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
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ixlenimm:$ordering), []> {
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ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;

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