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Revert "[AMDGPU][MC] GFX9 - Support NV bit in FLAT instructions in pre-GFX90A" (#166693)
Reverts llvm/llvm-project#154237 It breaks bot: https://lab.llvm.org/buildbot/#/builders/123/builds/30172
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9 files changed

+78
-1941
lines changed

9 files changed

+78
-1941
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2366,18 +2366,6 @@ def isGFX8GFX9NotGFX90A :
23662366
" Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
23672367
AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
23682368

2369-
// Pre-90A GFX9s allow the NV bit in FLAT instructions.
2370-
def isNVAllowedInFlat :
2371-
Predicate<"!Subtarget->hasGFX90AInsts() &&"
2372-
" Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
2373-
AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX90AInsts), (not FeatureGFX10Insts))>;
2374-
2375-
// GFX8 or GFX90A+ do not allow the NV bit in FLAT instructions.
2376-
def isNVNotAllowedInFlat :
2377-
Predicate<"(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) ||"
2378-
" ((Subtarget->getGeneration() == AMDGPUSubtarget::GFX9) && Subtarget->hasGFX90AInsts())">,
2379-
AssemblerPredicate <(any_of FeatureVolcanicIslands, FeatureGFX90AInsts)>;
2380-
23812369
def isGFX90AOnly :
23822370
Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
23832371
AssemblerPredicate<(all_of FeatureGFX90AInsts, (not FeatureGFX940Insts))>;

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1602,11 +1602,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
16021602

16031603
bool hasKernargPreload() const { return AMDGPU::hasKernargPreload(getSTI()); }
16041604

1605-
bool isFlatInstAndNVAllowed(const MCInst &Inst) const {
1606-
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
1607-
return (TSFlags & SIInstrFlags::FLAT) && isGFX9() && !isGFX90A();
1608-
}
1609-
16101605
AMDGPUTargetStreamer &getTargetStreamer() {
16111606
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
16121607
return static_cast<AMDGPUTargetStreamer &>(TS);
@@ -5375,7 +5370,7 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
53755370
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scale_offset")]);
53765371
Error(S, "scale_offset is not supported on this GPU");
53775372
}
5378-
if ((CPol & CPol::NV) && !isFlatInstAndNVAllowed(Inst)) {
5373+
if (CPol & CPol::NV) {
53795374
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
53805375
StringRef CStr(S.getPointer());
53815376
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("nv")]);
@@ -7150,13 +7145,6 @@ ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
71507145
unsigned Enabled = 0, Seen = 0;
71517146
for (;;) {
71527147
SMLoc S = getLoc();
7153-
7154-
if (isGFX9() && trySkipId("nv")) {
7155-
Enabled |= CPol::NV;
7156-
Seen |= CPol::NV;
7157-
continue;
7158-
}
7159-
71607148
bool Disabling;
71617149
unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);
71627150
if (!CPol)

‎llvm/lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 49 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
125125
bits<7> saddr;
126126
bits<10> vdst;
127127

128-
bits<6> cpol;
128+
bits<5> cpol;
129129

130130
// Only valid on gfx9
131131
bits<1> lds = ps.lds; // LDS DMA for global and scratch
@@ -2693,52 +2693,29 @@ class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
26932693
!subst("$sccb", !if(has_sccb, "$sccb",""), ps.AsmOperands);
26942694
}
26952695

2696-
class FLAT_Real_vi_ex_gfx9 <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
2697-
FLAT_Real_vi <op, ps, has_sccb> {
2698-
let AssemblerPredicate = isNVNotAllowedInFlat;
2699-
}
2700-
2701-
class FLAT_Real_gfx9 <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
2702-
FLAT_Real_vi <op, ps, has_sccb> {
2703-
let AssemblerPredicate = isNVAllowedInFlat;
2704-
let Subtarget = SIEncodingFamily.GFX9;
2705-
let DecoderNamespace = "GFX9";
2706-
let Inst{55} = cpol{CPolBit.NV}; // nv - GFX9 (pre-90A) uses bit 55 as the non-volatile bit.
2707-
}
2708-
2709-
multiclass FLAT_Real_mc_vi <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> {
2710-
def _vi: FLAT_Real_vi_ex_gfx9<op, ps, has_sccb>;
2711-
def _gfx9: FLAT_Real_gfx9<op, ps, has_sccb>;
2712-
}
2713-
27142696
multiclass FLAT_Real_AllAddr_vi<bits<7> op,
27152697
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
2716-
defm "" : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
2717-
defm _SADDR : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
2718-
}
2719-
2720-
multiclass FLAT_Real_AllAddr_vi_ex_gfx9<bits<7> op,
2721-
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
2722-
def _vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
2723-
def _SADDR_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
2698+
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
2699+
def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
27242700
}
27252701

27262702
class FLAT_Real_gfx940 <bits<7> op, FLAT_Pseudo ps> :
27272703
FLAT_Real <op, ps>,
27282704
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX940> {
27292705
let AssemblerPredicate = isGFX940Plus;
2730-
let DecoderNamespace = "GFX940";
2706+
let DecoderNamespace = "GFX9";
27312707
let Inst{13} = ps.sve;
27322708
let Inst{25} = !if(ps.has_sccb, cpol{CPolBit.SCC}, ps.sccbValue);
27332709
}
27342710

27352711
multiclass FLAT_Real_AllAddr_SVE_vi<bits<7> op> {
2736-
let OtherPredicates = [isGFX8GFX9NotGFX940] in {
2737-
defm "" : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(NAME)>;
2712+
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME)> {
2713+
let AssemblerPredicate = isGFX8GFX9NotGFX940;
2714+
let OtherPredicates = [isGFX8GFX9NotGFX940];
2715+
}
2716+
def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")> {
2717+
let DecoderNamespace = "GFX9";
27382718
}
2739-
2740-
defm _SADDR_vi : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")>;
2741-
27422719
let AssemblerPredicate = isGFX940Plus in {
27432720
def _VE_gfx940 : FLAT_Real_gfx940<op, !cast<FLAT_Pseudo>(NAME)>;
27442721
def _SVS_gfx940 : FLAT_Real_gfx940<op, !cast<FLAT_Pseudo>(NAME#"_SVS")>;
@@ -2751,11 +2728,11 @@ multiclass FLAT_Real_AllAddr_LDS<bits<7> op, bits<7> pre_gfx940_op,
27512728
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
27522729

27532730
let OtherPredicates = [isGFX8GFX9NotGFX940] in {
2754-
let AsmString = pre_gfx940_name # !cast<FLAT_Pseudo>(NAME).AsmOperands # " lds" in {
2755-
defm "" : FLAT_Real_mc_vi<pre_gfx940_op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
2731+
def _vi : FLAT_Real_vi<pre_gfx940_op, !cast<FLAT_Pseudo>(NAME), has_sccb> {
2732+
let AsmString = pre_gfx940_name # !cast<FLAT_Pseudo>(NAME).AsmOperands # " lds";
27562733
}
2757-
let AsmString = pre_gfx940_name # !cast<FLAT_Pseudo>(NAME#"_SADDR").AsmOperands # " lds" in {
2758-
defm _SADDR : FLAT_Real_mc_vi<pre_gfx940_op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
2734+
def _SADDR_vi : FLAT_Real_vi<pre_gfx940_op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb> {
2735+
let AsmString = pre_gfx940_name # !cast<FLAT_Pseudo>(NAME#"_SADDR").AsmOperands # " lds";
27592736
}
27602737
}
27612738

@@ -2771,66 +2748,47 @@ multiclass FLAT_Real_AllAddr_SVE_LDS<bits<7> op, bits<7> pre_gfx940_op> {
27712748
def _ST_gfx940 : FLAT_Real_gfx940<op, !cast<FLAT_Pseudo>(NAME#"_ST")>;
27722749
}
27732750

2774-
defm FLAT_LOAD_UBYTE_vi : FLAT_Real_mc_vi <0x10, FLAT_LOAD_UBYTE>;
2775-
defm FLAT_LOAD_SBYTE_vi : FLAT_Real_mc_vi <0x11, FLAT_LOAD_SBYTE>;
2776-
defm FLAT_LOAD_USHORT_vi : FLAT_Real_mc_vi <0x12, FLAT_LOAD_USHORT>;
2777-
defm FLAT_LOAD_SSHORT_vi : FLAT_Real_mc_vi <0x13, FLAT_LOAD_SSHORT>;
2778-
defm FLAT_LOAD_DWORD_vi : FLAT_Real_mc_vi <0x14, FLAT_LOAD_DWORD>;
2779-
defm FLAT_LOAD_DWORDX2_vi : FLAT_Real_mc_vi <0x15, FLAT_LOAD_DWORDX2>;
2780-
defm FLAT_LOAD_DWORDX4_vi : FLAT_Real_mc_vi <0x17, FLAT_LOAD_DWORDX4>;
2781-
defm FLAT_LOAD_DWORDX3_vi : FLAT_Real_mc_vi <0x16, FLAT_LOAD_DWORDX3>;
2782-
2783-
defm FLAT_STORE_BYTE_vi : FLAT_Real_mc_vi <0x18, FLAT_STORE_BYTE>;
2784-
defm FLAT_STORE_BYTE_D16_HI_vi : FLAT_Real_mc_vi <0x19, FLAT_STORE_BYTE_D16_HI>;
2785-
defm FLAT_STORE_SHORT_vi : FLAT_Real_mc_vi <0x1a, FLAT_STORE_SHORT>;
2786-
defm FLAT_STORE_SHORT_D16_HI_vi : FLAT_Real_mc_vi <0x1b, FLAT_STORE_SHORT_D16_HI>;
2787-
defm FLAT_STORE_DWORD_vi : FLAT_Real_mc_vi <0x1c, FLAT_STORE_DWORD>;
2788-
defm FLAT_STORE_DWORDX2_vi : FLAT_Real_mc_vi <0x1d, FLAT_STORE_DWORDX2>;
2789-
defm FLAT_STORE_DWORDX4_vi : FLAT_Real_mc_vi <0x1f, FLAT_STORE_DWORDX4>;
2790-
defm FLAT_STORE_DWORDX3_vi : FLAT_Real_mc_vi <0x1e, FLAT_STORE_DWORDX3>;
2791-
2792-
defm FLAT_LOAD_UBYTE_D16_vi : FLAT_Real_mc_vi <0x20, FLAT_LOAD_UBYTE_D16>;
2793-
defm FLAT_LOAD_UBYTE_D16_HI_vi : FLAT_Real_mc_vi <0x21, FLAT_LOAD_UBYTE_D16_HI>;
2794-
defm FLAT_LOAD_SBYTE_D16_vi : FLAT_Real_mc_vi <0x22, FLAT_LOAD_SBYTE_D16>;
2795-
defm FLAT_LOAD_SBYTE_D16_HI_vi : FLAT_Real_mc_vi <0x23, FLAT_LOAD_SBYTE_D16_HI>;
2796-
defm FLAT_LOAD_SHORT_D16_vi : FLAT_Real_mc_vi <0x24, FLAT_LOAD_SHORT_D16>;
2797-
defm FLAT_LOAD_SHORT_D16_HI_vi : FLAT_Real_mc_vi <0x25, FLAT_LOAD_SHORT_D16_HI>;
2751+
def FLAT_LOAD_UBYTE_vi : FLAT_Real_vi <0x10, FLAT_LOAD_UBYTE>;
2752+
def FLAT_LOAD_SBYTE_vi : FLAT_Real_vi <0x11, FLAT_LOAD_SBYTE>;
2753+
def FLAT_LOAD_USHORT_vi : FLAT_Real_vi <0x12, FLAT_LOAD_USHORT>;
2754+
def FLAT_LOAD_SSHORT_vi : FLAT_Real_vi <0x13, FLAT_LOAD_SSHORT>;
2755+
def FLAT_LOAD_DWORD_vi : FLAT_Real_vi <0x14, FLAT_LOAD_DWORD>;
2756+
def FLAT_LOAD_DWORDX2_vi : FLAT_Real_vi <0x15, FLAT_LOAD_DWORDX2>;
2757+
def FLAT_LOAD_DWORDX4_vi : FLAT_Real_vi <0x17, FLAT_LOAD_DWORDX4>;
2758+
def FLAT_LOAD_DWORDX3_vi : FLAT_Real_vi <0x16, FLAT_LOAD_DWORDX3>;
2759+
2760+
def FLAT_STORE_BYTE_vi : FLAT_Real_vi <0x18, FLAT_STORE_BYTE>;
2761+
def FLAT_STORE_BYTE_D16_HI_vi : FLAT_Real_vi <0x19, FLAT_STORE_BYTE_D16_HI>;
2762+
def FLAT_STORE_SHORT_vi : FLAT_Real_vi <0x1a, FLAT_STORE_SHORT>;
2763+
def FLAT_STORE_SHORT_D16_HI_vi : FLAT_Real_vi <0x1b, FLAT_STORE_SHORT_D16_HI>;
2764+
def FLAT_STORE_DWORD_vi : FLAT_Real_vi <0x1c, FLAT_STORE_DWORD>;
2765+
def FLAT_STORE_DWORDX2_vi : FLAT_Real_vi <0x1d, FLAT_STORE_DWORDX2>;
2766+
def FLAT_STORE_DWORDX4_vi : FLAT_Real_vi <0x1f, FLAT_STORE_DWORDX4>;
2767+
def FLAT_STORE_DWORDX3_vi : FLAT_Real_vi <0x1e, FLAT_STORE_DWORDX3>;
2768+
2769+
def FLAT_LOAD_UBYTE_D16_vi : FLAT_Real_vi <0x20, FLAT_LOAD_UBYTE_D16>;
2770+
def FLAT_LOAD_UBYTE_D16_HI_vi : FLAT_Real_vi <0x21, FLAT_LOAD_UBYTE_D16_HI>;
2771+
def FLAT_LOAD_SBYTE_D16_vi : FLAT_Real_vi <0x22, FLAT_LOAD_SBYTE_D16>;
2772+
def FLAT_LOAD_SBYTE_D16_HI_vi : FLAT_Real_vi <0x23, FLAT_LOAD_SBYTE_D16_HI>;
2773+
def FLAT_LOAD_SHORT_D16_vi : FLAT_Real_vi <0x24, FLAT_LOAD_SHORT_D16>;
2774+
def FLAT_LOAD_SHORT_D16_HI_vi : FLAT_Real_vi <0x25, FLAT_LOAD_SHORT_D16_HI>;
27982775

27992776
multiclass FLAT_Real_Atomics_vi <bits<7> op,
28002777
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
28012778
defvar ps = !cast<FLAT_Pseudo>(NAME);
2802-
defm "" : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
2803-
defm _RTN : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
2804-
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN_agpr"), has_sccb>;
2805-
}
2806-
2807-
multiclass FLAT_Real_Atomics_vi_ex_gfx9 <bits<7> op,
2808-
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
2809-
defvar ps = !cast<FLAT_Pseudo>(NAME);
2810-
def _vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
2811-
def _RTN_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
2812-
2813-
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN_agpr"), has_sccb>;
2779+
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
2780+
def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
2781+
def _RTN_agpr_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN_agpr"), has_sccb>;
28142782
}
28152783

28162784
multiclass FLAT_Global_Real_Atomics_vi<bits<7> op,
28172785
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> :
28182786
FLAT_Real_AllAddr_vi<op, has_sccb> {
2819-
defm _RTN : FLAT_Real_mc_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
2820-
defm _SADDR_RTN : FLAT_Real_mc_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
2821-
2822-
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_RTN_agpr"), has_sccb>;
2823-
def _SADDR_RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN_agpr"), has_sccb>;
2824-
}
2825-
2826-
multiclass FLAT_Global_Real_Atomics_vi_ex_gfx9<bits<7> op,
2827-
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> :
2828-
FLAT_Real_AllAddr_vi_ex_gfx9<op, has_sccb> {
2829-
def _RTN_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
2830-
def _SADDR_RTN_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
2787+
def _RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
2788+
def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
28312789

2832-
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_RTN_agpr"), has_sccb>;
2833-
def _SADDR_RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN_agpr"), has_sccb>;
2790+
def _RTN_agpr_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN_agpr"), has_sccb>;
2791+
def _SADDR_RTN_agpr_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN_agpr"), has_sccb>;
28342792
}
28352793

28362794
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40>;
@@ -2992,10 +2950,10 @@ let AssemblerPredicate = isGFX940Plus in {
29922950
defm GLOBAL_ATOMIC_ADD_F64 : FLAT_Global_Real_Atomics_gfx940<0x4f>;
29932951
defm GLOBAL_ATOMIC_MIN_F64 : FLAT_Global_Real_Atomics_gfx940<0x50>;
29942952
defm GLOBAL_ATOMIC_MAX_F64 : FLAT_Global_Real_Atomics_gfx940<0x51>;
2995-
defm FLAT_ATOMIC_ADD_F32 : FLAT_Real_Atomics_vi_ex_gfx9<0x4d>;
2996-
defm FLAT_ATOMIC_PK_ADD_F16 : FLAT_Real_Atomics_vi_ex_gfx9<0x4e>;
2997-
defm FLAT_ATOMIC_PK_ADD_BF16 : FLAT_Real_Atomics_vi_ex_gfx9<0x52>;
2998-
defm GLOBAL_ATOMIC_PK_ADD_BF16 : FLAT_Global_Real_Atomics_vi_ex_gfx9<0x52>;
2953+
defm FLAT_ATOMIC_ADD_F32 : FLAT_Real_Atomics_vi<0x4d>;
2954+
defm FLAT_ATOMIC_PK_ADD_F16 : FLAT_Real_Atomics_vi<0x4e>;
2955+
defm FLAT_ATOMIC_PK_ADD_BF16 : FLAT_Real_Atomics_vi<0x52>;
2956+
defm GLOBAL_ATOMIC_PK_ADD_BF16 : FLAT_Global_Real_Atomics_vi<0x52>;
29992957
} // End AssemblerPredicate = isGFX940Plus
30002958

30012959
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -186,12 +186,8 @@ void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
186186
O << " dlc";
187187
if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
188188
O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
189-
if (Imm & ~CPol::ALL_pregfx12) {
190-
if ((Imm & CPol::NV) && AMDGPU::isGFX9(STI) && !AMDGPU::isGFX90A(STI))
191-
O << " nv";
192-
else
193-
O << " /* unexpected cache policy bit */";
194-
}
189+
if (Imm & ~CPol::ALL_pregfx12)
190+
O << " /* unexpected cache policy bit */";
195191
}
196192

197193
void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,

‎llvm/test/MC/AMDGPU/gfx90a_err.s‎

Lines changed: 0 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -674,46 +674,3 @@ v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0]
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v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1]
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
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// nv bit in FLAT instructions
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flat_load_ubyte v5, v[2:3] offset:4095 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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flat_load_ubyte a5, v[2:3] offset:4095 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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flat_store_dword v[2:3], v5 offset:4095 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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flat_store_dword v[2:3], a5 offset:4095 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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flat_atomic_add_f64 v[0:1], v[2:3] offset:4095 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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global_load_ubyte v5, v[2:3], off offset:-1 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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global_store_byte v[2:3], v5, off offset:-1 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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global_atomic_add v[2:3], v5, off nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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global_atomic_swap a1, v[2:3], a2, off glc nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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global_atomic_swap_x2 v[2:3], v[4:5], off nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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global_atomic_swap_x2 v[2:3], a[4:5], off nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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scratch_load_ubyte v5, off, s2 offset:-1 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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scratch_load_ubyte a5, off, s2 offset:-1 nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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scratch_store_dword v2, v3, off nv
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// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
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