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[SYCL] Allow _Bitint of size greater than 128 bits when -fintelfpga is used (#6152)
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10 files changed

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10 files changed

+128
-3
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‎clang/include/clang/Basic/LangOptions.def‎

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Original file line numberDiff line numberDiff line change
@@ -269,6 +269,7 @@ LANGOPT(GPUExcludeWrongSideOverloads, 1, 0, "always exclude wrong side overloads
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LANGOPT(SYCLIsDevice , 1, 0, "Generate code for SYCL device")
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LANGOPT(SYCLIsHost , 1, 0, "SYCL host compilation")
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LANGOPT(IntelFPGA , 1, 0, "Perform ahead-of-time compilation for FPGA")
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LANGOPT(SYCLAllowFuncPtr , 1, 0, "Allow function pointers in SYCL device code")
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LANGOPT(SYCLStdLayoutKernelParams, 1, 0, "Enable standard layout requirement for SYCL kernel parameters")
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LANGOPT(SYCLUnnamedLambda , 1, 0, "Allow unnamed lambda SYCL kernels")

‎clang/include/clang/Driver/Options.td‎

Lines changed: 2 additions & 1 deletion
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@@ -2754,7 +2754,8 @@ defm strict_vtable_pointers : BoolFOption<"strict-vtable-pointers",
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NegFlag<SetFalse>>;
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def fstrict_overflow : Flag<["-"], "fstrict-overflow">, Group<f_Group>;
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def fintelfpga : Flag<["-"], "fintelfpga">, Group<f_Group>,
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Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">;
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Flags<[CC1Option, CoreOption]>, MarshallingInfoFlag<LangOpts<"IntelFPGA">>,
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HelpText<"Perform ahead-of-time compilation for FPGA">;
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def fsycl_device_only : Flag<["-"], "fsycl-device-only">, Flags<[CoreOption]>,
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HelpText<"Compile SYCL kernels for device">;
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def fsycl_targets_EQ : CommaJoined<["-"], "fsycl-targets=">, Flags<[NoXarchOption, CC1Option, CoreOption]>,

‎clang/lib/Driver/ToolChains/Clang.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4965,8 +4965,11 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
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HasFPGA = true;
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break;
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}
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if (HasFPGA)
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if (HasFPGA) {
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CmdArgs.push_back("-fsycl-disable-range-rounding");
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// Pass -fintelfpga to both the host and device SYCL compilations if set.
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CmdArgs.push_back("-fintelfpga");
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}
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// Add any options that are needed specific to SYCL offload while
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// performing the host side compilation.

‎clang/lib/Sema/SemaType.cpp‎

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@@ -2292,7 +2292,7 @@ QualType Sema::BuildBitIntType(bool IsUnsigned, Expr *BitWidth,
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}
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const TargetInfo &TI = getASTContext().getTargetInfo();
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if (NumBits > TI.getMaxBitIntWidth()) {
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if (NumBits > TI.getMaxBitIntWidth() && !Context.getLangOpts().IntelFPGA) {
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Diag(Loc, diag::err_bit_int_max_size)
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<< IsUnsigned << static_cast<uint64_t>(TI.getMaxBitIntWidth());
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return QualType();

‎clang/test/CodeGenSYCL/no-opaque-ptrs-sycl-host-intelfpga-bitint.cpp‎

Lines changed: 23 additions & 0 deletions
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@@ -0,0 +1,23 @@
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// RUN: %clang_cc1 -no-opaque-pointers -fsycl-is-host -fintelfpga -triple x86_64 -emit-llvm %s -o - | FileCheck %s
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// This test checks that we generate appropriate code for division
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// operations of _BitInts of size greater than 128 bits, since it
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// is allowed when -fintelfpga is enabled.
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// CHECK: define{{.*}} void @_Z3fooDB211_S_(i211* {{.*}} sret(i211) align 8 %agg.result, i211* {{.*}} byval(i211) align 8 %[[ARG1:[0-9]+]], i211* {{.*}} byval(i211) align 8 %[[ARG2:[0-9]+]])
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signed _BitInt(211) foo(signed _BitInt(211) a, signed _BitInt(211) b) {
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// CHECK: %[[VAR_A:a]].addr = alloca i211, align 8
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// CHECK: %[[VAR_B:b]].addr = alloca i211, align 8
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// CHECK: %[[VAR_A]] = load i211, i211* %[[ARG1]], align 8
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// CHECK: %[[VAR_B]] = load i211, i211* %[[ARG2]], align 8
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// CHECK: store i211 %[[VAR_A]], i211* %[[VAR_A]].addr, align 8
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// CHECK: store i211 %[[VAR_B]], i211* %[[VAR_B]].addr, align 8
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// CHECK: %[[TEMP1:[0-9]+]] = load i211, i211* %[[VAR_A]].addr, align 8
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// CHECK: %[[TEMP2:[0-9]+]] = load i211, i211* %[[VAR_B]].addr, align 8
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// CHECK: %div = sdiv i211 %[[TEMP1]], %[[TEMP2]]
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// CHECK: store i211 %div, i211* %agg.result, align 8
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// CHECK: %[[RES:[0-9+]]] = load i211, i211* %agg.result, align 8
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// CHECK: store i211 %[[RES]], i211* %agg.result, align 8
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// CHECK: ret void
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return a / b;
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}

‎clang/test/CodeGenSYCL/no-opaque-ptrs-sycl-intelfpga-bitint.cpp‎

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@@ -0,0 +1,26 @@
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// RUN: %clang_cc1 -no-opaque-pointers -fsycl-is-device -fintelfpga -triple spir64_fpga -IInputs -emit-llvm %s -o - | FileCheck %s
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// This test checks that we generate appropriate code for division
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// operations of _BitInts of size greater than 128 bits, since it
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// is allowed when -fintelfpga is enabled.
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#include "Inputs/sycl.hpp"
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// CHECK: define{{.*}} void @_Z3fooDB211_S_(i211 addrspace(4)* {{.*}} sret(i211) align 8 %agg.result, i211* {{.*}} byval(i211) align 8 %[[ARG1:[0-9]+]], i211* {{.*}} byval(i211) align 8 %[[ARG2:[0-9]+]])
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signed _BitInt(211) foo(signed _BitInt(211) a, signed _BitInt(211) b) {
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// CHECK: %[[VAR_A:a]] = load i211, i211* %[[ARG1]], align 8
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// CHECK: %[[VAR_B:b]] = load i211, i211* %[[ARG2]], align 8
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// CHECK: %[[RES:div]] = sdiv i211 %[[VAR_A]], %[[VAR_B]]
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// CHECK: store i211 %[[RES]], i211 addrspace(4)* %agg.result, align 8
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// CHECK: ret void
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return a / b;
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}
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int main() {
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sycl::handler h;
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auto lambda = []() {
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_BitInt(211) a, b = 3, c = 4;
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a = foo(b, c);
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};
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h.single_task(lambda);
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}

‎clang/test/CodeGenSYCL/sycl-host-intelfpga-bitint.cpp‎

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@@ -0,0 +1,23 @@
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// RUN: %clang_cc1 -opaque-pointers -fsycl-is-host -fintelfpga -triple x86_64 -emit-llvm %s -o - | FileCheck %s
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// This test checks that we generate appropriate code for division
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// operations of _BitInts of size greater than 128 bits, since it
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// is allowed when -fintelfpga is enabled.
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// CHECK: define{{.*}} void @_Z3fooDB211_S_(ptr {{.*}} sret(i211) align 8 %agg.result, ptr {{.*}} byval(i211) align 8 %[[ARG1:[0-9]+]], ptr {{.*}} byval(i211) align 8 %[[ARG2:[0-9]+]])
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signed _BitInt(211) foo(signed _BitInt(211) a, signed _BitInt(211) b) {
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// CHECK: %[[VAR_A:a]].addr = alloca i211, align 8
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// CHECK: %[[VAR_B:b]].addr = alloca i211, align 8
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// CHECK: %[[VAR_A]] = load i211, ptr %[[ARG1]], align 8
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// CHECK: %[[VAR_B]] = load i211, ptr %[[ARG2]], align 8
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// CHECK: store i211 %[[VAR_A]], ptr %[[VAR_A]].addr, align 8
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// CHECK: store i211 %[[VAR_B]], ptr %[[VAR_B]].addr, align 8
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// CHECK: %[[TEMP1:[0-9]+]] = load i211, ptr %[[VAR_A]].addr, align 8
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// CHECK: %[[TEMP2:[0-9]+]] = load i211, ptr %[[VAR_B]].addr, align 8
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// CHECK: %div = sdiv i211 %[[TEMP1]], %[[TEMP2]]
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// CHECK: store i211 %div, ptr %agg.result, align 8
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// CHECK: %[[RES:[0-9+]]] = load i211, ptr %agg.result, align 8
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// CHECK: store i211 %[[RES]], ptr %agg.result, align 8
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// CHECK: ret void
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return a / b;
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}

‎clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp‎

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@@ -0,0 +1,26 @@
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// RUN: %clang_cc1 -opaque-pointers -fsycl-is-device -fintelfpga -triple spir64_fpga -IInputs -emit-llvm %s -o - | FileCheck %s
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// This test checks that we generate appropriate code for division
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// operations of _BitInts of size greater than 128 bits, since it
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// is allowed when -fintelfpga is enabled.
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#include "Inputs/sycl.hpp"
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// CHECK: define{{.*}} void @_Z3fooDB211_S_(ptr addrspace(4) {{.*}} sret(i211) align 8 %agg.result, ptr {{.*}} byval(i211) align 8 %[[ARG1:[0-9]+]], ptr {{.*}} byval(i211) align 8 %[[ARG2:[0-9]+]])
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signed _BitInt(211) foo(signed _BitInt(211) a, signed _BitInt(211) b) {
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// CHECK: %[[VAR_A:a]] = load i211, ptr %[[ARG1]], align 8
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// CHECK: %[[VAR_B:b]] = load i211, ptr %[[ARG2]], align 8
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// CHECK: %[[RES:div]] = sdiv i211 %[[VAR_A]], %[[VAR_B]]
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// CHECK: store i211 %[[RES]], ptr addrspace(4) %agg.result, align 8
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// CHECK: ret void
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return a / b;
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}
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int main() {
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sycl::handler h;
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auto lambda = []() {
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_BitInt(211) a, b = 3, c = 4;
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a = foo(b, c);
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};
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h.single_task(lambda);
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}

‎clang/test/Driver/sycl-offload-intelfpga.cpp‎

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@@ -20,6 +20,12 @@
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// RUN: | FileCheck -check-prefix=CHK-TOOLS-INTELFPGA-G0 %s
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// CHK-TOOLS-INTELFPGA-G0-NOT: clang{{.*}} "-debug-info-kind=constructor"
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/// -fintelfpga passes it to host and device cc1 compilations
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// RUN: %clangxx -### -fsycl -fintelfpga %s 2>&1 \
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// RUN: | FileCheck -check-prefix=CHK-HOST-DEVICE %s
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// CHK-HOST-DEVICE: clang{{.*}} "-cc1"{{.*}} "-fsycl-is-device"{{.*}} "-fintelfpga"
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// CHK-HOST-DEVICE: clang{{.*}} "-cc1"{{.*}} "-fintelfpga"{{.*}} "-fsycl-is-host"
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/// FPGA target implies -fsycl-disable-range-rounding
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// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %s 2>&1 \
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// RUN: | FileCheck -check-prefix=CHK-RANGE-ROUNDING %s

‎clang/test/SemaSYCL/sycl-intelfpga.cpp‎

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@@ -0,0 +1,16 @@
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// RUN: %clang_cc1 -fsycl-is-device -fintelfpga -verify=device-intelfpga -fsyntax-only %s
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// RUN: %clang_cc1 -fsycl-is-host -fintelfpga -verify=host-intelfpga -fsyntax-only %s
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// RUN: %clang_cc1 -fsycl-is-device -verify=device -fsyntax-only %s
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// RUN: %clang_cc1 -fsycl-is-host -verify=host -fsyntax-only %s
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// Tests that we do not issue errors for _Bitints of size greater than 128
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// when -fintelfpga is enabled. The backend is expected to be able to handle
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// this. When -fintelfpga is not passed, we continue to diagnose.
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// device-intelfpga-no-diagnostics
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// host-intelfpga-no-diagnostics
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// device-error@+2 3{{signed _BitInt of bit sizes greater than 128 not supported}}
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// host-error@+1 3{{signed _BitInt of bit sizes greater than 128 not supported}}
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signed _BitInt(211) foo(signed _BitInt(211) a, signed _BitInt(211) b) {
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return a / b;
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}

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