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authored andcommittedApr 23, 2024
Fix resolution of 2D block writes with cacheopts
Pick proper operand destination argument index when resolving 2D block writes with cacheopts. Add cacheopt 2D block write and read tests. (cherry picked from commit e50b775)
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3 files changed

+55
-9
lines changed

3 files changed

+55
-9
lines changed
 

‎IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1064,7 +1064,7 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
10641064
Value* imageResHeight = CI.getArgOperand(2);
10651065
Value* imageResPitch = CI.getArgOperand(3);
10661066

1067-
SmallVector<Value*, 13> args;
1067+
SmallVector<Value*, 14> args;
10681068
args.push_back(imageResBaseoffset);
10691069
args.push_back(imageResWidth);
10701070
args.push_back(imageResHeight);
@@ -1114,17 +1114,12 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
11141114
}
11151115
else
11161116
{
1117-
uint32_t blockWriteDstOperandId = 5;
1118-
if (hasCacheOpts)
1119-
{
1120-
blockWriteDstOperandId = 6;
1121-
}
1122-
Value *dst = CI.getArgOperand(blockWriteDstOperandId);
1123-
args.push_back(dst);
1117+
Value *srcVal = CI.getArgOperand(5);
1118+
args.push_back(srcVal);
11241119
BlockFunc = GenISAIntrinsic::getDeclaration(
11251120
CI.getCalledFunction()->getParent(),
11261121
GenISAIntrinsic::GenISA_LSC2DBlockWrite,
1127-
dst->getType());
1122+
srcVal->getType());
11281123
}
11291124

11301125
Instruction* BlockOp = CallInst::Create(BlockFunc, args, "", &CI);

‎IGC/Compiler/tests/LSCFuncsResolution/subgroup_block_read.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,11 @@ define spir_kernel void @test_lsc(i64 %base, <2 x i32> %cord) {
5555
; CHECK: call <32 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v32i16(i64 %base, i32 0, i32 7, i32 0, i32 [[TMP13]], i32 [[TMP14]], i32 16, i32 16, i32 32, i32 2, i1 false, i1 true, i32 0)
5656
%7 = call <32 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k32v2(i64 %base, i32 0, i32 7, i32 0, <2 x i32> %cord)
5757

58+
; CHECK: [[TMP15:%.*]] = extractelement <2 x i32> %cord, i32 0
59+
; CHECK: [[TMP16:%.*]] = extractelement <2 x i32> %cord, i32 1
60+
; CHECK: call <32 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v32i16(i64 %base, i32 0, i32 7, i32 0, i32 [[TMP15]], i32 [[TMP16]], i32 16, i32 16, i32 16, i32 2, i1 false, i1 false, i32 4)
61+
%8 = call <32 x i16> @__builtin_IB_subgroup_block_read_flat_cacheopts_u16_m16k16v2(i64 %base, i32 0, i32 7, i32 0, <2 x i32> %cord, i32 4)
62+
5863
; CHECK: ret void
5964
ret void
6065
}
@@ -69,6 +74,8 @@ declare <16 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k16v2(i6
6974
declare <16 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k32(i64, i32, i32, i32, <2 x i32>)
7075
declare <32 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k32v2(i64, i32, i32, i32, <2 x i32>)
7176

77+
declare <32 x i16> @__builtin_IB_subgroup_block_read_flat_cacheopts_u16_m16k16v2(i64, i32, i32, i32, <2 x i32>, i32)
78+
7279
!igc.functions = !{!0}
7380

7481
!0 = !{void (i64, <2 x i32>)* @test_lsc, !1}
Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2024 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
;
9+
; RUN: igc_opt -enable-debugify --igc-lsc-funcs-translation -platformpvc -S < %s 2>&1 | FileCheck %s
10+
; ------------------------------------------------
11+
; LSCFuncsResolution
12+
; ------------------------------------------------
13+
14+
; Test checks that lsc builtins are lowered
15+
16+
; Debug-info related check
17+
; CHECK-NOT: WARNING
18+
; CHECK: CheckModuleDebugify: PASS
19+
20+
define spir_kernel void @test_lsc(i64 %base_dst, <2 x i32> %coord, <8 x i32> %val_to_store) {
21+
; CHECK-LABEL: @test_lsc(
22+
23+
; CHECK: [[XOFF0:%.*]] = extractelement <2 x i32> %coord, i32 0
24+
; CHECK: [[YOFF0:%.*]] = extractelement <2 x i32> %coord, i32 1
25+
; CHECK: call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 %base_dst, i32 127, i32 7, i32 127, i32 [[XOFF0]], i32 [[YOFF0]], i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, i32 0, <8 x i32> %val_to_store)
26+
call void @__builtin_IB_subgroup_block_write_flat_u32_wi8_m8k16v1(i64 %base_dst, i32 127, i32 7, i32 127, <2 x i32> %coord, <8 x i32> %val_to_store)
27+
28+
; CHECK: [[XOFF1:%.*]] = extractelement <2 x i32> %coord, i32 0
29+
; CHECK: [[YOFF1:%.*]] = extractelement <2 x i32> %coord, i32 1
30+
; CHECK: call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 %base_dst, i32 127, i32 7, i32 127, i32 [[XOFF1]], i32 [[YOFF1]], i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, i32 2, <8 x i32> %val_to_store)
31+
call void @__builtin_IB_subgroup_block_write_flat_cacheopts_u32_wi8_m8k16v1(i64 %base_dst, i32 127, i32 7, i32 127, <2 x i32> %coord, <8 x i32> %val_to_store, i32 2)
32+
33+
; CHECK: ret void
34+
ret void;
35+
}
36+
37+
declare void @__builtin_IB_subgroup_block_write_flat_u32_wi8_m8k16v1(i64, i32, i32, i32, <2 x i32>, <8 x i32>)
38+
declare void @__builtin_IB_subgroup_block_write_flat_cacheopts_u32_wi8_m8k16v1(i64, i32, i32, i32, <2 x i32>, <8 x i32>, i32)
39+
40+
!igc.functions = !{!0}
41+
!0 = !{void (i64, <2 x i32>, <8 x i32>)* @test_lsc, !1}
42+
!1 = !{!2, !3}
43+
!2 = !{!"function_type", i32 0}
44+
!3 = !{!"sub_group_size", i32 16}

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