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weiyu-chengfxbot
weiyu-chen
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refactor implementation of IEEE FP64 macros
Change-Id: Ia211d37afdf8f8f66d44af9c8c6b1d425e06d1b1
1 parent e1fae8f commit 3492d19

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‎visa/TranslationInterface.cpp

+24-51
Original file line numberDiff line numberDiff line change
@@ -713,16 +713,10 @@ int IR_Builder::translateVISAArithmeticDoubleInst(ISA_Opcode opcode, Common_ISA_
713713
G4_CondMod *condModOverflow = createCondMod(Mod_o, tmpFlag->getRegVar(), 0);
714714
inst->setCondMod(condModOverflow);
715715

716-
bool generateIf = true;
717-
718-
if (generateIf)
719716
{
720717
// if
721718
G4_Predicate *predicateFlagReg = createPredicate(PredState_Minus, tmpFlag->getRegVar(), 0, predCtrlValue);
722719
inst = createIf(predicateFlagReg, exsize, instOpt);
723-
}
724-
{
725-
726720

727721
// madm (4) r9.acc3 r0.noacc r6.noacc r8.acc2 {Align16, N1/N2}
728722
G4_SrcRegRegion *t0SrcOpnd = createSrcRegRegion(tsrc0);
@@ -815,24 +809,23 @@ int IR_Builder::translateVISAArithmeticDoubleInst(ISA_Opcode opcode, Common_ISA_
815809
t12SrcOpnd1->setAccRegSel(ACC2);
816810
inst = createInst(NULL, G4_madm, NULL, false, exsize, t8DstOpnd2, t9SrcOpnd1x1,
817811
t11SrcOpnd1, t12SrcOpnd1, madmInstOpt, line_no);
818-
}
819812

820-
if (generateIf && !hasDefaultRoundDenorm)
821-
{
822-
// else (8) {Q1/Q2}
823-
inst = createElse(exsize, instOpt);
813+
if (!hasDefaultRoundDenorm)
814+
{
815+
// else (8) {Q1/Q2}
816+
inst = createElse(exsize, instOpt);
824817

825-
// restore cr0.0 {NoMask}
826-
G4_DstRegRegion *cr0DstRegOpndForRestoreElseInst = createDstRegRegion(regDstCR0);
827-
auto tmpSrcOpndForCR0OnElse = Create_Src_Opnd_From_Dcl(regCR0, getRegionScalar());
828-
inst = createInst(NULL, G4_mov, NULL, false, 1, cr0DstRegOpndForRestoreElseInst, tmpSrcOpndForCR0OnElse,
829-
NULL, InstOpt_WriteEnable, line_no);
830-
}
818+
// restore cr0.0 {NoMask}
819+
G4_DstRegRegion *cr0DstRegOpndForRestoreElseInst = createDstRegRegion(regDstCR0);
820+
auto tmpSrcOpndForCR0OnElse = Create_Src_Opnd_From_Dcl(regCR0, getRegionScalar());
821+
inst = createInst(NULL, G4_mov, NULL, false, 1, cr0DstRegOpndForRestoreElseInst, tmpSrcOpndForCR0OnElse,
822+
NULL, InstOpt_WriteEnable, line_no);
823+
}
831824

832-
if (generateIf)
833-
{
834-
// endif (8) {Q1/Q2}
835-
inst = createEndif(exsize, instOpt);
825+
{
826+
// endif (8) {Q1/Q2}
827+
inst = createEndif(exsize, instOpt);
828+
}
836829
}
837830
}; //for loop
838831

@@ -1613,24 +1606,18 @@ int IR_Builder::translateVISAArithmeticDoubleSQRTInst(ISA_Opcode opcode, Common_
16131606
inst = createMathInst(NULL, false, exsize, dst0, src0, src1, MATH_RSQRTM, madmInstOpt, line_no);
16141607
inst->setCondMod(condModOverflow);
16151608

1616-
bool generateIf = true;
1617-
1618-
if (generateIf)
16191609
{
16201610
// if
16211611
G4_Predicate *predicateFlagReg = createPredicate(PredState_Minus, flagReg->getRegVar(), 0, predCtrlValue);
16221612
inst = createIf(predicateFlagReg, exsize, instOpt);
1623-
}
16241613

1625-
{
16261614
// madm (4) r9.acc3 r0.noacc r2(r8).noacc r7.acc2 {Align16, N1/N2}
16271615
dst0 = createDstRegRegion(tdst9); dst0->setAccRegSel(ACC3);
16281616
src0 = createSrcRegRegion(csrc0); src0->setAccRegSel(NOACC);
16291617
src1 = createSrcRegRegion(csrc2); src1->setAccRegSel(NOACC);
16301618
src2 = createSrcRegRegion(tsrc7); src2->setAccRegSel(ACC2);
16311619
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
16321620

1633-
16341621
// madm (4) r11.acc4 r0.noacc r6.noacc r7.acc2 {Align16, N1/N2}
16351622
dst0 = createDstRegRegion(tdst11); dst0->setAccRegSel(ACC4);
16361623
src0 = createSrcRegRegion(csrc0); src0->setAccRegSel(NOACC);
@@ -1646,7 +1633,6 @@ int IR_Builder::translateVISAArithmeticDoubleSQRTInst(ISA_Opcode opcode, Common_
16461633
src2 = createSrcRegRegion(tsrc7); src2->setAccRegSel(ACC2);
16471634
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
16481635

1649-
16501636
// madm (4) r10.acc5 r2(r8).noacc -r11.acc4 r9.acc3 {Align16, N1/N2}
16511637
dst0 = createDstRegRegion(tdst10); dst0->setAccRegSel(ACC5);
16521638
src0 = createSrcRegRegion(csrc2); src0->setAccRegSel(NOACC);
@@ -1663,55 +1649,48 @@ int IR_Builder::translateVISAArithmeticDoubleSQRTInst(ISA_Opcode opcode, Common_
16631649
neg_src1->setAccRegSel(src1->getAccRegSel());
16641650
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, neg_src1, src2, madmInstOpt, line_no);
16651651

1666-
16671652
// madm (4) r8.acc6 r1.noacc r2(r8).noacc r1.noacc {Align16, N1/N2}
16681653
dst0 = createDstRegRegion(tdst8); dst0->setAccRegSel(ACC6);
16691654
src0 = createSrcRegRegion(csrc1); src0->setAccRegSel(NOACC);
16701655
src1 = createSrcRegRegion(csrc2); src1->setAccRegSel(NOACC);
16711656
src2 = createSrcRegRegion(csrc1); src2->setAccRegSel(NOACC);
16721657
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
16731658

1674-
16751659
// madm (4) r8.acc7 r1.noacc r8.acc6 r10.acc5 {Align16, N1/N2}
16761660
dst0 = createDstRegRegion(tdst8); dst0->setAccRegSel(ACC7);
16771661
src0 = createSrcRegRegion(csrc1); src0->setAccRegSel(NOACC);
16781662
src1 = createSrcRegRegion(tsrc8); src1->setAccRegSel(ACC6);
16791663
src2 = createSrcRegRegion(tsrc10); src2->setAccRegSel(ACC5);
16801664
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
16811665

1682-
16831666
// madm (4) r7.acc8 r0.noacc r10.acc5 r11.acc4 {Align16, N1/N2}
16841667
dst0 = createDstRegRegion(tdst7); dst0->setAccRegSel(ACC8);
16851668
src0 = createSrcRegRegion(csrc0); src0->setAccRegSel(NOACC);
16861669
src1 = createSrcRegRegion(tsrc10); src1->setAccRegSel(ACC5);
16871670
src2 = createSrcRegRegion(tsrc11); src2->setAccRegSel(ACC4);
16881671
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
16891672

1690-
16911673
// madm (4) r10.acc9 r0.noacc r10.acc5 r9.acc3 {Align16, N1/N2}
16921674
dst0 = createDstRegRegion(tdst10); dst0->setAccRegSel(ACC9);
16931675
src0 = createSrcRegRegion(csrc0); src0->setAccRegSel(NOACC);
16941676
src1 = createSrcRegRegion(tsrc10); src1->setAccRegSel(ACC5);
16951677
src2 = createSrcRegRegion(tsrc9); src2->setAccRegSel(ACC3);
16961678
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
16971679

1698-
16991680
// madm (4) r7.acc8 r11.acc4 r8.acc7 r7.acc8 {Align16, N1/N2}
17001681
dst0 = createDstRegRegion(tdst7); dst0->setAccRegSel(ACC8);
17011682
src0 = createSrcRegRegion(tsrc11); src0->setAccRegSel(ACC4);
17021683
src1 = createSrcRegRegion(tsrc8); src1->setAccRegSel(ACC7);
17031684
src2 = createSrcRegRegion(tsrc7); src2->setAccRegSel(ACC8);
17041685
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
17051686

1706-
17071687
// madm (4) r8.acc7 r9.acc3 r8.acc7 r10.acc9 {Align16, N1/N2}
17081688
dst0 = createDstRegRegion(tdst8); dst0->setAccRegSel(ACC7);
17091689
src0 = createSrcRegRegion(tsrc9); src0->setAccRegSel(ACC3);
17101690
src1 = createSrcRegRegion(tsrc8); src1->setAccRegSel(ACC7);
17111691
src2 = createSrcRegRegion(tsrc10); src2->setAccRegSel(ACC9);
17121692
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
17131693

1714-
17151694
// madm (4) r9.acc3 r6.noacc -r7.acc8 r7.acc8 {Align16, N1/N2}
17161695
dst0 = createDstRegRegion(tdst9); dst0->setAccRegSel(ACC3);
17171696
if (IsSrc0Moved)
@@ -1752,23 +1731,17 @@ int IR_Builder::translateVISAArithmeticDoubleSQRTInst(ISA_Opcode opcode, Common_
17521731
src2 = createSrcRegRegion(tsrc8); src2->setAccRegSel(ACC7);
17531732
inst = createInst(NULL, G4_madm, NULL, false, exsize, dst0, src0, src1, src2, madmInstOpt, line_no);
17541733

1755-
}
1756-
1757-
1758-
if (generateIf && !hasDefaultRoundDenorm)
1759-
{
1760-
// else (8) {Q1/Q2}
1761-
inst = createElse(exsize, instOpt);
1762-
1763-
// restore cr0.0 {NoMask}
1764-
dst0 = createDstRegRegion(regDstCR0);
1765-
src0 = Create_Src_Opnd_From_Dcl(tmpRegCR0, getRegionScalar());
1766-
// mov (1) cr0.0<0;1,0>:ud r108.0<1>:ud {NoMask}
1767-
inst = createInst(NULL, G4_mov, NULL, false, 1, dst0, src0, NULL, InstOpt_WriteEnable, line_no);
1768-
}
1734+
if (!hasDefaultRoundDenorm)
1735+
{
1736+
// else (8) {Q1/Q2}
1737+
inst = createElse(exsize, instOpt);
17691738

1770-
if (generateIf)
1771-
{
1739+
// restore cr0.0 {NoMask}
1740+
dst0 = createDstRegRegion(regDstCR0);
1741+
src0 = Create_Src_Opnd_From_Dcl(tmpRegCR0, getRegionScalar());
1742+
// mov (1) cr0.0<0;1,0>:ud r108.0<1>:ud {NoMask}
1743+
inst = createInst(NULL, G4_mov, NULL, false, 1, dst0, src0, NULL, InstOpt_WriteEnable, line_no);
1744+
}
17721745
// endif (8) {Q1/Q2}
17731746
inst = createEndif(exsize, instOpt);
17741747
}

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