diff --git a/cmd/metrics/loader.go b/cmd/metrics/loader.go index 15be3a6d..e011225c 100644 --- a/cmd/metrics/loader.go +++ b/cmd/metrics/loader.go @@ -89,7 +89,7 @@ func NewLoader(uarch string, useLegacyLoader bool) (Loader, error) { case cpus.UarchCLX, cpus.UarchSKX, cpus.UarchBDX, cpus.UarchBergamo, cpus.UarchGenoa, cpus.UarchTurinZen5, cpus.UarchTurinZen5c: slog.Debug("Using legacy loader for microarchitecture", slog.String("uarch", uarch)) return newLegacyLoader(), nil - case cpus.UarchGNR, cpus.UarchGNR_X1, cpus.UarchGNR_X2, cpus.UarchGNR_X3, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchSRF_SP, cpus.UarchSRF_AP, cpus.UarchEMR, cpus.UarchEMR_MCC, cpus.UarchEMR_XCC, cpus.UarchSPR, cpus.UarchSPR_MCC, cpus.UarchSPR_XCC, cpus.UarchICX: + case cpus.UarchCWF, cpus.UarchGNR, cpus.UarchGNR_X1, cpus.UarchGNR_X2, cpus.UarchGNR_X3, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchSRF_SP, cpus.UarchSRF_AP, cpus.UarchEMR, cpus.UarchEMR_MCC, cpus.UarchEMR_XCC, cpus.UarchSPR, cpus.UarchSPR_MCC, cpus.UarchSPR_XCC, cpus.UarchICX: slog.Debug("Using perfmon loader for microarchitecture", slog.String("uarch", uarch)) return newPerfmonLoader(), nil case cpus.UarchGraviton2, cpus.UarchGraviton3, cpus.UarchGraviton4, cpus.UarchAxion, cpus.UarchAltraFamily, cpus.UarchAmpereOneAC03, cpus.UarchAmpereOneAC04, cpus.UarchAmpereOneAC04_1: diff --git a/cmd/metrics/resources/perfmon/cwf/clearwaterforest_core.json b/cmd/metrics/resources/perfmon/cwf/clearwaterforest_core.json new file mode 100644 index 00000000..8d9ff3c5 --- /dev/null +++ b/cmd/metrics/resources/perfmon/cwf/clearwaterforest_core.json @@ -0,0 +1,5519 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6+ (codenamed Clearwater Forest) - V1.01", + "DatePublished": "02/26/2026", + "Version": "1.01", + "Legend": "" + }, + "Events": [ + { + "EventCode": "0x00", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.", + "PublicDescription": "Fixed Counter: Counts the number of instructions retired.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.CORE", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", + "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", + "Counter": "Fixed counter 2", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "BriefDescription": "Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "PublicDescription": "Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "Counter": "Fixed counter 4", + "PEBScounters": "36", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x06", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "BriefDescription": "Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.", + "PublicDescription": "Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.", + "Counter": "Fixed counter 5", + "PEBScounters": "37", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x07", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_RETIRING.ALL", + "BriefDescription": "Fixed Counter: Counts the number of consumed retirement slots.", + "PublicDescription": "Fixed Counter: Counts the number of consumed retirement slots.", + "Counter": "Fixed counter 6", + "PEBScounters": "38", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "PublicDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", + "PublicDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "PublicDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "LD_BLOCKS.DTLB_MISS", + "BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.", + "PublicDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x1f", + "UMaskExt": "0x00", + "EventName": "LD_BLOCKS.ALL", + "BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) and others.", + "PublicDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) and others.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x05", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.L1_MISS", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.WCB_FULL", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x81", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x82", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.WCB_FULL_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0xf4", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.L1_BOUND_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSED_WALK", + "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.", + "PublicDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x0e", + "UMaskExt": "0x00", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x0e", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "BriefDescription": "Counts misaligned loads that are 4K page splits.", + "PublicDescription": "Counts misaligned loads that are 4K page splits.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x13", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "BriefDescription": "Counts misaligned stores that are 4K page splits.", + "PublicDescription": "Counts misaligned stores that are 4K page splits.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0x24", + "UMask": "0x41", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_DATA_RD_MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x42", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_RFO_MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x44", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_CODE_RD_MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x7f", + "UMaskExt": "0x01", + "EventName": "L2_REQUEST.MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xbf", + "UMaskExt": "0x01", + "EventName": "L2_REQUEST.HIT", + "BriefDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Hit. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Hit. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_DATA_RD", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_RFO", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_CODE_RD", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.HWPF", + "BriefDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests, including hits and misses. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests, including hits and misses. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "UMaskExt": "0x01", + "EventName": "L2_REQUEST.ALL", + "BriefDescription": "Counts the number of L2 cache accesses from front door requests for Code Read, Data Read, RFO, ITOM, and L2 Prefetches. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door requests for Code Read, Data Read, RFO, ITOM, and L2 Prefetches. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "UMaskExt": "0x00", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "UMaskExt": "0x00", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x31", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "CORE_REJECT_L2Q.ANY", + "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.", + "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops. Note that L2 prefetcher requests that are dropped are not counted by this event. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", + "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provided data.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provided data.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x06", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_OTHERMOD", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches, a snoop was required, and hits in other core or module on same die. Another core provides the data with a fwd, no fwd, or hitM.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches, a snoop was required, and hits in other core or module on same die. Another core provides the data with a fwd, no fwd, or hitM.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "PublicDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "PublicDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSED_WALK", + "BriefDescription": "Counts the number of page walks initiated by a store that missed the first and second level TLBs.", + "PublicDescription": "Counts the number of page walks initiated by a store that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x0e", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ITLB_MISS", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ICACHE", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x72", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.LSD_MISPREDICT", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a branch mispredict that resulted in LSD exit.", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a branch mispredict that resulted in LSD exit.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions.", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.IQ_JEU_SCB", + "BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.", + "PublicDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.NON_C01_MS_SCB", + "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.", + "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.C01_MS_SCB", + "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state).", + "PublicDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ICACHE.HIT", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ICACHE.MISSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "ICACHE.ACCESSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "PublicDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x0e", + "UMaskExt": "0x00", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.", + "PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ALL_P", + "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls.", + "PublicDescription": "Counts the number of retirement slots not consumed due to front end stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALL_P", + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "PublicDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P]", + "PublicDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Counts the number of instructions retired.", + "PublicDescription": "Counts the number of instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x00", + "UMaskExt": "0x01", + "EventName": "UOPS_RETIRED.X87", + "BriefDescription": "Counts the number of x87 uops retired, includes those in ms flows.", + "PublicDescription": "Counts the number of x87 uops retired, includes those in ms flows.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.EOM", + "BriefDescription": "Counts the number of uops retired that are the last uop of a macro-instruction.", + "PublicDescription": "Counts the number of uops retired that are the last uop of a macro-instruction. EOM uops indicate the 'end of a macro-instruction' and play a crucial role in the processor's control flow and recovery mechanisms.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_RETIRING.ALL_P", + "BriefDescription": "Counts the number of consumed retirement slots.", + "PublicDescription": "Counts the number of consumed retirement slots.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.MS", + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.LSD", + "BriefDescription": "Counts the number of uops retired that originated from a loop stream detector.", + "PublicDescription": "Counts the number of uops retired that originated from a loop stream detector.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.FPDIV", + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", + "PublicDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.IDIV", + "BriefDescription": "Counts the number of integer divide uops retired.", + "PublicDescription": "Counts the number of integer divide uops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "PublicDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "PublicDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "PublicDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "PublicDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD", + "BriefDescription": "Counts the number of taken backward conditional branch instructions retired.", + "PublicDescription": "Counts the number of taken backward conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", + "BriefDescription": "Counts the number of taken forward conditional branch instructions retired.", + "PublicDescription": "Counts the number of taken forward conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Counts the number of taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Counts the number of not taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of not taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_RET", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_RETURN]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_RETURN]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Counts the number of near RET branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_RET]", + "PublicDescription": "Counts the number of near RET branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_RET]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_IND_CALL", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_INDIRECT_CALL", + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL]", + "PublicDescription": "Counts the number of near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_DIR_CALL", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_DIRECT_CALL", + "BriefDescription": "Counts the number of near direct CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_CALL]", + "PublicDescription": "Counts the number of near direct CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_CALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x30", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Counts the number of near CALL branch instructions retired.", + "PublicDescription": "Counts the number of near CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_IND_JMP", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_INDIRECT_JMP", + "BriefDescription": "Counts the number of near indirect JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP]", + "PublicDescription": "Counts the number of near indirect JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.ALL_NEAR_IND", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_INDIRECT", + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]", + "PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x58", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.ALL_NEAR_IND_OR_RET", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x58", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN", + "BriefDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]", + "PublicDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_DIR_JMP", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_DIRECT_JMP", + "BriefDescription": "Counts the number of near direct JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_JMP]", + "PublicDescription": "Counts the number of near direct JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_JMP]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xfb", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Counts the number of near taken branch instructions retired.", + "PublicDescription": "Counts the number of near taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "Counts the number of mispredicted taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Counts the number of mispredicted not taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted not taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_NEAR_IND", + "BriefDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.NEAR_INDIRECT", + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND]", + "PublicDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.ALL", + "BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior", + "PublicDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.CISC", + "BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow", + "PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.BRANCH_DETECT", + "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", + "PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.PREDECODE", + "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.", + "PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.DECODE", + "BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.", + "PublicDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.ICACHE", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.BRANCH_RESTEER", + "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", + "PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.OTHER", + "BriefDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred", + "PublicDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.32B_SP", + "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.64B_DP", + "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.128B_SP", + "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", + "PublicDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.128B_DP", + "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.", + "PublicDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.256B_SP", + "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.256B_DP", + "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x3f", + "UMaskExt": "0x00", + "EventName": "FP_INST_RETIRED.ALL", + "BriefDescription": "Counts the total number of floating point retired instructions.", + "PublicDescription": "Counts the total number of floating point retired instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FP_FLOPS_RETIRED.FP64", + "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results", + "PublicDescription": "Counts the number of floating point operations that produce 64 bit double precision results", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FP_FLOPS_RETIRED.FP32", + "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results", + "PublicDescription": "Counts the number of floating point operations that produce 32 bit single precision results", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FP_FLOPS_RETIRED.ALL", + "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", + "PublicDescription": "Counts the number of all types of floating point operations per uop with all default weighting", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L2_HIT", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT_NO_SNOOP", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and did not have to snoop another core.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and did not have to snoop another core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT_WITH_SNOOP", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and required a snoop (that resulted in a snoop miss, snoop hitm, snoop hit with fwd, or snoop hit with no fwd).", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and required a snoop (that resulted in a snoop miss, snoop hitm, snoop hit with fwd, or snoop hit with no fwd).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x06", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 and L3 caches.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 and L3 caches.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x0e", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L2_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 cache.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.LATE_SWPF", + "BriefDescription": "Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss, that matched a current outstanding prefetch request initiated by a Code SWPF stream.", + "PublicDescription": "Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss, that matched a current outstanding prefetch request initiated by a Code SWPF stream.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_OCCUPANCY", + "BriefDescription": "Counts number of active integer dividers per cycle.", + "PublicDescription": "Counts number of active integer dividers per cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the integer dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the integer dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ARITH.FPDIV_OCCUPANCY", + "BriefDescription": "Counts the number of floating point dividers per cycle in the loop stage.", + "PublicDescription": "Counts the number of floating point dividers per cycle in the loop stage.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_UOPS", + "BriefDescription": "Counts the number of integer divider uops executed per cycle.", + "PublicDescription": "Counts the number of integer divider uops executed per cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "ARITH.FPDIV_UOPS", + "BriefDescription": "Counts the number of floating point divider uops executed per cycle.", + "PublicDescription": "Counts the number of floating point divider uops executed per cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x06", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.", + "PublicDescription": "Counts the number of load uops retired that miss in the second Level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.", + "PublicDescription": "Counts the number of store uops retired that miss in the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x13", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS", + "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.", + "PublicDescription": "Counts the number of memory uops retired that missed in the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "BriefDescription": "Counts the number of load uops retired that performed one or more locks", + "PublicDescription": "Counts the number of load uops retired that performed one or more locks", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "BriefDescription": "Counts the number of retired split load uops.", + "PublicDescription": "Counts the number of retired split load uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "BriefDescription": "Counts the number of retired split store uops.", + "PublicDescription": "Counts the number of retired split store uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x43", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "BriefDescription": "Counts the number of memory uops retired that were splits.", + "PublicDescription": "Counts the number of memory uops retired that were splits.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "BriefDescription": "Counts the number of load ops retired.", + "PublicDescription": "Counts the number of load ops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of store ops retired.", + "PublicDescription": "Counts the number of store ops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x83", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.ALL", + "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST).", + "PublicDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.", + "PublicDescription": "Counts the number of load ops retired that hit the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.", + "PublicDescription": "Counts the number of load ops retired that hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_NO_SNOOP", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_SNOOP_HIT", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x1c", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.", + "PublicDescription": "Counts the number of load ops retired that miss in the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.", + "PublicDescription": "Counts the number of load ops retired that miss in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM", + "PublicDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_OR_NOFWD", + "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in a Remote DRAM", + "PublicDescription": "Counts the number of load ops retired that miss the L3 cache and hit in a Remote DRAM, OR had a Remote snoop miss/no fwd and hit in the Local DRAM.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_NONM", + "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in a Remote Cache and non-modified data was forwarded", + "PublicDescription": "Counts the number of load ops retired that miss the L3 cache and hit in a Remote Cache and non-modified data was forwarded", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_HITM", + "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in a Remote Cache and modified data was forwarded", + "PublicDescription": "Counts the number of load ops retired that miss the L3 cache and hit in a Remote Cache and modified data was forwarded", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0xff", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.ALL", + "BriefDescription": "Counts the total number of load ops retired that miss the L3 cache.", + "PublicDescription": "Counts the total number of load ops retired that miss the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_HITM", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_WITH_FWD", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_NO_FWD", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xe4", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "This event is deprecated. [This event is alias to LBR_INSERTS.ANY]", + "PublicDescription": "This event is deprecated. [This event is alias to LBR_INSERTS.ANY]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xe4", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LBR_INSERTS.ANY", + "BriefDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RETIRED.LBR_INSERTS]", + "PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xe6", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe6", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BACLEARS.INDIRECT", + "BriefDescription": "Counts the number of BACLEARS due to an indirect branch.", + "PublicDescription": "Counts the number of BACLEARS due to an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe6", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "BACLEARS.UNCOND", + "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.", + "PublicDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe6", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BACLEARS.RETURN", + "BriefDescription": "Counts the number of BACLEARS due to a return branch.", + "PublicDescription": "Counts the number of BACLEARS due to a return branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe6", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BACLEARS.COND", + "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.", + "PublicDescription": "Counts the number of BACLEARS due to a conditional jump.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe8", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "PREDICTION.BTCLEAR", + "BriefDescription": "Counts the total number of BTCLEARS.", + "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x33FBFC00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x33FBFC00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/cwf/clearwaterforest_metrics.json b/cmd/metrics/resources/perfmon/cwf/clearwaterforest_metrics.json new file mode 100644 index 00000000..507bc1ba --- /dev/null +++ b/cmd/metrics/resources/perfmon/cwf/clearwaterforest_metrics.json @@ -0,0 +1,1010 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) 6+ (codenamed Clearwater Forest)", + "DatePublished": "03/31/2026", + "Version": "1.0", + "Legend": "", + "TmaVersion": "", + "TmaFlavor": "" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "Freq", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "Freq", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "Util", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "CPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.WR", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.RD", + "Alias": "b" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH0.WR", + "Alias": "c" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.WR", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "((a + b + c + d) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_retired_per_instr", + "LegacyName": "metric_loads retired per instr", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_retired_per_instr", + "LegacyName": "metric_stores retired per instr", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ICACHE.MISSES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "MPI, D-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b) / d", + "Category": "MPI, I-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_number_of_partial_pci_writes", + "LegacyName": "metric_IO_number of partial PCI writes per sec", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "per second", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "(a + b) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_read_l3_miss", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound reads initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_partial_write_l3_miss", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound partial writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_full_write_l3_miss", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound full cache line writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_msi", + "LegacyName": "metric_IO MSI per sec", + "Level": 1, + "BriefDescription": "Message Signaled Interrupts (MSI) per second sent by the integrated I/O traffic controller (IIO) to System Configuration Controller (Ubox).", + "UnitOfMeasure": "per second", + "Events": [ + { + "Name": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_lost_fwd", + "LegacyName": "metric_IO lost fwd per sec", + "Level": 1, + "BriefDescription": "The number of times per second that ownership of a cacheline was stolen from the integrated IO controller before it was able to write back the modified line.", + "UnitOfMeasure": "per second", + "Events": [ + { + "Name": "UNC_I_MISC1.LOST_FWD", + "Alias": "a" + }, + { + "Name": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "(a + b) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "IRP, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_read", + "LegacyName": "metric_IIO_bandwidth_read (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_write", + "LegacyName": "metric_IIO_bandwidth_write (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_cstate_c0", + "LegacyName": "metric_CPU_cstate_C0", + "Level": 1, + "BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_P_CLOCKTICKS", + "Alias": "a" + }, + { + "Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(b / a[0]) * socket_count", + "Category": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_cstate_c6", + "LegacyName": "metric_CPU_cstate_C6", + "Level": 1, + "BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_P_CLOCKTICKS", + "Alias": "a" + }, + { + "Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(b / a[0]) * socket_count", + "Category": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "LegacyName": "metric_IO_bandwidth_read_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "LegacyName": "metric_IO_bandwidth_write_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/cwf/clearwaterforest_uncore.json b/cmd/metrics/resources/perfmon/cwf/clearwaterforest_uncore.json new file mode 100644 index 00000000..2b05c340 --- /dev/null +++ b/cmd/metrics/resources/perfmon/cwf/clearwaterforest_uncore.json @@ -0,0 +1,6167 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6+ (codenamed Clearwater Forest) - V1.01", + "DatePublished": "02/26/2026", + "Version": "1.01", + "Legend": "" + }, + "Events": [ + { + "Unit": "B2CMI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to memory (B2CMI)", + "PublicDescription": "Clockticks of the mesh to memory (B2CMI)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x24", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_READS.NORMAL", + "BriefDescription": "Counts normal reads issue to CMI", + "PublicDescription": "Counts normal reads issue to CMI", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x24", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_READS.ALL", + "BriefDescription": "Counts any read", + "PublicDescription": "Counts any read", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.FULL", + "BriefDescription": "Full Non-ISOCH - All Channels", + "PublicDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL", + "BriefDescription": "Partial Non-ISOCH - All Channels", + "PublicDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.ALL", + "BriefDescription": "All Writes - All Channels", + "PublicDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x33", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0", + "BriefDescription": "Tracker Occupancy : Channel 0", + "PublicDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x56", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH", + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "PublicDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x56", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH", + "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", + "PublicDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Counts cisgress directory updates", + "PublicDescription": "Counts cisgress directory updates", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S", + "BriefDescription": "Any I2S Transition", + "PublicDescription": "Any I2S Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A", + "BriefDescription": "Any I2A Transition", + "PublicDescription": "Any I2A Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I", + "BriefDescription": "Any A2I Transition", + "PublicDescription": "Any A2I Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S", + "BriefDescription": "Any A2S Transition", + "PublicDescription": "Any A2S Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1A", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints", + "PublicDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS", + "BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints", + "PublicDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "Number of CHA clock cycles while the event is enabled", + "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "Code read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "Read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C001FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "All locally initiated requests from IA Cores which miss the cache", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "Code read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "All TOR ItoM inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "All TOR RFO inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "BriefDescription": "Data read opt from local IA that hit the cache", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "Data read opt prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "BriefDescription": "Data read opt from local IA that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "Data read opt prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "ItoMs from local IO devices which hit the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "BriefDescription": "RFOs from local IO devices which hit the cache", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "RFOs from local IO devices", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "All TOR ItoM inserts from local IO devices", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "Read for ownership from local IA", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "BriefDescription": "Data read opt from local IA", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "BriefDescription": "Data read opt prefetch from local IA", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "Code read from local IA", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C806FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "BriefDescription": "Read for ownership from local IA that miss the LLC targeting local memory", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8077E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "BriefDescription": "Read for ownership from local IA that miss the LLC targeting remote memory", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C886FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting local memory", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8877E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting remote memory", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "CLFlush events that are initiated from the Core", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8D7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "BriefDescription": "CLFlushOpt events that are initiated from the Core", + "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "BriefDescription": "ItoM events that are initiated from the Core", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC57FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "BriefDescription": "SpecItoM events that are initiated from the Core", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC3FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices which hit the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices which miss the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA.", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA.", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80EFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "BriefDescription": "CRDs from local IA cores to locally homed memory", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80F7E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "BriefDescription": "CRDs from local IA cores to remotely homed memory", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88EFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "BriefDescription": "CRD Prefetches from local IA cores to locally homed memory", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88F7E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "BriefDescription": "CRD Prefetches from local IA cores to remotely homed memory", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD47FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNear requests from local IA cores", + "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC27FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "BriefDescription": "WbMtoI requests from local IA cores", + "PublicDescription": "TOR Inserts : WbMtoIs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "BriefDescription": "ItoM requests from local IA cores that hit the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "BriefDescription": "ItoM requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C877DE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "BriefDescription": "UCRDF requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C87FDE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "BriefDescription": "WIL requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "BriefDescription": "WCILF requests from local IA core", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "BriefDescription": "WCILF requests from local IA core that miss the cache", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "BriefDescription": "WCIL requests from a local IA core", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "BriefDescription": "WCIL requests from a local IA core that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F86", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86E86", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F06", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "BriefDescription": "WBMtoI requests from IO devices", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "BriefDescription": "CLFlush requests from IO devices", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC2FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC37FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC67FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C81782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", + "BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "PublicDescription": "DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C80782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", + "BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C88782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", + "BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCC782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", + "BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C89782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", + "BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCD782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", + "BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00182", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "PublicDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00181", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "PublicDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy for Code read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "BriefDescription": "TOR Occupancy for All TOR RFO inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "BriefDescription": "TOR Occupancy for Code read prefetch from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "BriefDescription": "TOR Occupancy for Data read opt from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "BriefDescription": "TOR Occupancy for Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "BriefDescription": "TOR Occupancy for ItoMs from local IO devices which hit the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "BriefDescription": "TOR Occupancy for RFOs from local IO devices which hit the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "BriefDescription": "TOR Occupancy for RFOs from local IO devices", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "BriefDescription": "TOR Occupancy for Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C806FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8077E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C886FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8877E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which hit the LLC", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which miss the LLC", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA.", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA.", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80EFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to locally homed memory", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80F7E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to remotely homed memory", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88EFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88F7E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "BriefDescription": "TOR Occupancy for CLFlush events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8D7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "BriefDescription": "TOR Occupancy for CLFlushOpt events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD47FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from local IA cores", + "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC57FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "BriefDescription": "TOR Occupancy for SpecItoM events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC27FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "BriefDescription": "TOR Occupancy for WbMtoI requests from local IA cores", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "BriefDescription": "TOR Occupancy for ItoM events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that hit the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C877DE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "BriefDescription": "TOR Occupancy for UCRDF requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C87FDE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "BriefDescription": "TOR Occupancy for WIL requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA core", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA core that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F86", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86E86", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F06", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "BriefDescription": "TOR Occupancy for WBMtoI requests from IO devices", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "BriefDescription": "TOR Occupancy for CLFlush requests from IO devices", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C80782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", + "BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C81782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", + "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "PublicDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C89782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", + "BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCD782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", + "BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C88782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", + "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCC782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", + "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00182", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "PublicDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00181", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "PublicDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x39", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "BriefDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "PublicDescription": "Cbo Misc : RFO HitS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x3d", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "BriefDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline.", + "PublicDescription": "Snoop Filter Capacity Evictions : M state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x30", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "HA Read and Write Requests : InvalItoE", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "PublicDescription": "HA Read and Write Requests : Reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x0C", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "PublicDescription": "HA Read and Write Requests : Writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x55", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled. DCLK is 1/4 of DRAM data rate.", + "PublicDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x02", + "UMask": "0xF7", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "PublicDescription": "DRAM Activate Count", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x03", + "UMask": "0xF8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG", + "BriefDescription": "CAS count for SubChannel 0 regular reads", + "PublicDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC2", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_PRE_REG", + "BriefDescription": "CAS count for SubChannel 0 auto-precharge reads", + "PublicDescription": "CAS count for SubChannel 0 auto-precharge reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "PublicDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_PRE_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 0 auto-precharge underfill reads", + "PublicDescription": "CAS count for SubChannel 0 auto-precharge underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xCF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD", + "BriefDescription": "CAS count for SubChannel 0, all reads", + "PublicDescription": "CAS count for SubChannel 0, all reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xF0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.WR", + "BriefDescription": "CAS count for SubChannel 0, all writes", + "PublicDescription": "CAS count for SubChannel 0, all writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.ALL", + "BriefDescription": "CAS count for SubChannel 0, all CAS operations", + "PublicDescription": "CAS count for SubChannel 0, all CAS operations", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG", + "BriefDescription": "CAS count for SubChannel 1 regular reads", + "PublicDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC2", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_PRE_REG", + "BriefDescription": "CAS count for SubChannel 1 auto-precharge reads", + "PublicDescription": "CAS count for SubChannel 1 auto-precharge reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "PublicDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_PRE_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 1 auto-precharge underfill reads", + "PublicDescription": "CAS count for SubChannel 1 auto-precharge underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xCF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD", + "BriefDescription": "CAS count for SubChannel 1, all reads", + "PublicDescription": "CAS count for SubChannel 1, all reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xF0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.WR", + "BriefDescription": "CAS count for SubChannel 1, all writes", + "PublicDescription": "CAS count for SubChannel 1, all writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.ALL", + "BriefDescription": "CAS count for SubChannel 1, all CAS operations", + "PublicDescription": "CAS count for SubChannel 1, all CAS operations", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x1a", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH0", + "BriefDescription": "Read buffer occupancy on subchannel 0", + "PublicDescription": "Read buffer occupancy on subchannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x1b", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH1", + "BriefDescription": "Read buffer occupancy on subchannel 1", + "PublicDescription": "Read buffer occupancy on subchannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x80", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0", + "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0", + "PublicDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x81", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1", + "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1", + "PublicDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x82", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0", + "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0", + "PublicDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x83", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1", + "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1", + "PublicDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x84", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0", + "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0", + "PublicDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x85", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1", + "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1", + "PublicDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x86", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0", + "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0", + "PublicDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x87", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1", + "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1", + "PublicDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2HOT", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2HOT_CLOCKTICKS", + "BriefDescription": "UNC_B2HOT_CLOCKTICKS", + "PublicDescription": "UNC_B2HOT_CLOCKTICKS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "IIO Clockticks", + "PublicDescription": "IIO Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.", + "PublicDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.", + "PublicDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "IRP Clockticks", + "PublicDescription": "IRP Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "PublicDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x1F", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_MISC1.LOST_FWD", + "BriefDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x1F", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "BriefDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", + "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_CLOCKTICKS", + "BriefDescription": "Number of UPI LL clock cycles while the event is enabled", + "PublicDescription": "Number of kfclks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", + "PublicDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "All Null Flits", + "PublicDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x47", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "BriefDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Sent", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x05", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "BriefDescription": "Matches on Receive path of a UPI Port : Request", + "PublicDescription": "Matches on Receive path of a UPI Port : Request", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x05", + "UMask": "0x0D", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback", + "PublicDescription": "Matches on Receive path of a UPI Port : Writeback", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2UPI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2UPI_CLOCKTICKS", + "BriefDescription": "Number of uclks in domain", + "PublicDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CXL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CXL_CLOCKTICKS", + "BriefDescription": "B2CXL Clockticks", + "PublicDescription": "B2CXL Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UBOX", + "EventCode": "0x42", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "BriefDescription": "Message Received : MSI", + "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "PCU Clockticks", + "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x35", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "BriefDescription": "Number of cores in C0", + "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x37", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "BriefDescription": "Number of cores in C6", + "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x03", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x32", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0", + "BriefDescription": "Tracker Inserts : Channel 0", + "PublicDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x19", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN", + "BriefDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "PublicDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1A", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "PublicDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS", + "BriefDescription": "Counts the number of d2k wasn't done due to credit constraints", + "PublicDescription": "Counts the number of d2k wasn't done due to credit constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1C", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE", + "BriefDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn", + "PublicDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x16", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN", + "BriefDescription": "Counts the number of times B2CMI egress did D2C (direct to core)", + "PublicDescription": "Counts the number of times B2CMI egress did D2C (direct to core)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x03", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHACMS", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHACMS_CLOCKTICKS", + "BriefDescription": "Clockticks for CMS units attached to CHA", + "PublicDescription": "Clockticks for CMS units attached to CHA", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHACMS", + "EventCode": "0x35", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHACMS_DISTRESS_ASSERTED", + "BriefDescription": "UNC_CHACMS_DISTRESS_ASSERTED", + "PublicDescription": "UNC_CHACMS_DISTRESS_ASSERTED", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x02", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x08", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO 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"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x02", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x08", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0", + "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0", + "PublicDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1", + "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1", + "PublicDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0", + "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0", + "PublicDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1", + "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1", + "PublicDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0", + "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0", + "PublicDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1", + "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1", + "PublicDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0", + "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0", + "PublicDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1", + "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1", + "PublicDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C001FF", + "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS", + "BriefDescription": "TOR Inserts for SF or LLC Evictions", + "PublicDescription": "TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x69", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REMOTE_SF.MISS", + "BriefDescription": "UNC_CHA_REMOTE_SF.MISS", + "PublicDescription": "UNC_CHA_REMOTE_SF.MISS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "MDF", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_MDF_CLOCKTICKS", + "BriefDescription": "MDF Clockticks", + "PublicDescription": "MDF Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C826FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and which target local memory", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A6FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target local memory", + "PublicDescription": "TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8277E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and target remote memory", + "PublicDescription": "TOR Inserts : Data read opt from local iA that missed the LLC targeting remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A77E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target remote memory", + "PublicDescription": "TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F2FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F37F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x8e", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x01", + "UMaskExt": "0x00010FF0", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", + "BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).", + "PublicDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC3", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_NON_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 0 regular reads", + "PublicDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xCC", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL_ALL", + "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "PublicDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC3", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_NON_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 1 regular reads", + "PublicDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xCC", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL_ALL", + "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "PublicDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/cwf/cwf.json b/cmd/metrics/resources/perfmon/cwf/cwf.json new file mode 100644 index 00000000..ddb9b717 --- /dev/null +++ b/cmd/metrics/resources/perfmon/cwf/cwf.json @@ -0,0 +1,266 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "PerfSpect Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with E-cores (Clearwater Forest)" + }, + "PerfmonMetricsFile": "resources:cwf/clearwaterforest_metrics.json", + "PerfmonCoreEventsFile": "resources:cwf/clearwaterforest_core.json", + "PerfmonUncoreEventsFile": "resources:cwf/clearwaterforest_uncore.json", + "PerfmonRetireLatencyFile": "", + "AlternateTMAMetricsFile": "", + "PerfspectMetricsFile": "resources:cwf/cwf_perfspect_metrics.json", + "ReportMetrics": [ + { + "MetricName": "cpu_operating_frequency", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_utilization", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_util_kernel", + "Origin": "perfspect" + }, + { + "MetricName": "cpi", + "Origin": "perfmon" + }, + { + "MetricName": "cycles_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cpi", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cycles_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "ipc", + "Origin": "perfspect" + }, + { + "MetricName": "giga_instructions_per_sec", + "Origin": "perfspect" + }, + { + "MetricName": "branch_misprediction_ratio", + "Origin": "perfspect" + }, + { + "MetricName": "loads_retired_per_instr", + "Origin": "perfmon" + }, + { + "MetricName": "stores_retired_per_instr", + "Origin": "perfmon" + }, + { + "MetricName": "locks_retired_per_instr", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "Origin": "perfmon" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "Origin": "perfmon" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "Origin": "perfmon" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "Origin": "perfmon" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "Origin": "perfmon" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "Origin": "perfmon" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "Origin": "perfmon" + }, + { + "MetricName": "upi_data_transmit_bw", + "Origin": "perfmon" + }, + { + "MetricName": "package_power", + "Origin": "perfspect" + }, + { + "MetricName": "dram_power", + "Origin": "perfspect" + }, + { + "MetricName": "core_c6_residency", + "Origin": "perfspect" + }, + { + "MetricName": "package_c6_residency", + "Origin": "perfspect" + }, + { + "MetricName": "memory_bandwidth_read", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_write", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_total", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "Origin": "perfspect" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "Origin": "perfmon" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "Origin": "perfmon" + }, + { + "MetricName": "uncore_frequency", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read_local", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read_remote", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write_local", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write_remote", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "Origin": "perfmon" + }, + { + "MetricName": "io_number_of_partial_pci_writes", + "Origin": "perfmon" + }, + { + "MetricName": "io_read_l3_miss", + "Origin": "perfmon" + }, + { + "MetricName": "io_partial_write_l3_miss", + "Origin": "perfmon" + }, + { + "MetricName": "io_full_write_l3_miss", + "Origin": "perfmon" + }, + { + "MetricName": "io_lost_fwd", + "Origin": "perfmon" + } + ] +} diff --git a/cmd/metrics/resources/perfmon/cwf/cwf_perfspect_metrics.json b/cmd/metrics/resources/perfmon/cwf/cwf_perfspect_metrics.json new file mode 100644 index 00000000..67e6ba7e --- /dev/null +++ b/cmd/metrics/resources/perfmon/cwf/cwf_perfspect_metrics.json @@ -0,0 +1,469 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved." + }, + "Metrics": [ + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "BriefDescription": "CPU utilization percentage in kernel mode", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC_P:SUP", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (a / b)", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_CPU utilization % in kernel mode" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_CPU utilization % in kernel mode > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "BriefDescription": "Number of cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "BriefDescription": "Kernel cycles per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "BriefDescription": "Number of kernel cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "BriefDescription": "Instructions per cycle", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "BriefDescription": "Billions of instructions per second", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a / 1000000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "BriefDescription": "Ratio of branch mispredictions to the total number of branches retired.", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "BriefDescription": "Locks retired per instruction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "BriefDescription": "Locks retired per transaction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "BriefDescription": "L1D misses per transaction (includes data+rfo with prefetches)", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "BriefDescription": "L1D demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "BriefDescription": "L1I code read misses (includes prefetches) per transaction", + "Events": [ + { + "Name": "ICACHE.MISSES", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "BriefDescription": "L2 demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "BriefDescription": "L2 misses per transaction (includes code+data+rfo with prefetches)", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.REFERENCE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "BriefDescription": "L2 demand data read misses per transaction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "BriefDescription": "LLC code read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "c" + } + ], + "Formula": "(a + b) / c", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "BriefDescription": "LLC data read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "d" + } + ], + "Formula": "(a + b + c) / d", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "BriefDescription": "Package power consumption in watts", + "Events": [ + { + "Name": "power/energy-pkg/", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "BriefDescription": "DRAM power consumption in watts", + "Events": [ + { + "Name": "power/energy-ram/", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "BriefDescription": "Core C6 state residency percentage", + "Events": [ + { + "Name": "cstate_core/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "ResolutionLevels": "CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "BriefDescription": "Package C6 state residency percentage", + "Events": [ + { + "Name": "cstate_pkg/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "CORES_PER_SOCKET", + "Alias": "c" + } + ], + "Formula": "100 * a * c / b", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "BriefDescription": "ITLB (2nd level) misses per transaction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "BriefDescription": "DTLB (2nd level) load misses per transaction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "BriefDescription": "DTLB (2nd level) store misses per transaction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + } + ] +} \ No newline at end of file