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config: add MMIO layout
The new configuration file contains the address and size of MMIO space and PCIE config space. Signed-off-by: Jiaqi Gao <[email protected]>
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14 files changed

+172
-79
lines changed

14 files changed

+172
-79
lines changed

Cargo.lock

Lines changed: 7 additions & 52 deletions
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config/mmio_layout.json

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@@ -0,0 +1,8 @@
1+
{
2+
"Mmio32Start": "0xC0000000",
3+
"Mmio32Size": "0x20000000",
4+
"PcieConfigBaseAddress": "0xE0000000",
5+
"PcieConfigSize": "0x10000000",
6+
"Mmio64Start": "0x100000000",
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"Mmio64Size": "0x40000000"
8+
}

src/devices/pci/Cargo.toml

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ lazy_static = { version = "1.0", features = ["spin_no_std"] }
1111
log = "0.4.13"
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spin = "0.9"
1313
tdx-tdcall = { path = "../../../deps/td-shim/tdx-tdcall", optional = true }
14+
td-payload = { path = "../../../deps/td-shim/td-payload" }
1415
x86 = { version = "0.47.0", optional = true}
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1617
[features]

src/devices/pci/src/config.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,10 @@ use bitflags::bitflags;
66
use core::convert::From;
77

88
use crate::mmio::{alloc_mmio32, alloc_mmio64};
9-
use crate::{PciCommand, PciError, Result};
9+
use crate::{PciCommand, PciError, Result, PCI_EX_BAR_BASE_ADDRESS};
1010

1111
pub const PCI_CONFIGURATION_ADDRESS_PORT: u16 = 0xCF8;
1212
pub const PCI_CONFIGURATION_DATA_PORT: u16 = 0xCFC;
13-
const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000u64;
1413
const PCI_MEM32_BASE_ADDRESS_MASK: u32 = 0xFFFF_FFF0;
1514
const PCI_MEM64_BASE_ADDRESS_MASK: u64 = 0xFFFF_FFFF_FFFF_FFF0;
1615

src/devices/pci/src/layout.rs

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@@ -0,0 +1,10 @@
1+
// Copyright (c) 2024 Intel Corporation
2+
//
3+
// SPDX-License-Identifier: BSD-2-Clause-Patent
4+
5+
pub const MMIO32_START: u32 = 0xC0000000;
6+
pub const MMIO32_SIZE: u32 = 0x20000000;
7+
pub const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000;
8+
pub const PCI_EX_BAR_SIZE: u64 = 0x10000000;
9+
pub const MMIO64_START: u64 = 0x100000000;
10+
pub const MMIO64_SIZE: u64 = 0x40000000;

src/devices/pci/src/lib.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,11 @@
66

77
mod config;
88
mod consts;
9+
mod layout;
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mod mmio;
1011
pub use config::*;
1112
pub use consts::*;
13+
pub use layout::*;
1214
pub use mmio::*;
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1416
#[cfg(feature = "fuzz")]

src/devices/pci/src/mmio.rs

Lines changed: 21 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,9 @@
44

55
use lazy_static::lazy_static;
66
use spin::Mutex;
7+
use td_payload::mm::MEMORY_MAP;
78

8-
use crate::{PciError, Result};
9-
10-
pub const MMIO32_START: u32 = 0xC000_0000;
11-
pub const MMIO32_SIZE: u32 = 0x2000_0000;
9+
use crate::{PciError, Result, MMIO32_SIZE, MMIO32_START, MMIO64_SIZE, MMIO64_START};
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1311
lazy_static! {
1412
static ref MMIO32: Mutex<u32> = Mutex::new(0);
@@ -20,16 +18,24 @@ lazy_static! {
2018
static ref MMIO_OFFSET: Mutex<u64> = Mutex::new(0);
2119
}
2220

23-
pub fn init_mmio(end_of_ram: u64) {
24-
*MMIO32.lock() = MMIO32_START;
25-
26-
let mmio64_start = if end_of_ram > u32::MAX as u64 {
27-
end_of_ram
28-
} else {
29-
u32::MAX as u64 + 1
30-
};
21+
pub fn init_mmio() {
22+
let memory_map = MEMORY_MAP.lock();
23+
24+
// Iterate through each region in the memory map and check if it overlaps with the MMIO32 or MMIO64 space.
25+
// If an overlap is detected, panic with an error message indicating an invalid MMIO configuration.
26+
// This ensures that the MMIO space does not conflict with the RAM space.
27+
for region in memory_map.iter() {
28+
if (region.addr < (MMIO32_START + MMIO32_SIZE) as u64
29+
&& region.addr + region.size > MMIO32_START as u64)
30+
|| (region.addr < MMIO64_START + MMIO64_SIZE
31+
&& region.addr + region.size > MMIO64_START)
32+
{
33+
panic!("Invalid MMIO configuration: MMIO space overlaps with the RAM space.");
34+
}
35+
}
3136

32-
*MMIO64.lock() = mmio64_start;
37+
*MMIO32.lock() = MMIO32_START;
38+
*MMIO64.lock() = MMIO64_START;
3339
}
3440

3541
#[cfg(feature = "fuzz")]
@@ -45,6 +51,8 @@ pub fn alloc_mmio32(size: u32) -> Result<u32> {
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4652
#[cfg(not(feature = "fuzz"))]
4753
pub fn alloc_mmio32(size: u32) -> Result<u32> {
54+
use crate::MMIO32_SIZE;
55+
4856
let cur = *MMIO32.lock();
4957
let addr = align_up(cur as u64, size as u64).ok_or(PciError::InvalidParameter)?;
5058

src/migtd/src/driver/serial.rs

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
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55
use alloc::boxed::Box;
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use core::sync::atomic::AtomicBool;
7+
use pci::PCI_EX_BAR_BASE_ADDRESS;
78
use td_payload::mm::shared::{alloc_shared_pages, free_shared_pages};
89
use virtio_serial::*;
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@@ -48,12 +49,12 @@ impl Timer for SerailTimer {
4849
}
4950
}
5051

51-
// #[cfg(feature = "virtio-serial")]
52-
pub fn virtio_serial_device_init(end_of_ram: u64) {
52+
#[cfg(feature = "virtio-serial")]
53+
pub fn virtio_serial_device_init() {
5354
pci_ex_bar_initialization();
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5556
// Initialize MMIO space
56-
pci::init_mmio(end_of_ram);
57+
pci::init_mmio();
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5859
// Enumerate the virtio device
5960
let (_b, dev, _f) = pci::find_device(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID).unwrap();
@@ -74,8 +75,6 @@ pub fn virtio_serial_device_init(end_of_ram: u64) {
7475
}
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7677
pub fn pci_ex_bar_initialization() {
77-
const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000u64;
78-
7978
// PcdPciExpressBaseAddress TBD
8079
let pci_exbar_base = PCI_EX_BAR_BASE_ADDRESS;
8180

src/migtd/src/driver/vsock.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,11 @@ pub fn vmcall_vsock_device_init(mid: u64, cid: u64) {
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}
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6868
#[cfg(feature = "virtio-vsock")]
69-
pub fn virtio_vsock_device_init(end_of_ram: u64) {
69+
pub fn virtio_vsock_device_init() {
7070
pci_ex_bar_initialization();
7171

7272
// Initialize MMIO space
73-
pci::init_mmio(end_of_ram);
73+
pci::init_mmio();
7474

7575
// Enumerate the virtio device
7676
let (_b, dev, _f) = pci::find_device(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID).unwrap();
@@ -95,7 +95,7 @@ pub fn virtio_vsock_device_init(end_of_ram: u64) {
9595

9696
#[cfg(feature = "virtio-vsock")]
9797
pub fn pci_ex_bar_initialization() {
98-
const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000u64;
98+
use pci::PCI_EX_BAR_BASE_ADDRESS;
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100100
// PcdPciExpressBaseAddress TBD
101101
let pci_exbar_base = PCI_EX_BAR_BASE_ADDRESS;

src/migtd/src/lib.rs

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Original file line numberDiff line numberDiff line change
@@ -23,8 +23,6 @@ pub mod ratls;
2323
#[cfg(target_os = "none")]
2424
pub extern "C" fn _start(hob: u64, payload: u64) -> ! {
2525
use td_payload::arch;
26-
#[cfg(any(feature = "virtio-serial", feature = "virtio-vsock"))]
27-
use td_payload::mm::end_of_ram;
2826
use td_payload::mm::layout::*;
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3028
const STACK_SIZE: usize = 0x1_0000;
@@ -57,11 +55,11 @@ pub extern "C" fn _start(hob: u64, payload: u64) -> ! {
5755
driver::timer::init_timer();
5856

5957
#[cfg(feature = "virtio-serial")]
60-
driver::serial::virtio_serial_device_init(end_of_ram() as u64);
58+
driver::serial::virtio_serial_device_init();
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6260
// Init the vsock-virtio device
6361
#[cfg(feature = "virtio-vsock")]
64-
driver::vsock::virtio_vsock_device_init(end_of_ram() as u64);
62+
driver::vsock::virtio_vsock_device_init();
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6664
arch::init::init(&layout, main);
6765
}

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