1170 and 1180 PAD_CTL fields differ from 10xx fields

[mciantyre]

#26 integrated 1170 pads into imxrt-iomuxc assuming that the pad control (PAD_CTL) register fields would be just like all the PAD_CTL register fields on the 10xx MCUs. You know what that means...

They're different. In fact, there's various PAD_CTL field layouts in the 1170, depending on what pad group you're looking at. Until this is addressed, do not use configure and Config with 1170 pads from imxrt-iomuxc version 0.2. These APIs generate the wrong PAD_CTL values.

This will also affect any pin traits that include PAD_CTL values, like ADC and uSDHC (#27). However, those are not yet implemented for 1170 pads.

None of this affects the 10xx pads. For a 1170 workaround, try using imxrt-ral APIs to specify PAD_CTL values. The SVD appears to match the reference manual for the registers I sampled.

10xx PAD_CTL fields

This is what Config thinks the PAD_CTL looks like.

11xx PAD_CTL fields

I'm noticing three different field layouts across the IOMUXC and IOMUXC_LPSR PAD_CTL registers. I'm ignoring the bits related to domain protection (high nibble of the registers), since that's expected to differ w.r.t. 10xx.

This discussion is specific to the 1170 MCU. I've not considered the 1160 or other 11xx MCUs.

Layout 1: EMC, SD, and DISP_B1 pads (IOMUXC)

No slew rate, speed, or hysteresis. Limited PU/PD config. PDRV is the drive strength; 0 is "high," and 1 is "normal."

Layout 2: LPSR pads (IOMUXC_LPSR)

Slew rate is back. Different way to configure PU/PD. DSE is the drive strength; 0 is "normal," and 1 is "high." It's an inverted PDRV field from the first layout.

Layout 3: AD and DISP_B2 pads (IOMUXC)

Almost the same as the LPSR layout, but with a shifted bit to toggle the open drain.

Other notes

I'm ignoring IOMUXC_SNVS pads, since we're not exporting those through this package. If my study is right, these add two different layouts of 1170 PAD_CTL fields. They also change for the 10xx.

[teburd]

The intro here definitely gave me a chuckle.

Oh yes... but of course they are different, kind of like the entire register map of 1010 is different than the 1050/1060/1064, which is... yeah that actually was a bug in Zephyr as well that someone from NXP had to fix.

Kind of a bummer here though.