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Consider merging with SIMDe? #50

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mr-c opened this issue Nov 7, 2023 · 7 comments
Open

Consider merging with SIMDe? #50

mr-c opened this issue Nov 7, 2023 · 7 comments

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@mr-c
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mr-c commented Nov 7, 2023

We'd love to have you participate!

Bonus, we already have lots of test cases and implementations for other archs and ISAs

simd-everywhere/simde#1087

@howjmay
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howjmay commented Nov 8, 2023

Hi @mr-c I am appreciate.
I am curious about what exactly is the merging you mentioned?
Does it mean moving the whole codebase under SIMDe or just import it in someway?

The current version of neon2rvv is far from stable yet. If I wish to do fast iteration, then staying in a independent repo would make things easier. And the current toolchain using in this repo is a weekly built release by myself.
https://github.com/howjmay/prebuilt-riscv-spike/releases/tag/latest
It is not a stable official version.

It would be great to know more details, and find a way to cooperate. However, in this moment has an independent repo may help me develop faster.

@mr-c
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mr-c commented Nov 8, 2023

The existing code will need to be adapted to the SIMDe way.

For example,

FORCE_INLINE int8x16_t vaddq_s8(int8x16_t __a, int8x16_t __b) { return __riscv_vadd_vv_i8m1(__a, __b, 16); }

would be added to
https://github.com/simd-everywhere/simde/blob/c877fe596198b9df22d9cef7416e80ae30f0489c/simde/arm/neon/add.h#L486-L513

with something like

#elif defined(SIMDE_RISCV64_RVV_NATIVE)
  r_.vint8m1 =  __riscv_vadd_vv_i8m1(a_.vint8m1, b_.vint8m1, 16);

And would be tested by the existing test:
https://github.com/simd-everywhere/simde/blob/c877fe596198b9df22d9cef7416e80ae30f0489c/test/arm/neon/add.c#L845-L911

But first we'd need to add the RVV native types to the simde_*_private types:
https://github.com/simd-everywhere/simde/blob/c877fe596198b9df22d9cef7416e80ae30f0489c/simde/arm/neon/types.h#L474-L484

#elif defined(SIMDE_RISCV64_RVV_NATIVE)
  typedef  vint8m1_t  simde_int8x16_t;

And https://github.com/simd-everywhere/simde/blob/c877fe596198b9df22d9cef7416e80ae30f0489c/simde/arm/neon/types.h#L136-L150

#elif defined(SIMDE_RISCV64_RVV_NATIVE)
  vint8m1_t vint8m1;

@mr-c
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mr-c commented Nov 8, 2023

However, in this moment has an independent repo may help me develop faster.

And that is great! We are ready for you when you are; no rush :-)

@howjmay
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howjmay commented Dec 19, 2023

Hey @mr-c I have finished about 90% of the intrinsics. I think I may be able to process some of the steps to merge to SIMDe. But in the meantime I will develop sse2rvv too. Do you think SIMDe needs that part?

@howjmay
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howjmay commented Jan 1, 2024

My another repo which solves the translation between see and rvv has covered around 35% of the intrinsics

https://github.com/howjmay/sse2rvv

@mr-c
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mr-c commented Feb 20, 2024

Hello @howjmay ; could you review simd-everywhere/simde#1130 and compare that with your approach?

@howjmay
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howjmay commented Feb 23, 2024

Let me try! That is a huge PR 😆

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