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possible.\nSome assertions are being triggered, the reason for which will need to\nbe worked out.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/67 | 9/110 | 1/190 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/39 | 0/52 | 0/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 38/38 | 52/52 | 124/124 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 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This change makes the SUBLEQ CPU\nfaster, with no real change in size. A comment about input on real\nhardware has been made as well.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/66 | 9/126 | 1/198 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/132 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 39/39 | 68/68 | 131/131 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 11/11 | 25/25 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"173.580MHz: New SM - Working"}},{"before":"a0c281581252a0e395696b6e908c703982765382","after":"b27f3d44ff732b90e146386dedbdcbb6cccf2d0d","ref":"refs/heads/feature/sm","pushedAt":"2024-03-19T00:35:38.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"174.294MHz: New SM - Input not quite working\n\nThe input is not quite working with the new state-machine. The system\nterminates on input, output is working and the Forth interpreter is\nworking (it prints the \" ok\" followed by a newline), it is just the\ninput instruction.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/65 | 9/126 | 1/198 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/39 | 0/68 | 0/128 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 38/38 | 68/68 | 128/128 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 11/11 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"174.294MHz: New SM - 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It is possible to\nspecify new program targets via the command line instead of editing the\nsource now, for example. There is also now a second configuration file\nthat can be used for running longer simulations. The programs under\n`progs/` have been edited so they can be run directly as well.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 2/65 | 9/126 | 5/198 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 39/39 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| 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can be overridden on the\ncommand line, thanks GHDL!).\n* Debugging facilities have been improved with more options, debugged\n values are all in decimal, much like the subleq file format.\n\nThere is still a few things to do to move everything over to the new\nsystem, such as new makefile targets, but it does seem to be working.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 2/65 | 9/126 | 5/198 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 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|\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 2/65 | 9/126 | 5/198 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 39/39 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 11/11 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 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`util.vhd`...perhaps).\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 2/65 | 9/126 | 5/198 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 39/39 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 11/11 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.509MHz: Changed signal names"}},{"before":"42b3059a7ede8208f71ba38b188bf2640d38bf16","after":"4ec105b46413e8eeed6f4aeae812eb25b1acfa07","ref":"refs/heads/master","pushedAt":"2024-03-10T15:04:19.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.705MHz: Failed improvements to BRAM loading\n\nThis commit contains *failed* improvements to the BRAM loading\nmechanism, the \"improvements\" are commented out as they do not\nsynthesize which is unfortunate (the do simulated correctly). The To Do\nlist has also been updated.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/69 | 9/126 | 1/190 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/42 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 41/41 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.705MHz: Failed improvements to BRAM loading"}},{"before":"ddb62cbfada9c23c3d3ae664ccae6a0d092bbd3d","after":null,"ref":"refs/heads/feature/uart","pushedAt":"2024-03-10T14:17:08.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"}},{"before":"dd5ebc9adfee598587553a0114e393bab53ba283","after":null,"ref":"refs/heads/feature/optimizations","pushedAt":"2024-03-10T14:17:02.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"}},{"before":"521e7b559d8a0dd8699421df21d8c4c62e6df90f","after":"42b3059a7ede8208f71ba38b188bf2640d38bf16","ref":"refs/heads/master","pushedAt":"2024-03-10T14:15:59.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.705MHz: Improvements to UART interface\n\nThe UART module has had a few improvements to it to make it easier to\nuse. This is what constitutes the majority of changes.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/69 | 9/126 | 1/190 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/42 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 41/41 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.705MHz: Improvements to UART interface"}},{"before":"6b1c395f64d3ba3fc2c0eb35459163fd3af9a33f","after":"521e7b559d8a0dd8699421df21d8c4c62e6df90f","ref":"refs/heads/master","pushedAt":"2024-03-10T01:21:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.705MHz: Improved test benches\n\n* Improved the UART test benches, which are now optionally executed by\n the main test bench.\n* Changed the naming used for many signals within `uart.vhd`.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/69 | 9/126 | 1/190 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/42 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 41/41 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.705MHz: Improved test benches"}},{"before":"af1d25f4a5232cf43c315b41cdcf813461881e9e","after":"6b1c395f64d3ba3fc2c0eb35459163fd3af9a33f","ref":"refs/heads/master","pushedAt":"2024-03-09T23:02:30.000Z","pushType":"push","commitsCount":6,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"Merge branch 'feature/uart'","shortMessageHtmlLink":"Merge branch 'feature/uart'"}},{"before":"38dda8cd7882d4da491a83bfea8b29db62f00be1","after":"ddb62cbfada9c23c3d3ae664ccae6a0d092bbd3d","ref":"refs/heads/feature/uart","pushedAt":"2024-03-09T23:02:14.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.705MHz: New UART module working\n\nThe new UART module is now fully working (in simulation, much like the\nprevious design, I still lack an FPGA dev board). There are still many\nimprovements that could be made to the UART module to make it more\ngeneric and easy to use without causing an problems, but it works so\nthis branch (feature/uart) can be merged to master.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 3/69 | 9/126 | 1/190 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/42 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 41/41 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.705MHz: New UART module working"}},{"before":"2bfbdd0fac86f113c4a2c47dbbb4a1817339dd93","after":"38dda8cd7882d4da491a83bfea8b29db62f00be1","ref":"refs/heads/feature/uart","pushedAt":"2024-03-09T21:22:23.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.725MHz: Fix GIF names\n\nThe names of the GIF in the `readme.md` file were incorrect, a new\nbullet point has also been added to the to-do list.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 0/64 | 0/117 | 0/205 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/41 | 0/68 | 1/136 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 40/40 | 68/68 | 135/135 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 11/11 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.725MHz: Fix GIF names"}},{"before":"16494e604a1f09366b6e32ffa434cd14dcfecd1f","after":"2bfbdd0fac86f113c4a2c47dbbb4a1817339dd93","ref":"refs/heads/feature/uart","pushedAt":"2024-03-09T19:46:01.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.725MHz: Added GIFs of system running\n\nSeveral animated GIFs of simulators and build system running have been\nadded, as they are nice and eye catching.\n\nAlso note that the speed at the top, 172.725MHz, is of the CPU core,\npreviously the design was limited by the UART, it is now limited by the\nCPU core, hopefully this can be sped up (not that it is a problem on a\nboard that is running at only 100MHz).\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 0/64 | 0/117 | 0/205 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/41 | 0/68 | 1/136 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 40/40 | 68/68 | 135/135 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 11/11 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.725MHz: Added GIFs of system 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It is not complex, but images help. Showing the system running\nin the terminal would also help.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 0/64 | 0/117 | 0/205 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/41 | 0/68 | 1/136 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 40/40 | 68/68 | 135/135 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 11/11 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.725MHz: Added system diagram"}},{"before":null,"after":"7a9e3c12f9a4b8dee4656a4418c69f267287905f","ref":"refs/heads/feature/uart","pushedAt":"2024-03-09T17:59:40.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"172.725MHz: Transition to new UART partially complete\n\nThe transition to using the new, smaller and faster UART, has almost\nbeen completed. The new UART could still use some improvements however,\nand the UART test benches should be (optionally generated) in the top\nlevel test bench. The whole system synthesizes much quicker.\n\nReads should *sometimes* work, although have not been tested, only\nUART output from the system. This is due to the fact that the signal for\na new character only appears for one clock cycle.\n\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 0/64 | 0/117 | 0/205 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/41 | 0/68 | 1/136 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 40/40 | 68/68 | 135/135 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart_rx_0 | | 11/11 | 24/24 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_rx_0 |\n| +uart_tx_0 | | 12/12 | 25/25 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart_tx_0 |\n+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"172.725MHz: Transition to new UART partially complete"}},{"before":"dd5ebc9adfee598587553a0114e393bab53ba283","after":"af1d25f4a5232cf43c315b41cdcf813461881e9e","ref":"refs/heads/master","pushedAt":"2024-03-09T15:23:28.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"149.557MHz: Improved fast_tb write mechanism\n\nA small change, a procedure to perform a write to the device has been\nmade, which cleans things up a little.\n\n+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |\n+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 0/75 | 0/145 | 0/216 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 39/39 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart | | 2/35 | 2/77 | 2/92 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart |\n| ++uart_rx_gen.baud_rx | | 9/9 | 21/21 | 25/25 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_rx_gen.baud_rx |\n| ++uart_rx_gen.rx_0 | | 7/7 | 18/18 | 23/23 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_rx_gen.rx_0 |\n| ++uart_tx_gen.baud_tx | | 10/10 | 21/21 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_tx_gen.baud_tx |\n| ++uart_tx_gen.tx_0 | | 7/7 | 15/15 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_tx_gen.tx_0 |\n+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"149.557MHz: Improved fast_tb write mechanism"}},{"before":"6a97c3759c1b80a18dc35d3b7eef08c6c4a85a7a","after":"dd5ebc9adfee598587553a0114e393bab53ba283","ref":"refs/heads/feature/optimizations","pushedAt":"2024-03-09T14:28:33.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"howerj","name":"James","path":"/howerj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1807662?s=80&v=4"},"commit":{"message":"149.557MHz: Integrated `system.vhd` into main prj\n\nThe file `system.vhd` has been integrated into the main project, meaning\nthe two test benches, the faster one and the more realistic one are more\nclosely aligned.\n\n+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |\n+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+\n| top/ | | 0/75 | 0/145 | 0/216 | 0/0 | 0/8 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | top |\n| +system | | 1/40 | 0/68 | 1/124 | 0/0 | 0/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system |\n| ++bram | | 0/0 | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/bram |\n| ++cpu | | 39/39 | 68/68 | 123/123 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/system/cpu |\n| +uart | | 2/35 | 2/77 | 2/92 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart |\n| ++uart_rx_gen.baud_rx | | 9/9 | 21/21 | 25/25 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_rx_gen.baud_rx |\n| ++uart_rx_gen.rx_0 | | 7/7 | 18/18 | 23/23 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_rx_gen.rx_0 |\n| ++uart_tx_gen.baud_tx | | 10/10 | 21/21 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_tx_gen.baud_tx |\n| ++uart_tx_gen.tx_0 | | 7/7 | 15/15 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | top/uart/uart_tx_gen.tx_0 |\n+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+","shortMessageHtmlLink":"149.557MHz: Integrated system.vhd into main prj"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEXnf2oQA","startCursor":null,"endCursor":null}},"title":"Activity ยท howerj/subleq-vhdl"}