How to create a delayed clock?

[matheusinacio7]

I'm learning about electronics now; reading the introduction book "But How Do It Know?" and reproducing the circuits using Digital (thanks a lot for the software!)

There's one problem though: the book mentions delaying a clock by one quarter of a cycle to have a "clk d" output; we can then AND clk + clk d to have a clock that is on for a shorter period of time and OR clk + clk d to have a clock that is on for a longer period of time - the author calls them "clk e" and "clk s" because clk e + clk s sets a good tempo for setting things down the bus

I haven't been able to reproduce this in Digital; the "delay" component doesn't seem to be delaying at all 🤔

I also know that in Digital the wires have no delay - so no matter the length of the wire, the data goes down instantly

Is it possible to simulate the "delayed clock by 1 quarter of a cycle" behavior?

[hneemann]

You must generate the clock signals with a faster running clock:

The "Delay" component delays a signal by just one gate propagation time.

[matheusinacio7]

Awesome! Makes a lot of sense; I didn't know about this D flip flop; it's simply a flip-flop that also outputs the reversed value, yeah?

Thanks so much for the quick answer!