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The Verilog testbench patterns (generated by Digital ) seem very useful, but I haven't been able to get to be recognized in Xilinx Vivado. Is it an IEEE 1364 compatible statement? Any suggestions on how to use its capabilities? |
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Answered by
wmuece
Feb 14, 2022
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The patterns are recognized by editing the _x with 0 or 1 and (for Vivado) using 1ns/1ps rather than 1us/1ns makes the patterns visible. |
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wmuece
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The patterns are recognized by editing the _x with 0 or 1 and (for Vivado) using 1ns/1ps rather than 1us/1ns makes the patterns visible.