GAL 16v8 use I/O as I

[coreidcc]

Based on how I read the 16v8 documentation I expect that it can handle more then 8 input. Of course I need to scarify an output for each I/O pin used as input.

The following expressions can be successfully synthesized with: expression -> create logic -> analyze -> 16v8/CUPL

let Zn = Z0 * Zi * ~flgLd | Z0 * flgLd | cf1 * cf0 * flgLd;
let Sn = Si * ~flgLd | S0 * flgLd;
let Vn = V0 ^ Vi * ~flgLd | V0 * flgLd | cf1 * cf0 * flgLd;
let Cn = Ci * ~flgLd * (cf1 | cf0) | C0 * (flgLd | (~cf1 * ~cf0));
let C = ~cf0 * cf1 | C0 * cf0 * cf1;

this results in the following CUPL.PLD file

Name flags.dig ;
PartNo 00 ;
Date 29.11.2021 ;
Revision 01 ;
Designer xxx ;
Company unknown ;
Assembly None ;
Location unknown ;
Device g16v8a ;

/* inputs */
PIN 1 = CLK;
PIN 2 = Ci;
PIN 3 = Si;
PIN 4 = Vi;
PIN 5 = Zi;
PIN 6 = cf0;
PIN 7 = cf1;
PIN 8 = flgLd;

/* outputs */
PIN 12 = Zn;
PIN 13 = Sn;
PIN 14 = Vn;
PIN 15 = Cn;
PIN 16 = C;

/* sequential logic */
Cn.D = (Ci & cf1 & !flgLd) # (Ci & cf0 & !flgLd) # (Cn & !cf0 & !cf1) # (Cn & flgLd);
Sn.D = (Si & !flgLd) # (Vn & flgLd);
Vn.D = (Sn & flgLd) # (Vi & !flgLd);
Zn.D = (Zi & Zn) # (Zn & flgLd) # (cf0 & cf1 & flgLd);

/* combinatorial logic */
C = (Cn & cf1) # (!cf0 & cf1)

once I add a 5th expression

let Zn = Z0 * Zi * ~flgLd | Z0 * flgLd | cf1 * cf0 * flgLd;
let Sn = Si * ~flgLd | S0 * flgLd;
let Vn = V0 ^ Vi * ~flgLd | V0 * flgLd | cf1 * cf0 * flgLd;
let Cn = Ci * ~flgLd * (cf1 | cf0) | C0 * (flgLd | (~cf1 * ~cf0));
let C = ~cf0 * cf1 | C0 * cf0 * cf1;
let we = ~wp * ~regLd

I'll get: Error during creation of hardware configuration. Too many input used!

What do I need to do that digital uses one of the I/O pins as input?

[hneemann]

This is currently not possible, see also here.

[rehsd]

It would be great to use the I/CLK and I/O/Q pins as inputs. As I've implemented SR latches in GALs with Digital, I have to route the SR latch through external pins to prevent a loop/cycle (allowing me to use Analysis to create a JEDEC). This burns up input pins quickly. Maybe there's a better way to deal with SR latches; I couldn't find it. Example where I'm using Digital with SR latches and could really use more input pins: https://www.rehsdonline.com/post/using-gal22v10-programmable-logic-devices.

[hneemann]

If you do not want to use the existing clocked D-latch, and actually want to build an unclocked SR latch, two macrocells are required for this. It would be better to use the buildin D-latch instead. Using SR-latches without a clock is also very sensitive to hazards. The circuit could become very fragile and unreliable.

[rehsd]

I appreciate the suggestion. I will see if I can refactor the logic to use the clocked D-latch. Thanks!

(It would still be nice to use the I/O/Q pins for input. :)

[hneemann]

The simplest is to use the clocked JK flipflops. The simulator can automatically replace them with d-flipflops.

It would still be nice to use the I/O/Q pins for input.

You are right! :-)