Basys3 constraints file

[wmuece]

The documentation says:
"At present only the BASYS3 board and the Mimas boards Mimas and Mimas V2 are supported. A constraints file is created, which contains the assignment of the pins."
How is a constraints file for Basys3 generated in Digital? Export does not seem to generate a constraints file. I'm not understanding how to do this.

[hneemann]

The simple Verilog and VHDL export only exports the logic of the circuit.
But if you want to run the circuit on an FPGA, especially the clock generation is very specific for each FPGA.
To be as flexible as possible, its generation is coded together with the generation of the contraint file in an external file. So far such a file exists only for BASYS3 and TinyFPGA-BX.
It is called "BASYS3.config" and located in the folder "examples/hdl".
This file must be selected in the settings. Then a new menu is displayed, which offers the corresponding functions.

[wmuece]

What I did to use Digital to successfully generate a .xdc constraint file. In the Digital Main menu: Edit -> Settings -> Advanced "ToolChain Configuration" set to the path to Basys3.config [Restart Digital] Digital Main menu now has new item: BASYS3 -> Export VHDL [Now edit the .xdc file with desired pin locations. Example: PACKAGE PIN -> PACKAGE PIN V17] Is this the correct procedure, or are there other issues shortcuts? - Dean Johnson

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On Feb 15, 2021, at 10:38 AM, Helmut Neemann ***@***.***> wrote: The simple Verilog and VHDL export only exports the logic of the circuit. But if you want to run the circuit on an FPGA, especially the clock generation is very specific for each FPGA. To be as flexible as possible, its generation is coded together with the generation of the contraint file in an external file. So far such a file exists only for BASYS3 and TinyFPGA-BX. It is called "BASYS3.config" and located in the folder "examples/hdl". This file must be selected in the settings. Then a new menu is displayed, which offers the corresponding functions. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#651 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AALLV2GVHML2YPTFLXYOWXLS7E5XHANCNFSM4XU2CKFQ>.

[hneemann]

This is the intended way to generate HDL code for a specific board.
The BASYS3 config also generates a project file for Vivado, which can be opened to perform the analysis, place&route, bit stream generation and flashing.
The TinyFPGA-BX config also starts the apio tools, which makes a complete smooth integration possible.

[wmuece]

I also observed that pasting the IO pins used in the hdl/BASYS3_IOs.dig file into my Digital file will also assign the BASYS PIN numbers in the .xdc file. The names of the IO pins can also be changed. Nice shortcut.

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On Feb 15, 2021, at 1:34 PM, Helmut Neemann ***@***.***> wrote: This is the intended way to generate HDL code for a specific board. The BASYS3 config also generates a project file for Vivado, which can be opened to perform the analysis, place&route, bit stream generation and flashing. The TinyFPGA-BX config also starts the apio tools, which makes a complete smooth integration possible. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#651 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AALLV2HK2MKUKJQCVQVYB3DS7FSMDANCNFSM4XU2CKFQ>.

[hneemann]

Unfortunately, I haven't had time to figure out how the Vivado TCL scripts work and then write one that does everything including writing the BitStream.
Then the integration would be perfect.