Data Flip Flop test, weird behavior.

[me-nkr]

Let's say I have test vectors as the following for a custom negative edge-triggered Data Flip Flop
( given the initial state of O is 0 )

C	I	O
1	1	0
0	0	0

here is a pseudo hdl for the implementation
Implementation 1

CHIP DataFlipFlop {
  IN data, time;
  OUT out;

  PARTS:
  DataLatch(data=data, time=time, out=l1);
  Not(in=time, out=Ntime);
  DataLatch(data=l1, time=Ntime, out=out);
}

Implementation 2

CHIP DataFlipFlop {
  IN data, time;
  OUT out;

  PARTS:
  Not(in=time, out=ntime);
  Not(in=ntime, out=nntime);
  DataLatch(data=data, time=nntime, out=l1);
  Not(in=time, out=nnNtime);
  DataLatch(data=l1, time=nnNtime, out=out);
}

The test vectors fail for the first implementation and succeed for the second one every single time.

Why is this? Is this some kind of race condition?

[hneemann]

I'm not sure what your own custom flip-flop looks like. A simple custom flip-flop e.g. made of two NOR gates has a random initial state. In this case, it is better to switch the flip-flop to a defined state before the actual test and set the test output to "don't care" (X) to cope with any initial state.
But the test sequence given above will cause a NOR flip-flop to oscillate in any case. Depending on the flip-flop, a transition
(00)->(11) or (11)->(00) is always dangerous.

[me-nkr]

The above is the flip-flop in the question, which fails

This is the flip-flop that passes

And the following is the test case.

time	data	out
0	0	x
1	0	x
0	0	0
1	1	0
0	0	0

PS: The Data Latch is implemented using an S-R Latch provided in Digital itself

[hneemann]

Please attach the circuit as a zip file.
Open the top most circuit and after that File->Export->Export to ZIP to create a zip file.

[me-nkr]

DFF.zip

This has the design on the top, there are test cases too ( failing ones are disabled and labeled ).

If you're looking into it, it would be nice if you could verify whether the enabled test cases are correct.

[hneemann]

If the built-in RS flip-flop is forced into oscillation (R and S change from 1 to 0 simultaneously), no error message is generated, but the state is set to a random value, which comes close to a real FF.

[me-nkr]

You are referring to the output as state, right?

Makes sense about the forcing to oscillation part.

• But if the output is random, there is at least one instance where the test passes right?
• Also why does this not happen with the same circuit but with time passed through two not gates? Is it the delay to pass through two not gates that makes the circuit not go into oscillation?