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Say I have an edge-triggered component that gets triggered on the falling edge. If I want to test and verify that it doesn't get triggered on the rising edge, I have to be able to stop the clock in half cycle and assert the state right? But I didn't see the option to do this in Digital's test functionality. Am I missing something or is this a feature that can be and will be added? Unrelated ( not opening another discussion since it seems trivial )
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It seems like I asked too early. While It would be nice if someone could confirm this though : ) |
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It seems like I asked too early.
While
C
completes a full cycle1
and0
can be used to tick-tock ( half steps ) the clock.It would be nice if someone could confirm this though : )