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Neither GAL16v8 nor 22v10 can be used for this purpose, since both do not offer the possibility of asynchronous set or clear. The GAL22v10 can perform this asynchronous operation, at least for all 10 flip-flops together, via a common control line, but not for each flip-flop independently. |
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Hi Could I do this with ATF150x type CPLDs? Thanks, Andrew Lynch PS, if you'd like to see what I am doing, here is an example: https://github.com/lynchaj/duodyne/tree/main/03%20processor.Z80%2C%20V1.1 As you can see, there are five GALs plus a few 74LSxxx chips I could not combine. I think it unlikely to further combine certain types of chips such as buffers, transceivers, and/or open collector outputs. Still, there are approximately eight remaining candidates except they contain asynchronous flip-flops. |
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Hi
My hobby is designing retrocomputer boards like Z80, etc. primarily using discrete logic chips like 74LSxxx. I've recently started using Digital as a PLD design tool to program GALs (GAL16V8 & GAL22V10) with combinatorial logic as a space saving measure on boards.
This works great for combinatorial logic (AND, OR, NOT) but not so much for many of the 74LSxxx chips that require "asynchronous flip-flops". I think that correlates to GAL "registered mode" programming which takes advantage of a built-in flip flop in the logic cells.
Unfortunately, this means I've not been able to combine a lot of 74LSxxx chips into GALs. The compromise I've struck on my boards is all the combinatorial logic is sucked up into the GALs but any that require "registered mode" are left on the board. Even relatively simple chips like 74LS74 D-flip-flop.
Is there a way to use all of the 74LSxxx chips in a GAL design by using "registered mode"? Maybe I need a different design tool?
I've looked into WinCUPL but that seems a like a huge investment in time and effort. I really prefer using Digital because of its graphical chip-as-a-building-block approach. I am less interested in analysis although it has proven handy at times.
Thanks, Andrew Lynch
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