Replies: 3 comments
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The GAL22v10 does not allow asynchronous setting and clearing of registers, whereas the AFT1504 supports asynchronous operations. Personally, I find it strange when a circuit that is not to be realized by 74xxx chips is designed by them. Why not utilize the much easier to use built-in components for the design? |
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Hi For the 7474, I can see using a D-type flip-flop built-in component, but how about for more complicated chips like 74175? If the ATF1504 can incorporate them into the design, it sure would be helpful if those 74xx library components could be used. Also, if the ATF1504 could use the 7474 flip-flop, why did I get the "no asynchronous flip flop" message when I went to do the analysis? I don't understand. Maybe if Digital allowed for specifying the target chip (GAL, ATF150x, etc.) up front then it could procede to analysis step and produce a JEDEC file? I recognize I am probably applying Digital outside its intended use, but it is one of the few open-source PLD design tools I am aware of. Digital's schematic capture is fantastic for updating retrocomputer designs. I just wish I could use it to bring more legacy 74xx chips into the PLD and reduce part count even further. Here is an example of what I am building: https://github.com/lynchaj/duodyne/tree/main/03%20processor.Z80%2C%20V1.0 The Z80 processor board is a derivation of some of my previous designs but using GALs to consolidate the combinatorial logic. However, even with multiple GALs, the board is quite crowded with components. If I could pull in a few more chips into a CPLD, that would simplify trace routing considerably. Again, Thanks for making Digital available and supporting it so well. Andrew Lynch |
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Hi https://github.com/lynchaj/nhyodyne For the duodyne system, I am consolidating certain boards and using PLDs to reduce part count and increase functionality per board. Thanks, Andrew Lynch |
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Hi
I've been experimenting with consolidating the multiple GAL22V10 and GAL16V8 parts into a single ATF1504AS PLCC84 CPLD. As long as I stick with the circuitry already in the GALs (combinatorial, with a few 74139s, 74151s, 74157s, etc.) I am OK and the design analyses fine and compiles to a JEDEC file. The ATMEL fitter works great and I can see the pins assigned to the CPLD in the .FIT file. Pretty nice, so Thank you, and congratulations on Digital. I love this tool and use it frequently.
I had thought maybe the limitation on asynchronous flip flops was related to GALs, so I tried to add a 7474 to my CPLD design and encountered the same error. Apparently, the CPLDs don't support asynchronous flip flops either. That's sort of a bummer because if it did, that would help me reduce part count on my Z80 processor board by another two chips (7474 and 74175)
I had an idea though that might make using Digital a bit easier is to have a warning message if someone selects a 74xx chips with asynchronous flip flops that it will not compile to a JEDEC file. That would save the effort of adding the chip to only find out later that it can't possibly work. Maybe specify the target device up front like GAL22V10 or ATF1504?
Is there some work around to the asynchronous flip flop issue or is that just the nature of GALs and CPLDs? Is the limitation in Digital or the devices themselves? Sorry if this is a silly question but I honestly don't know.
Thanks, Andrew Lynch
PS, please don't take this as being critical of Digital. I really like the program and use it a lot. I am very happy to combine the 5 GALs into one CPLD but would like to understand better the limitation of asynchronous flip flops.
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