Metastability in SR latch for short pulses

[mengstr]

[Not a question - just a note for someone else that might encounter the same problem]

I had an issue of oscillation in a SR latch in a larger circuit and the first thing to check is usually that not both the S and R inputs being active at the same time. But that was not the case here.

I'm a bit ashamed to say that it took me a minute to realise that it was caused by sending it a too short trigger pulse. If the input is not active until the SR have settled it goes into a metastable state that in the simulation is shown as a forever oscillation and in real life settles down to a random state after a random amount of time.

Even if I'm well aware of metastability in D flip flops when you violate the setup and hold times, it didn't immediately occur to me that also a too short set or reset pulse on a SR also causes metastability.

The fix is easy, just make sure that the pulse are at a minimum two gate delays.

[hneemann]

This is caused by the fact that two gates in a SR flipflop must switch one after the other. If the switching pulse is released after only one of the gates has switched, both gates output the same value. And this is the same state as if both, S- and R- are activated.