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Hi, I am using the latest pre-release version of Digital Version v0.30-3-gf8b800a I am trying to analyze a circuit from a Zilog Application Note, figure 10, page 19. I can enter it fine and even do simulation with it and it seems to perform as expected. However, when I press the Analysis key (F9) I get the following error message: Error analysing the circuit Cannot analyse Node FlipflopJKAsync Would anyone please share with me what I am doing wrong with my design? I tried a variety of changes but to no avail. I searched the discussion forum for similar issues without finding anything relevant. Thanks in advance, Andrew Lynch PS, I made an update for a more clear and corrected circuit but still the same error on analyse |
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The 74191 uses asynchronous set/reset to load the counter. This is not supported by the analysis algorithm used in Digital. This could also not be flashed to a GAL22v10, for example, because the GAL22v10 does not support this either. On the GAL22v10, only all flip-flops can be reset together and not independently. |
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Hi
OK, that makes sense. I didn't understand the limitations of what I could program into a GAL. I will need to redesign my circuit for the GAL22V10 to eliminate those types of parts using asynchronous flip flops.
I re-ran a different circuit for a different board that used a 74LS74 flip flop and it now gives the same error message using the current version of Digital. I think that was a fix to a recent version.
I am glad Digital now gives the error message before I started trying to program GALs with impossible instructions resulting in boards that don't work correctly. Good to know now while it is still in the design phase.
Digital is still very useful to me but now I better understand why it does what it does. Thank you! Andrew Lynch
On Saturday, March 11, 2023 at 02:03:21 AM EST, Helmut Neemann ***@***.***> wrote:
The 74191 uses asynchronous set/reset to load the counter. This is not supported by the analysis algorithm used in Digital. This could also not be flashed to a GAL22v10, for example, because the GAL22v10 does not support this either. On the GAL22v10, only all flip-flops can be reset together and not independently.
GALs use a large AND matrix for the realization of the function, which becomes very large very quickly, which is why the functions are limited. FPGAs are built quite differently, which is why there is more flexibility there.
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Perhaps it is easier to build the required circuit directly with the built-in components of the simulator instead of using the 74xxx library. Then there will be no surprises when one of the ICs uses unsupported built-in components for its implementation. |
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Hi This would be handy for future projects. So far, I've found 7474, 74191, 74175, and 74164 Thanks! |
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HiThanks! Yes, in the case of the interrupt acknowledge cycle delay circuit, I am going to implement the circuit using standard logic chips instead of a GAL. There are really only 4 chips in the circuit (74LS191, 74LS32, 74LS04, and 74LS07) plus some passives. Using a GAL in this case would save only two chips and it is not worth it if the 74LS191 and 74LS07 can't be included in the GAL design.
For future design work with Digital though, I will take your advice and use the built-in components to the maximum extent possible. Actually, I don't mind finding out during the design phase that the GAL won't accept certain components containing flip flops because it came out prior to making the actual board. Problems at this point are relatively easy to fix. The error message is a big help because it prevented me from going forward with an impossibly flawed design and wasting time and money.
The GAL22V10 is great for combining a good amount of miscellaneous logic devices into a single chip which saves space on the PCB. However, I've avoided using PLDs in my hobby projects prior to this point because it is so easy to lose their programming information. Once the programming information is lost very often the project becomes irreproducible.
One of the great strengths of Digital (IMO) is that it is Free/Open software, and I can include the Digital program files with my board distribution and also the JEDEC and CUPL files. I include the truth table, CSV, even a graphical image of the circuitry the GAL replaces. Very nice indeed! Practically no chance of losing the contents of the PLD.
Thanks! Andrew Lynch
On Saturday, March 11, 2023 at 11:58:08 AM EST, Helmut Neemann ***@***.***> wrote:
Perhaps it is easier to build the required circuit directly with the built-in components of the simulator instead of using the 74xxx library. Then there will be no surprises when one of the ICs uses unsupported built-in components for its implementation.
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The 74191 uses asynchronous set/reset to load the counter. This is not supported by the analysis algorithm used in Digital. This could also not be flashed to a GAL22v10, for example, because the GAL22v10 does not support this either. On the GAL22v10, only all flip-flops can be reset together and not independently.
GALs use a large AND matrix for the realization of the function, which becomes very large very quickly, which is why the functions are limited. FPGAs are built quite differently, which is why there is more flexibility there.