Understanding propagation delays in Digital

[jongena]

How can propagation delays be realistically taken into account with Digital ?
I executed my circuit in single step and Async mode, similar to the example of the muller pipeline.
Propagation delays are then clearly visible in the data graph.

Two questions:

1. If I run the circuit no longer in Async mode / single step, are these delays still taken into account in Digital, although on the
   data graph they are no longer visible ? Correct or wrong ? Or how are they taken into account ?
2. To avoid an unrealistically long accumulation of propagation delays, it would be useful to be able to simulate various components (gates, flip-flops etc) with NO propagation delay at all. Can this be included in a future version ? My understanding of the internal clockwork of digital is only partial, so perhaps there is another way to avoid too large propagation delays. Can you provide more info ?

Many thanks in advance !

J.Ongena

[hneemann]

If the propagation delay were not taken into account, the circuit would also behave differently. The propagation delay is therefore always taken into account. It is just not always shown in the graph to keep things simple.
Circuits that contain feedback, such as flip-flops, often cannot be mathematically described or simulated without this delay.
Furthermore, gates without propagation delay are unrealistic. Even in reality there is no such thing. The only components that are simulated without propagation delay are those that consist only of wires (splitters, bit expansion, etc.).
An "unrealistically long accumulation of propagation delays" is not possible in the simulator, because the propagation times in the simulator are all of the same length: Each component has the same propagation time, which is not so in reality. So in the simulation almost all components, except the inverter, are faster than in reality.
In the simulation all gates are as fast as the inverter, in reality most components are slower than an inverter. For example, an AND gate has about twice the propagation time in reality.

[jongena]

Many thanks for the reply. This clarifies. However, the gates in the design at hand here are built with diode-resistor logic. I have represented them in digital with their gate function, to be able to reason more easily on the schematic. I could retransform everything to resistor diode logic, but this is not really wished. These diode resistor gates are very fast, and operate practically without delay. Therefore again my question: is there a possibility to reduce the delay in the gates ? Or what do you recommend me with the existing possibilities in Digital ?

With my best regards,

J.Ongena

[hneemann]

To be honest, I don't understand the question.
The diode is one of the components that are simulated without any gate delay at all.
When it is about the performance of the simulation, the gate delay does not matter, because this simulator uses an event based approach for the simulation. There is no concept of time in the simulation. There is only a sequence of events that are processed as fast as possible.

[jongena]

I am sorry for not being clear enough. The circuit I have is one consisting mainly of diodes and resistors, with some invertors and ring registers. The diodes and resistors are arranged in such a way that they operate as gates. E.g. two diodes in parallel, which on one side act as two inputs, and on the other side are connected together to a pull up resistor act as a positive logic "and gate". I translated all these diode/resistor combinations in the circuit (there are ~ hundred of them) into the respective positive (or negative) logic "and gates" or "or gates", in order to be able to understand the circuit more easily. I have thus implemented all these equivalent gates in Digital (not the separate diodes and resistors). I could redo everything with the resistors and diodes, but this would make it (much) more difficult to follow and understand the logic of the circuit when performing the simulation. Thus in this case would it be useful to have an option (only needed for the gates) to reduce the propagation delay or eliminate it altogether, such that they mimic closely the fast switching diodes - resistor gates in the real circuit. The circuit I have is a reverse engineered calculator circuit of 1971, where this kind of logic gates was still very much in use. Perhaps I am in some sense "misusing" Digital, but I am of the opinion that it is the ideal tool to study the logic of such an old-fashioned circuit and would very much like to continue the work started several weeks ago. Any help or further advice would be very much appreciated, in as far as possible.

[hneemann]

I am sorry for not being clear enough.

Never mind! 😄

Your project sounds interesting! But I'm afraid, if in your circuit the differences in propagation times of different part of the circuit play an important role, it will be difficult to simulate the behavior correctly with this simulator.
This simulator uses the simplest imaginable model for propagation times which is still sufficient to simulate and illustrate e.g. edge triggering. The reason for this decision was performance: The simulator should be fast enough to simulate processors with some 100kHz clock frequency. (This project was originally started to simulate processors).
What can be done is to delay certain signals with a delay element to adjust the propagation times.
But the simulation only gives good results if the behavior depends only on the clock signal and not on differences in propagation times.

Is your project publicly available somewhere, so that I can have a look at it?

[jongena]

Dear Mr. Neemann, Many thanks for your reply. I have worked with Mr. Hilpert in Vancouver. He did the reverse engineering of this state machine based on detailed photos I sent him from the front- and backside of the two PCBs loaded with resistors diodes and a dozen Japanese MOS ICs, for which at first the function was unknown, but lateron became clear (and a copy of the relevant pages in the NEC databook of that time found in the National Library in Tokyo a few months later showed that he was 100% correct!) and the schematics (and many other details) can be found on:http://madrona.ca/e/eec/calcs/TEALRiccar.html. The theory of operation is the same as for the Royal Digital machine, also on his website. (see: http://madrona.ca/e/eec/calcs/TEALRoyalDI.html). Does this provide you the information you need ? If you any further info, please let me know.
Mr. Hilpert had in earlier times simulations of various calculators, but these do not function anymore since the moment the MacroMedia ShockWave plug-in for the browser was discontinued. We are looking for an alternative, and thought that Digital would most likely be a very nice solution. Any advice or suggestion from your side would be very welcome !
Send you best regards ! J.Ongena, Belgium