diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst index 5726169f89..cb5c37d3c9 100644 --- a/CONTRIBUTORS.rst +++ b/CONTRIBUTORS.rst @@ -196,7 +196,7 @@ Notable contributors `Zixun Li `__ ------------------------------------------- -- Add new DCD port for Microchip SAMx7x +- Add new DCD port for Microchip SAMHS - Add IAR compiler support - Improve UAC2, CDC, DFU class driver diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 7ce982713c..69ac5c960d 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -26,7 +26,7 @@ Supported MCUs | +-----------------------+--------+------+-----------+-------------------+--------------+ | | SAM L21, L22 | ✔ | | ✖ | samd | | | +-----------------------+--------+------+-----------+-------------------+--------------+ -| | SAM E70,S70,V70,V71 | ✔ | | ✔ | samx7x | | +| | SAM E70,S70,V70,V71 | ✔ | | ✔ | samhs | | +--------------+-----------------------+--------+------+-----------+-------------------+--------------+ | NordicSemi | nRF52833, nRF52840 | ✔ | ✖ | ✖ | nrf5x | | | +-----------------------+--------+------+-----------+-------------------+--------------+ diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index b911e1e535..5c141df7a9 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -55,7 +55,8 @@ #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 + CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 || \ + CFG_TUSB_MCU == OPT_MCU_SAMX7X || CFG_TUSB_MCU == OPT_MCU_SAM3U #include "sam.h" #elif CFG_TUSB_MCU == OPT_MCU_SAMG diff --git a/hw/bsp/russian_woodpecker/board.mk b/hw/bsp/russian_woodpecker/board.mk new file mode 100644 index 0000000000..7464605571 --- /dev/null +++ b/hw/bsp/russian_woodpecker/board.mk @@ -0,0 +1,40 @@ +DEPS_SUBMODULES += hw/mcu/microchip + +CFLAGS += \ + -mthumb \ + -mcpu=cortex-m3 \ + -mfloat-abi=soft \ + -nostdlib -nostartfiles \ + -D__ATSAM3U2C__ \ + -D__SAM3U2C__ \ + -DCFG_TUSB_MCU=OPT_MCU_SAM3U + +# suppress following warnings from mcu driver +# CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual + +DEPS_SUBMODULES += hw/mcu/microchip +DEPS_SUBMODULES += lib/CMSIS_5 + +MCU_DIR = hw/mcu/microchip/sam3u + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/gcc/sam3u2c_flash.ld +LDFLAGS += -L"$(TOP)/$(MCU_DIR)/gcc/gcc/" + +SRC_C += \ + src/portable/microchip/sam3u/dcd_samhs.c \ + $(MCU_DIR)/gcc/gcc/startup_sam3u.c \ + $(MCU_DIR)/gcc/system_sam3u.c + +INC += \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MCU_DIR)/include \ + $(TOP)/hw/bsp/$(BOARD) + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM3 + +# For flash-jlink target +JLINK_DEVICE = ATSAM3U2C + +flash: flash-jlink diff --git a/hw/bsp/russian_woodpecker/russian_woodpecker.c b/hw/bsp/russian_woodpecker/russian_woodpecker.c new file mode 100644 index 0000000000..3b12797f4b --- /dev/null +++ b/hw/bsp/russian_woodpecker/russian_woodpecker.c @@ -0,0 +1,213 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, hathach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "../board.h" + +#include + +#include +#include + +#define CONF_CPU_FREQUENCY 96000000 + +#define LED_R_PIN 1U +#define LED_R_PORT PIOA +#define LED_G_PIN 5U +#define LED_G_PORT PIOB +#define LED_B_PIN 30U +#define LED_B_PORT PIOA + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +//------------- IMPLEMENTATION -------------// +void board_init(void) +{ + /* wait states 96MHz */ + EFC0->EEFC_FMR = (EFC0->EEFC_FMR & ~EEFC_FMR_FWS_Msk) | (3 << EEFC_FMR_FWS_Pos); +#ifdef _SAM3U_EFC1_INSTANCE_ + EFC1->EEFC_FMR = (EFC0->EEFC_FMR & ~EEFC_FMR_FWS_Msk) | (3 << EEFC_FMR_FWS_Pos); +#endif + + /* enable external xtal */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCXTST_Msk | CKGR_MOR_MOSCXTBY)) | CKGR_MOR_KEY_PASSWD | + CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(0xFF); + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) + continue; + + /* select as mainck */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(PMC_MCKR_PRES_Msk | PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK | + PMC_MCKR_PRES(0); + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) + continue; + + /* plla setup, 12MHz x 8 = 96MHz */ + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(7) | CKGR_PLLAR_DIVA(1) | CKGR_PLLAR_PLLACOUNT(63); + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) + continue; + + /* upll config */ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(255) | CKGR_UCKR_UPLLEN; + while (!(PMC->PMC_SR & PMC_SR_LOCKU)) + continue; + + /* plla as mck */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(PMC_MCKR_PRES_Msk | PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_PLLA_CLK | + PMC_MCKR_PRES(0); + + /* Disable Watchdog */ + WDT->WDT_MR |= WDT_MR_WDDIS; + + /* LED */ + PMC->PMC_PCER0 = 1 << ID_PIOA; + PMC->PMC_PCER0 = 1 << ID_PIOB; + LED_R_PORT->PIO_PER = (1 << LED_R_PIN); + LED_R_PORT->PIO_OER = (1 << LED_R_PIN); + LED_G_PORT->PIO_PER = (1 << LED_G_PIN); + LED_G_PORT->PIO_OER = (1 << LED_G_PIN); + LED_B_PORT->PIO_PER = (1 << LED_B_PIN); + LED_B_PORT->PIO_OER = (1 << LED_B_PIN); + + // Button + // _pmc_enable_periph_clock(ID_PIOA); + // gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN); + // gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP); + // gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF); + + // Uart via EDBG Com + // _pmc_enable_periph_clock(ID_USART1); + // gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1); + // gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1); + + // usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async()); + // usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE); + // usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM); + // usart_async_enable(&edbg_com); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(96000000 / 1000); +#endif + + // Enable USB clock + PMC->PMC_PCER0 = 1 << ID_UDPHS; +} + +//--------------------------------------------------------------------+ +// USB Interrupt Handler +//--------------------------------------------------------------------+ +void UDPHS_Handler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + static uint8_t curr_led; + + if (state) + { + switch (curr_led) + { + case 0: + LED_R_PORT->PIO_CODR = (1 << LED_R_PIN); + LED_G_PORT->PIO_SODR = (1 << LED_G_PIN); + LED_B_PORT->PIO_SODR = (1 << LED_B_PIN); + break; + + case 1: + LED_R_PORT->PIO_SODR = (1 << LED_R_PIN); + LED_G_PORT->PIO_CODR = (1 << LED_G_PIN); + LED_B_PORT->PIO_SODR = (1 << LED_B_PIN); + break; + + case 2: + LED_R_PORT->PIO_SODR = (1 << LED_R_PIN); + LED_G_PORT->PIO_SODR = (1 << LED_G_PIN); + LED_B_PORT->PIO_CODR = (1 << LED_B_PIN); + break; + } + } + else + { + LED_R_PORT->PIO_SODR = (1 << LED_R_PIN); + LED_G_PORT->PIO_SODR = (1 << LED_G_PIN); + LED_B_PORT->PIO_SODR = (1 << LED_B_PIN); + } + + curr_led++; + curr_led %= 3; +} + +uint32_t board_button_read(void) +{ + return 0; + // return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN); +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void)buf; + (void)len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + (void)buf; + (void)len; + // while until previous transfer is complete + // while(uart_busy) {} + // uart_busy = true; + + // io_write(&edbg_com.io, buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ +} diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk index ba7088e445..56108d8c24 100644 --- a/hw/bsp/same70_qmtech/board.mk +++ b/hw/bsp/same70_qmtech/board.mk @@ -19,7 +19,7 @@ ASF_DIR = hw/mcu/microchip/same70 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld SRC_C += \ - src/portable/microchip/samx7x/dcd_samx7x.c \ + src/portable/microchip/samhs/dcd_samhs.c \ $(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \ $(ASF_DIR)/same70b/gcc/system_same70q21b.c \ $(ASF_DIR)/hpl/core/hpl_init.c \ diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk index cb2decf504..72cb78e320 100644 --- a/hw/bsp/same70_xplained/board.mk +++ b/hw/bsp/same70_xplained/board.mk @@ -19,7 +19,7 @@ ASF_DIR = hw/mcu/microchip/same70 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld SRC_C += \ - src/portable/microchip/samx7x/dcd_samx7x.c \ + src/portable/microchip/samhs/dcd_samhs.c \ $(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \ $(ASF_DIR)/same70b/gcc/system_same70q21b.c \ $(ASF_DIR)/hpl/core/hpl_init.c \ diff --git a/hw/mcu/microchip b/hw/mcu/microchip index 58eb376320..097482e3a6 160000 --- a/hw/mcu/microchip +++ b/hw/mcu/microchip @@ -1 +1 @@ -Subproject commit 58eb3763200ff51a998be5f537acf67299add227 +Subproject commit 097482e3a668291faf6e423b1df8950eff10b394 diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 383a8d6860..0603eab9f9 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -107,6 +107,11 @@ #define TUP_RHPORT_HIGHSPEED 1 #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER +#elif TU_CHECK_MCU(OPT_MCU_SAM3U) + #define TUP_DCD_ENDPOINT_MAX 7 + #define TUP_RHPORT_HIGHSPEED 0x01 + #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER + #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ) #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER diff --git a/src/portable/microchip/sam3u/dcd_samhs.c b/src/portable/microchip/sam3u/dcd_samhs.c new file mode 100644 index 0000000000..0c525acb6d --- /dev/null +++ b/src/portable/microchip/sam3u/dcd_samhs.c @@ -0,0 +1,750 @@ +/* +* The MIT License (MIT) +* +* Copyright (c) 2018, hathach (tinyusb.org) +* Copyright (c) 2021, HiFiPhile +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +* +* This file is part of the TinyUSB stack. +*/ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_SAM3U) + +#include "device/dcd.h" +#include "sam.h" + +#if TU_CHECK_MCU(OPT_MCU_SAM3U) +#include "samhs_sam3u.h" +#endif + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +// SAMHS registers +#define SAMHS_REG ((samhs_reg_t*) SAMHS_BASE_REG) + +// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) +// We disable SOF for now until needed later on +#ifndef USE_SOF +# define USE_SOF 0 +#endif + +// Dual bank can imporve performance, but need 2 times bigger packet buffer +// Only 4KB packet buffer, use with caution ! +// Enable in FS mode as packets are smaller +#ifndef USE_DUAL_BANK +# if TUD_OPT_HIGH_SPEED +# define USE_DUAL_BANK 0 +# else +# define USE_DUAL_BANK 1 +# endif +#endif + +#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])FIFO_RAM_ADDR)[(ep)]) + +// DMA Channel Transfer Descriptor +typedef struct { + volatile uint32_t next_desc; + volatile uint32_t buff_addr; + volatile uint32_t chnl_ctrl; + uint32_t padding; +} dma_desc_t; + +// Transfer control context +typedef struct { + uint8_t * buffer; + uint16_t total_len; + uint16_t queued_len; + uint16_t max_packet_size; + uint8_t interval; + tu_fifo_t * fifo; +} xfer_ctl_t; + +static tusb_speed_t get_speed(void); +static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix); + +// DMA descriptors shouldn't be placed in ITCM ! +CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6]; + +static xfer_ctl_t xfer_status[EP_MAX]; + +static const tusb_desc_endpoint_t ep0_desc = +{ + .bEndpointAddress = 0x00, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, +}; + +// TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size) +// { +// if (SCB->CCR & SCB_CCR_DC_Msk) +// { +// SCB_CleanInvalidateDCache_by_Addr(addr, size); +// } +// else +// { +// __DSB(); +// __ISB(); +// } +// } +//------------------------------------------------------------------ +// Device API +//------------------------------------------------------------------ + +// Initialize controller to device mode +void dcd_init (uint8_t rhport) +{ + dcd_connect(rhport); +} + +// Enable device interrupt +void dcd_int_enable (uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ((IRQn_Type) UDPHS_IRQn); +} + +// Disable device interrupt +void dcd_int_disable (uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ((IRQn_Type) UDPHS_IRQn); +} + +// Receive Set Address request, mcu port must also include status IN response +void dcd_set_address (uint8_t rhport, uint8_t dev_addr) +{ + (void) dev_addr; + // DCD can only set address after status for this request is complete + // do it at dcd_edpt0_status_complete() + + // Response with zlp status + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); +} + +// Wake up host +void dcd_remote_wakeup (uint8_t rhport) +{ + (void) rhport; + SAMHS_REG->SAMHS_DEV_CTRL |= SAMHS_DEV_CTRL_REWAKEUP; +} + +// Connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + dcd_int_disable(rhport); + // Enable the USB controller in device mode + SAMHS_REG->SAMHS_DEV_CTRL = SAMHS_DEV_CTRL_EN_SAMHS; + +#if TUD_OPT_HIGH_SPEED + SAMHS_REG->SAMHS_DEV_TST &= ~SAMHS_DEV_TST_SPEED_CFG_Msk; +#else + SAMHS_REG->SAMHS_DEV_TST |= SAMHS_DEV_TST_SPEED_CFG_FULL_SPEED; +#endif + // Enable the End Of Reset, Suspend & Wakeup interrupts + SAMHS_REG->SAMHS_DEV_IEN = (SAMHS_DEV_IEN_ENDRESET | SAMHS_DEV_IEN_DET_SUSPD | SAMHS_DEV_IEN_WAKE_UP); +#if USE_SOF + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_INT_SOF; +#endif + // Clear the End Of Reset, SOF & Wakeup interrupts + SAMHS_REG->SAMHS_DEV_CLRINT = (SAMHS_DEV_CLRINT_ENDRESET | SAMHS_DEV_CLRINT_INT_SOF | SAMHS_DEV_CLRINT_WAKE_UP); + + // Ack the Wakeup Interrupt + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_WAKE_UP; + // Attach the device + SAMHS_REG->SAMHS_DEV_CTRL &= ~SAMHS_DEV_CTRL_DETACH; +} + +// Disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + dcd_int_disable(rhport); + // Disable all endpoints + for(size_t i = 0; i < EP_MAX; i++) + { + SAMHS_REG->SAMHS_DEV_EPT[i].SAMHS_DEV_EPTCTLDIS = SAMHS_DEV_EPTCTLDIS_EPT_DISABL; + } + // Clear all the pending interrupts + SAMHS_REG->SAMHS_DEV_CLRINT = 0xF; + // Disable all interrupts + SAMHS_REG->SAMHS_DEV_IEN = 0; + // Detach the device + SAMHS_REG->SAMHS_DEV_CTRL |= SAMHS_DEV_CTRL_DETACH; + // Disable the device address + SAMHS_REG->SAMHS_DEV_CTRL &= ~(SAMHS_DEV_CTRL_FADDR_EN | SAMHS_DEV_CTRL_DEV_ADDR_Msk); +} + +static tusb_speed_t get_speed(void) +{ + if (SAMHS_REG->SAMHS_DEV_INTSTA & SAMHS_DEV_INTSTA_SPEED) { + return TUSB_SPEED_HIGH; + } + + return TUSB_SPEED_FULL; +} + +static void dcd_ep_handler(uint8_t ep_ix) +{ + uint32_t int_status = SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTSTA; + int_status &= SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCTL; + + uint16_t count = (SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTSTA & + SAMHS_DEV_EPTSTA_BYTE_COUNT_Msk) >> SAMHS_DEV_EPTSTA_BYTE_COUNT_Pos; + xfer_ctl_t *xfer = &xfer_status[ep_ix]; + + if (ep_ix == 0U) + { + static uint8_t ctrl_dir; + + if (int_status & SAMHS_DEV_EPTSTA_RX_SETUP) // Received SETUP + { + ctrl_dir = (SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTSTA & SAMHS_DEV_EPTSTA_CURBK_CTLDIR_Msk) >> SAMHS_DEV_EPTSTA_CURBK_CTLDIR_Pos; + // Setup packet should always be 8 bytes. If not, ignore it, and try again. + if (count == 8) + { + uint8_t *ptr = EP_GET_FIFO_PTR(0,8); + dcd_event_setup_received(0, ptr, true); + } + // Ack and disable SETUP interrupt + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_RX_SETUP; + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLDIS = SAMHS_DEV_EPTCTLDIS_RX_SETUP; + } + if (int_status & SAMHS_DEV_EPTSTA_RXRDY_TXKL) // Received OUT + { + uint8_t *ptr = EP_GET_FIFO_PTR(0,8); + + if (count && xfer->total_len) + { + uint16_t remain = xfer->total_len - xfer->queued_len; + if (count > remain) + { + count = remain; + } + if (xfer->buffer) + { + memcpy(xfer->buffer + xfer->queued_len, ptr, count); + } else + { + tu_fifo_write_n(xfer->fifo, ptr, count); + } + xfer->queued_len = (uint16_t)(xfer->queued_len + count); + } + // Acknowledge the interrupt + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_RXRDY_TXKL; + if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) + { + // RX COMPLETE + dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true); + // Disable the interrupt + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLDIS = SAMHS_DEV_EPTCTLDIS_RXRDY_TXKL; + // Re-enable SETUP interrupt + if (ctrl_dir == 1) + { + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_RX_SETUP; + } + } + } + if (int_status & SAMHS_DEV_EPTSTA_TX_COMPLT) + { + // Disable the interrupt + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLDIS = SAMHS_DEV_EPTCTLDIS_TX_COMPLT; + if ((xfer->total_len != xfer->queued_len)) + { + // TX not complete + dcd_transmit_packet(xfer, 0); + } else + { + // TX complete + dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true); + // Re-enable SETUP interrupt + if (ctrl_dir == 0) + { + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_RX_SETUP; + } + } + } + } else + { + if (int_status & SAMHS_DEV_EPTSTA_RXRDY_TXKL) + { + if (count && xfer->total_len) + { + uint16_t remain = xfer->total_len - xfer->queued_len; + if (count > remain) + { + count = remain; + } + uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8); + if (xfer->buffer) + { + memcpy(xfer->buffer + xfer->queued_len, ptr, count); + } else { + tu_fifo_write_n(xfer->fifo, ptr, count); + } + xfer->queued_len = (uint16_t)(xfer->queued_len + count); + } + + // Acknowledge the interrupt + SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_RXRDY_TXKL; + if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) + { + // RX COMPLETE + dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true); + // Disable the interrupt + SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCTLDIS = SAMHS_DEV_EPTCTLDIS_RXRDY_TXKL; + // Though the host could still send, we don't know. + } + } + if (int_status & SAMHS_DEV_EPTSTA_TXRDY) + { + // Acknowledge the interrupt + // SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_TXRDY; // !TODO: check this + if ((xfer->total_len != xfer->queued_len)) + { + // TX not complete + dcd_transmit_packet(xfer, ep_ix); + } else + { + // TX complete + dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true); + // Disable the interrupt + SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCTLDIS = SAMHS_DEV_EPTCTLDIS_TXRDY; + } + } + } +} + +static void dcd_dma_handler(uint8_t ep_ix) +{ + uint32_t status = SAMHS_REG->SAMHS_DEV_DMA[ep_ix - 1].SAMHS_DEV_DMASTATUS; + if (status & SAMHS_DEV_DMASTATUS_CHANN_ENB) + { + return; // Ignore EOT_STA interrupt + } + // Disable DMA interrupt + SAMHS_REG->SAMHS_DEV_IEN &= ~(SAMHS_DEV_IEN_DMA_1 << (ep_ix - 1)); + + xfer_ctl_t *xfer = &xfer_status[ep_ix]; + uint16_t count = xfer->total_len - ((status & SAMHS_DEV_DMASTATUS_BUFF_COUNT_Msk) >> SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos); + if(SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCFG & SAMHS_DEV_EPTCFG_EPT_DIR) + { + dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true); + } else + { + dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true); + } +} + +void dcd_int_handler(uint8_t rhport) +{ + (void) rhport; + uint32_t int_status = SAMHS_REG->SAMHS_DEV_INTSTA; + int_status &= SAMHS_REG->SAMHS_DEV_IEN; + // End of reset interrupt + if (int_status & SAMHS_DEV_INTSTA_ENDRESET) + { + // Reset all endpoints + for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) + { + SAMHS_REG->SAMHS_DEV_EPTRST = (SAMHS_DEV_EPTRST_EPT_0 << ep_ix); + } + dcd_edpt_open (0, &ep0_desc); + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_ENDRESET; + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_WAKE_UP; + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_DET_SUSPD; + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_DET_SUSPD; + + dcd_event_bus_reset(rhport, get_speed(), true); + } + // End of Wakeup interrupt + if (int_status & SAMHS_DEV_INTSTA_WAKE_UP) + { + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_WAKE_UP; + SAMHS_REG->SAMHS_DEV_IEN &= ~(SAMHS_DEV_IEN_WAKE_UP); + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_DET_SUSPD; + + dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); + } + // Suspend interrupt + if (int_status & SAMHS_DEV_INTSTA_DET_SUSPD) + { + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_DET_SUSPD; + SAMHS_REG->SAMHS_DEV_IEN &= ~(SAMHS_DEV_IEN_DET_SUSPD); + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_WAKE_UP; + + dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); + } +#if USE_SOF + if(int_status & SAMHS_DEV_INTSTA_INT_SOF) + { + SAMHS_REG->SAMHS_DEV_CLRINT = SAMHS_DEV_CLRINT_INT_SOF; + + dcd_event_bus_signal(0, DCD_EVENT_SOF, true); + } +#endif + // Endpoints interrupt + for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) + { + if (int_status & (SAMHS_DEV_INTSTA_EPT_0 << ep_ix)) + { + dcd_ep_handler(ep_ix); + } + } + // Endpoints DMA interrupt + for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) + { + if (EP_DMA_SUPPORT(ep_ix)) + { + if (int_status & (SAMHS_DEV_INTSTA_DMA_1 << (ep_ix - 1))) + { + dcd_dma_handler(ep_ix); + } + } + } +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ +// Invoked when a control transfer's status stage is complete. +// May help DCD to prepare for next control transfer, this API is optional. +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) +{ + (void) rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS ) + { + uint8_t const dev_addr = (uint8_t) request->wValue; + + SAMHS_REG->SAMHS_DEV_CTRL |= SAMHS_DEV_CTRL_DEV_ADDR(dev_addr) | SAMHS_DEV_CTRL_FADDR_EN; + } +} + +// Configure endpoint's registers according to descriptor +bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress); + uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc); + tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer; + uint8_t fifoSize = 0; // FIFO size + uint16_t defaultEndpointSize = 8; // Default size of Endpoint + // Find upper 2 power number of epMaxPktSize + if (epMaxPktSize) + { + while (defaultEndpointSize < epMaxPktSize) + { + fifoSize++; + defaultEndpointSize <<= 1; + } + } + xfer_status[epnum].max_packet_size = epMaxPktSize; + + SAMHS_REG->SAMHS_DEV_EPTRST = (SAMHS_DEV_EPTRST_EPT_0 << epnum); + + if (epnum == 0) + { + // Enable the control endpoint - Endpoint 0 + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLENB |= SAMHS_DEV_EPTCTLENB_EPT_ENABL; + // Configure the Endpoint 0 configuration register + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCFG = (SAMHS_DEV_EPTCFG_EPT_SIZE(fifoSize) | + SAMHS_DEV_EPTCFG_EPT_TYPE(TUSB_XFER_CONTROL) | + SAMHS_DEV_EPTCFG_BK_NUMBER_1); + + + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_TOGGLESQ; + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_FRCESTALL; + + if (SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCFG & SAMHS_DEV_EPTCFG_EPT_MAPD) + { + // Endpoint configuration is successful + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_RX_SETUP; + // Enable Endpoint 0 Interrupts + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_EPT_0; + return true; + } else + { + // Endpoint configuration is not successful + return false; + } + } else + { + // Enable the endpoint + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCTLENB |= SAMHS_DEV_EPTCTLENB_EPT_ENABL; + // Set up the maxpacket size, fifo start address fifosize + // and enable the interrupt. CLear the data toggle. + // AUTOSW is needed for DMA ack ! + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCFG = (SAMHS_DEV_EPTCFG_EPT_SIZE(fifoSize) | + SAMHS_DEV_EPTCFG_EPT_TYPE(eptype) | + SAMHS_DEV_EPTCFG_BK_NUMBER_1 | + ((dir & 0x01) << 3)); + if (eptype == TUSB_XFER_ISOCHRONOUS) + { + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCFG |= SAMHS_DEV_EPTCFG_NB_TRANS(1); + } +#if USE_DUAL_BANK + if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK) + { + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCFG |= SAMHS_DEV_EPTCFG_BK_NUMBER_2; + } +#endif + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_TOGGLESQ; + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_FRCESTALL; + if (SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCFG & SAMHS_DEV_EPTCFG_EPT_MAPD) + { + SAMHS_REG->SAMHS_DEV_IEN |= (SAMHS_DEV_IEN_EPT_0 << epnum); + return true; + } else + { + // Endpoint configuration is not successful + return false; + } + } +} + +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + + // Disable endpoint interrupt + SAMHS_REG->SAMHS_DEV_IEN &= ~(SAMHS_DEV_IEN_EPT_0 << epnum); + // Disable EP + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCTLENB &= ~(SAMHS_DEV_EPTCTLENB_EPT_ENABL); +} + +static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) +{ + uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len); + if (len) + { + if (len > xfer->max_packet_size) + { + len = xfer->max_packet_size; + } + uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8); + if(xfer->buffer) + { + memcpy(ptr, xfer->buffer + xfer->queued_len, len); + } + else + { + tu_fifo_read_n(xfer->fifo, ptr, len); + } + __DSB(); + __ISB(); + xfer->queued_len = (uint16_t)(xfer->queued_len + len); + } + if (ep_ix == 0U) + { + // Control endpoint: clear the interrupt flag to send the data + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTSETSTA = SAMHS_DEV_EPTSETSTA_TXRDY; + } else + { + // Other endpoint types: clear the FIFO control flag to send the data + SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTSETSTA = SAMHS_DEV_EPTSETSTA_TXRDY; + } + SAMHS_REG->SAMHS_DEV_EPT[ep_ix].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_TX_COMPLT; +} + +// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack +bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = &xfer_status[epnum]; + + xfer->buffer = buffer; + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->fifo = NULL; + + if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) + { + // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the + // address to 32-byte boundaries. + // CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31); + uint32_t udd_dma_ctrl = total_bytes << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos; + if (dir == TUSB_DIR_OUT) + { + udd_dma_ctrl |= SAMHS_DEV_DMACONTROL_END_TR_IT | SAMHS_DEV_DMACONTROL_END_TR_EN; + } else { + udd_dma_ctrl |= SAMHS_DEV_DMACONTROL_END_B_EN; + } + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMAADDRESS = (uint32_t)buffer; + udd_dma_ctrl |= SAMHS_DEV_DMACONTROL_END_BUFFIT | SAMHS_DEV_DMACONTROL_CHANN_ENB; + // Disable IRQs to have a short sequence + // between read of EOT_STA and DMA enable + uint32_t irq_state = __get_PRIMASK(); + __disable_irq(); + if (!(SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMASTATUS & SAMHS_DEV_DMASTATUS_END_TR_ST)) + { + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMACONTROL = udd_dma_ctrl; + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_DMA_1 << (epnum - 1); + __set_PRIMASK(irq_state); + return true; + } + __set_PRIMASK(irq_state); + + // Here a ZLP has been recieved + // and the DMA transfer must be not started. + // It is the end of transfer + return false; + } else + { + if (dir == TUSB_DIR_OUT) + { + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_RXRDY_TXKL; + } else + { + dcd_transmit_packet(xfer,epnum); + } + } + return true; +} + +// The number of bytes has to be given explicitly to allow more flexible control of how many +// bytes should be written and second to keep the return value free to give back a boolean +// success message. If total_bytes is too big, the FIFO will copy only what is available +// into the USB buffer! +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = &xfer_status[epnum]; + if(epnum == 0x80) + xfer = &xfer_status[EP_MAX]; + + xfer->buffer = NULL; + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->fifo = ff; + + if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) + { + tu_fifo_buffer_info_t info; + uint32_t udd_dma_ctrl_lin = SAMHS_DEV_DMACONTROL_CHANN_ENB; + uint32_t udd_dma_ctrl_wrap = SAMHS_DEV_DMACONTROL_CHANN_ENB | SAMHS_DEV_DMACONTROL_END_BUFFIT; + if (dir == TUSB_DIR_OUT) + { + tu_fifo_get_write_info(ff, &info); + udd_dma_ctrl_lin |= SAMHS_DEV_DMACONTROL_END_TR_IT | SAMHS_DEV_DMACONTROL_END_TR_EN; + udd_dma_ctrl_wrap |= SAMHS_DEV_DMACONTROL_END_TR_IT | SAMHS_DEV_DMACONTROL_END_TR_EN; + } else { + tu_fifo_get_read_info(ff, &info); + if(info.len_wrap == 0) + { + udd_dma_ctrl_lin |= SAMHS_DEV_DMACONTROL_END_B_EN; + } + udd_dma_ctrl_wrap |= SAMHS_DEV_DMACONTROL_END_B_EN; + } + + // Clean invalidate cache of linear part + // CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31); + + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMAADDRESS = (uint32_t)info.ptr_lin; + if (info.len_wrap) + { + // Clean invalidate cache of wrapped part + // CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31); + + dma_desc[epnum - 1].next_desc = 0; + dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap; + dma_desc[epnum - 1].chnl_ctrl = + udd_dma_ctrl_wrap | (info.len_wrap << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos); + // Clean cache of wrapped DMA descriptor + // CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t)); + + udd_dma_ctrl_lin |= SAMHS_DEV_DMASTATUS_DESC_LDST; + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMANXTDSC = (uint32_t)&dma_desc[epnum - 1]; + } else { + udd_dma_ctrl_lin |= SAMHS_DEV_DMACONTROL_END_BUFFIT; + } + udd_dma_ctrl_lin |= (info.len_lin << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos); + // Disable IRQs to have a short sequence + // between read of EOT_STA and DMA enable + uint32_t irq_state = __get_PRIMASK(); + __disable_irq(); + if (!(SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMASTATUS & SAMHS_DEV_DMASTATUS_END_TR_ST)) + { + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMACONTROL = udd_dma_ctrl_lin; + SAMHS_REG->SAMHS_DEV_IEN |= SAMHS_DEV_IEN_DMA_1 << (epnum - 1); + __set_PRIMASK(irq_state); + return true; + } + __set_PRIMASK(irq_state); + + // Here a ZLP has been recieved + // and the DMA transfer must be not started. + // It is the end of transfer + return false; + } else + { + if (dir == TUSB_DIR_OUT) + { + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_RXRDY_TXKL; + } else + { + dcd_transmit_packet(xfer,epnum); + } + } + return true; +} + +// Stall endpoint +void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTSETSTA = SAMHS_DEV_EPTSETSTA_FRCESTALL; + // Re-enable SETUP interrupt + if (epnum == 0) + { + SAMHS_REG->SAMHS_DEV_EPT[0].SAMHS_DEV_EPTCTLENB = SAMHS_DEV_EPTCTLENB_RX_SETUP; + } +} + +// clear stall, data toggle is also reset to DATA0 +void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_FRCESTALL; + SAMHS_REG->SAMHS_DEV_EPT[epnum].SAMHS_DEV_EPTCLRSTA = SAMHS_DEV_EPTCLRSTA_TOGGLESQ; +} + +#endif diff --git a/src/portable/microchip/sam3u/samhs_sam3u.h b/src/portable/microchip/sam3u/samhs_sam3u.h new file mode 100644 index 0000000000..392d8cef6d --- /dev/null +++ b/src/portable/microchip/sam3u/samhs_sam3u.h @@ -0,0 +1,343 @@ + /* +* The MIT License (MIT) +* +* Copyright (c) 2019 Microchip Technology Inc. +* Copyright (c) 2018, hathach (tinyusb.org) +* Copyright (c) 2021, HiFiPhile +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +* +* This file is part of the TinyUSB stack. +*/ + +#ifndef _SAMHS_SAM3U_H_ +#define _SAMHS_SAM3U_H_ + +/* -------- SAMHS_DEV_CTRL : (SAMHS Offset: 0x00) SAMHS Control Register -------- */ +#define SAMHS_DEV_CTRL_DEV_ADDR_Pos 0 +#define SAMHS_DEV_CTRL_DEV_ADDR_Msk (0x7fu << SAMHS_DEV_CTRL_DEV_ADDR_Pos) /**< \brief (SAMHS_DEV_CTRL) SAMHS Address */ +#define SAMHS_DEV_CTRL_DEV_ADDR(value) ((SAMHS_DEV_CTRL_DEV_ADDR_Msk & ((value) << SAMHS_DEV_CTRL_DEV_ADDR_Pos))) +#define SAMHS_DEV_CTRL_FADDR_EN (0x1u << 7) /**< \brief (SAMHS_DEV_CTRL) Function Address Enable */ +#define SAMHS_DEV_CTRL_EN_SAMHS (0x1u << 8) /**< \brief (SAMHS_DEV_CTRL) SAMHS Enable */ +#define SAMHS_DEV_CTRL_DETACH (0x1u << 9) /**< \brief (SAMHS_DEV_CTRL) Detach Command */ +#define SAMHS_DEV_CTRL_REWAKEUP (0x1u << 10) /**< \brief (SAMHS_DEV_CTRL) Send Remote Wake Up */ +#define SAMHS_DEV_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (SAMHS_DEV_CTRL) Pull-Down Disable */ +/* -------- SAMHS_DEV_FNUM : (SAMHS Offset: 0x04) SAMHS Frame Number Register -------- */ +#define SAMHS_DEV_FNUM_MICRO_FRAME_NUM_Pos 0 +#define SAMHS_DEV_FNUM_MICRO_FRAME_NUM_Msk (0x7u << SAMHS_DEV_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (SAMHS_DEV_FNUM) Microframe Number */ +#define SAMHS_DEV_FNUM_FRAME_NUMBER_Pos 3 +#define SAMHS_DEV_FNUM_FRAME_NUMBER_Msk (0x7ffu << SAMHS_DEV_FNUM_FRAME_NUMBER_Pos) /**< \brief (SAMHS_DEV_FNUM) Frame Number as defined in the Packet Field Formats */ +#define SAMHS_DEV_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (SAMHS_DEV_FNUM) Frame Number CRC Error */ +/* -------- SAMHS_DEV_IEN : (SAMHS Offset: 0x10) SAMHS Interrupt Enable Register -------- */ +#define SAMHS_DEV_IEN_DET_SUSPD (0x1u << 1) /**< \brief (SAMHS_DEV_IEN) Suspend Interrupt Enable */ +#define SAMHS_DEV_IEN_MICRO_SOF (0x1u << 2) /**< \brief (SAMHS_DEV_IEN) Micro-SOF Interrupt Enable */ +#define SAMHS_DEV_IEN_INT_SOF (0x1u << 3) /**< \brief (SAMHS_DEV_IEN) SOF Interrupt Enable */ +#define SAMHS_DEV_IEN_ENDRESET (0x1u << 4) /**< \brief (SAMHS_DEV_IEN) End Of Reset Interrupt Enable */ +#define SAMHS_DEV_IEN_WAKE_UP (0x1u << 5) /**< \brief (SAMHS_DEV_IEN) Wake Up CPU Interrupt Enable */ +#define SAMHS_DEV_IEN_ENDOFRSM (0x1u << 6) /**< \brief (SAMHS_DEV_IEN) End Of Resume Interrupt Enable */ +#define SAMHS_DEV_IEN_UPSTR_RES (0x1u << 7) /**< \brief (SAMHS_DEV_IEN) Upstream Resume Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_0 (0x1u << 8) /**< \brief (SAMHS_DEV_IEN) Endpoint 0 Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_1 (0x1u << 9) /**< \brief (SAMHS_DEV_IEN) Endpoint 1 Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_2 (0x1u << 10) /**< \brief (SAMHS_DEV_IEN) Endpoint 2 Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_3 (0x1u << 11) /**< \brief (SAMHS_DEV_IEN) Endpoint 3 Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_4 (0x1u << 12) /**< \brief (SAMHS_DEV_IEN) Endpoint 4 Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_5 (0x1u << 13) /**< \brief (SAMHS_DEV_IEN) Endpoint 5 Interrupt Enable */ +#define SAMHS_DEV_IEN_EPT_6 (0x1u << 14) /**< \brief (SAMHS_DEV_IEN) Endpoint 6 Interrupt Enable */ +#define SAMHS_DEV_IEN_DMA_1 (0x1u << 25) /**< \brief (SAMHS_DEV_IEN) DMA Channel 1 Interrupt Enable */ +#define SAMHS_DEV_IEN_DMA_2 (0x1u << 26) /**< \brief (SAMHS_DEV_IEN) DMA Channel 2 Interrupt Enable */ +#define SAMHS_DEV_IEN_DMA_3 (0x1u << 27) /**< \brief (SAMHS_DEV_IEN) DMA Channel 3 Interrupt Enable */ +#define SAMHS_DEV_IEN_DMA_4 (0x1u << 28) /**< \brief (SAMHS_DEV_IEN) DMA Channel 4 Interrupt Enable */ +#define SAMHS_DEV_IEN_DMA_5 (0x1u << 29) /**< \brief (SAMHS_DEV_IEN) DMA Channel 5 Interrupt Enable */ +#define SAMHS_DEV_IEN_DMA_6 (0x1u << 30) /**< \brief (SAMHS_DEV_IEN) DMA Channel 6 Interrupt Enable */ +/* -------- SAMHS_DEV_INTSTA : (SAMHS Offset: 0x14) SAMHS Interrupt Status Register -------- */ +#define SAMHS_DEV_INTSTA_SPEED (0x1u << 0) /**< \brief (SAMHS_DEV_INTSTA) Speed Status */ +#define SAMHS_DEV_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (SAMHS_DEV_INTSTA) Suspend Interrupt */ +#define SAMHS_DEV_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (SAMHS_DEV_INTSTA) Micro Start Of Frame Interrupt */ +#define SAMHS_DEV_INTSTA_INT_SOF (0x1u << 3) /**< \brief (SAMHS_DEV_INTSTA) Start Of Frame Interrupt */ +#define SAMHS_DEV_INTSTA_ENDRESET (0x1u << 4) /**< \brief (SAMHS_DEV_INTSTA) End Of Reset Interrupt */ +#define SAMHS_DEV_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (SAMHS_DEV_INTSTA) Wake Up CPU Interrupt */ +#define SAMHS_DEV_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (SAMHS_DEV_INTSTA) End Of Resume Interrupt */ +#define SAMHS_DEV_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (SAMHS_DEV_INTSTA) Upstream Resume Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_0 (0x1u << 8) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 0 Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_1 (0x1u << 9) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 1 Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_2 (0x1u << 10) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 2 Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_3 (0x1u << 11) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 3 Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_4 (0x1u << 12) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 4 Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_5 (0x1u << 13) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 5 Interrupt */ +#define SAMHS_DEV_INTSTA_EPT_6 (0x1u << 14) /**< \brief (SAMHS_DEV_INTSTA) Endpoint 6 Interrupt */ +#define SAMHS_DEV_INTSTA_DMA_1 (0x1u << 25) /**< \brief (SAMHS_DEV_INTSTA) DMA Channel 1 Interrupt */ +#define SAMHS_DEV_INTSTA_DMA_2 (0x1u << 26) /**< \brief (SAMHS_DEV_INTSTA) DMA Channel 2 Interrupt */ +#define SAMHS_DEV_INTSTA_DMA_3 (0x1u << 27) /**< \brief (SAMHS_DEV_INTSTA) DMA Channel 3 Interrupt */ +#define SAMHS_DEV_INTSTA_DMA_4 (0x1u << 28) /**< \brief (SAMHS_DEV_INTSTA) DMA Channel 4 Interrupt */ +#define SAMHS_DEV_INTSTA_DMA_5 (0x1u << 29) /**< \brief (SAMHS_DEV_INTSTA) DMA Channel 5 Interrupt */ +#define SAMHS_DEV_INTSTA_DMA_6 (0x1u << 30) /**< \brief (SAMHS_DEV_INTSTA) DMA Channel 6 Interrupt */ +/* -------- SAMHS_DEV_CLRINT : (SAMHS Offset: 0x18) SAMHS Clear Interrupt Register -------- */ +#define SAMHS_DEV_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (SAMHS_DEV_CLRINT) Suspend Interrupt Clear */ +#define SAMHS_DEV_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (SAMHS_DEV_CLRINT) Micro Start Of Frame Interrupt Clear */ +#define SAMHS_DEV_CLRINT_INT_SOF (0x1u << 3) /**< \brief (SAMHS_DEV_CLRINT) Start Of Frame Interrupt Clear */ +#define SAMHS_DEV_CLRINT_ENDRESET (0x1u << 4) /**< \brief (SAMHS_DEV_CLRINT) End Of Reset Interrupt Clear */ +#define SAMHS_DEV_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (SAMHS_DEV_CLRINT) Wake Up CPU Interrupt Clear */ +#define SAMHS_DEV_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (SAMHS_DEV_CLRINT) End Of Resume Interrupt Clear */ +#define SAMHS_DEV_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (SAMHS_DEV_CLRINT) Upstream Resume Interrupt Clear */ +/* -------- SAMHS_DEV_EPTRST : (SAMHS Offset: 0x1C) SAMHS Endpoints Reset Register -------- */ +#define SAMHS_DEV_EPTRST_EPT_0 (0x1u << 0) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 0 Reset */ +#define SAMHS_DEV_EPTRST_EPT_1 (0x1u << 1) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 1 Reset */ +#define SAMHS_DEV_EPTRST_EPT_2 (0x1u << 2) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 2 Reset */ +#define SAMHS_DEV_EPTRST_EPT_3 (0x1u << 3) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 3 Reset */ +#define SAMHS_DEV_EPTRST_EPT_4 (0x1u << 4) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 4 Reset */ +#define SAMHS_DEV_EPTRST_EPT_5 (0x1u << 5) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 5 Reset */ +#define SAMHS_DEV_EPTRST_EPT_6 (0x1u << 6) /**< \brief (SAMHS_DEV_EPTRST) Endpoint 6 Reset */ +/* -------- SAMHS_DEV_TST : (SAMHS Offset: 0xE0) SAMHS Test Register -------- */ +#define SAMHS_DEV_TST_SPEED_CFG_Pos 0 +#define SAMHS_DEV_TST_SPEED_CFG_Msk (0x3u << SAMHS_DEV_TST_SPEED_CFG_Pos) /**< \brief (SAMHS_DEV_TST) Speed Configuration */ +#define SAMHS_DEV_TST_SPEED_CFG(value) ((SAMHS_DEV_TST_SPEED_CFG_Msk & ((value) << SAMHS_DEV_TST_SPEED_CFG_Pos))) +#define SAMHS_DEV_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (SAMHS_DEV_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */ +#define SAMHS_DEV_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (SAMHS_DEV_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */ +#define SAMHS_DEV_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (SAMHS_DEV_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */ +#define SAMHS_DEV_TST_TST_J (0x1u << 2) /**< \brief (SAMHS_DEV_TST) Test J Mode */ +#define SAMHS_DEV_TST_TST_K (0x1u << 3) /**< \brief (SAMHS_DEV_TST) Test K Mode */ +#define SAMHS_DEV_TST_TST_PKT (0x1u << 4) /**< \brief (SAMHS_DEV_TST) Test Packet Mode */ +#define SAMHS_DEV_TST_OPMODE2 (0x1u << 5) /**< \brief (SAMHS_DEV_TST) OpMode2 */ +/* -------- SAMHS_DEV_EPTCFG : (SAMHS Offset: N/A) SAMHS Endpoint Configuration Register -------- */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_Pos 0 +#define SAMHS_DEV_EPTCFG_EPT_SIZE_Msk (0x7u << SAMHS_DEV_EPTCFG_EPT_SIZE_Pos) /**< \brief (SAMHS_DEV_EPTCFG) Endpoint Size */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE(value) ((SAMHS_DEV_EPTCFG_EPT_SIZE_Msk & ((value) << SAMHS_DEV_EPTCFG_EPT_SIZE_Pos))) +#define SAMHS_DEV_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 8 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 16 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 32 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 64 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 128 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 256 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 512 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (SAMHS_DEV_EPTCFG) 1024 bytes */ +#define SAMHS_DEV_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (SAMHS_DEV_EPTCFG) Endpoint Direction */ +#define SAMHS_DEV_EPTCFG_EPT_TYPE_Pos 4 +#define SAMHS_DEV_EPTCFG_EPT_TYPE_Msk (0x3u << SAMHS_DEV_EPTCFG_EPT_TYPE_Pos) /**< \brief (SAMHS_DEV_EPTCFG) Endpoint Type */ +#define SAMHS_DEV_EPTCFG_EPT_TYPE(value) ((SAMHS_DEV_EPTCFG_EPT_TYPE_Msk & ((value) << SAMHS_DEV_EPTCFG_EPT_TYPE_Pos))) +#define SAMHS_DEV_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (SAMHS_DEV_EPTCFG) Control endpoint */ +#define SAMHS_DEV_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (SAMHS_DEV_EPTCFG) Isochronous endpoint */ +#define SAMHS_DEV_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (SAMHS_DEV_EPTCFG) Bulk endpoint */ +#define SAMHS_DEV_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (SAMHS_DEV_EPTCFG) Interrupt endpoint */ +#define SAMHS_DEV_EPTCFG_BK_NUMBER_Pos 6 +#define SAMHS_DEV_EPTCFG_BK_NUMBER_Msk (0x3u << SAMHS_DEV_EPTCFG_BK_NUMBER_Pos) /**< \brief (SAMHS_DEV_EPTCFG) Number of Banks */ +#define SAMHS_DEV_EPTCFG_BK_NUMBER(value) ((SAMHS_DEV_EPTCFG_BK_NUMBER_Msk & ((value) << SAMHS_DEV_EPTCFG_BK_NUMBER_Pos))) +#define SAMHS_DEV_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (SAMHS_DEV_EPTCFG) Zero bank, the endpoint is not mapped in memory */ +#define SAMHS_DEV_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (SAMHS_DEV_EPTCFG) One bank (bank 0) */ +#define SAMHS_DEV_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (SAMHS_DEV_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */ +#define SAMHS_DEV_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (SAMHS_DEV_EPTCFG) Triple bank (bank0/bank1/bank2) */ +#define SAMHS_DEV_EPTCFG_NB_TRANS_Pos 8 +#define SAMHS_DEV_EPTCFG_NB_TRANS_Msk (0x3u << SAMHS_DEV_EPTCFG_NB_TRANS_Pos) /**< \brief (SAMHS_DEV_EPTCFG) Number Of Transaction per Microframe */ +#define SAMHS_DEV_EPTCFG_NB_TRANS(value) ((SAMHS_DEV_EPTCFG_NB_TRANS_Msk & ((value) << SAMHS_DEV_EPTCFG_NB_TRANS_Pos))) +#define SAMHS_DEV_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (SAMHS_DEV_EPTCFG) Endpoint Mapped */ +/* -------- SAMHS_DEV_EPTCTLENB : (SAMHS Offset: N/A) SAMHS Endpoint Control Enable Register -------- */ +#define SAMHS_DEV_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (SAMHS_DEV_EPTCTLENB) Endpoint Enable */ +#define SAMHS_DEV_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (SAMHS_DEV_EPTCTLENB) Packet Auto-Valid Enable */ +#define SAMHS_DEV_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (SAMHS_DEV_EPTCTLENB) Interrupts Disable DMA */ +#define SAMHS_DEV_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (SAMHS_DEV_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */ +#define SAMHS_DEV_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (SAMHS_DEV_EPTCTLENB) Overflow Error Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_RXRDY_TXKL (0x1u << 9) /**< \brief (SAMHS_DEV_EPTCTLENB) Received OUT Data Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (SAMHS_DEV_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_TXRDY (0x1u << 11) /**< \brief (SAMHS_DEV_EPTCTLENB) TX Packet Ready Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCTLENB) Received SETUP */ +#define SAMHS_DEV_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCTLENB) Stall Sent Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCTLENB) NAKIN Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (SAMHS_DEV_EPTCTLENB) NAKOUT Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (SAMHS_DEV_EPTCTLENB) Busy Bank Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (SAMHS_DEV_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (SAMHS_DEV_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ +#define SAMHS_DEV_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (SAMHS_DEV_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ +#define SAMHS_DEV_EPTCTLENB_TXRDY_TRER (0x1u << 11) /**< \brief (SAMHS_DEV_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCTLENB) Error Flow Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_ERR_CRC_NTR (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCTLENB) ISO CRC Error/Number of Transaction Error Interrupt Enable */ +#define SAMHS_DEV_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCTLENB) Bank Flush Error Interrupt Enable */ +/* -------- SAMHS_DEV_EPTCTLDIS : (SAMHS Offset: N/A) SAMHS Endpoint Control Disable Register -------- */ +#define SAMHS_DEV_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (SAMHS_DEV_EPTCTLDIS) Endpoint Disable */ +#define SAMHS_DEV_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (SAMHS_DEV_EPTCTLDIS) Packet Auto-Valid Disable */ +#define SAMHS_DEV_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (SAMHS_DEV_EPTCTLDIS) Interrupts Disable DMA */ +#define SAMHS_DEV_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (SAMHS_DEV_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */ +#define SAMHS_DEV_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (SAMHS_DEV_EPTCTLDIS) Overflow Error Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_RXRDY_TXKL (0x1u << 9) /**< \brief (SAMHS_DEV_EPTCTLDIS) Received OUT Data Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (SAMHS_DEV_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_TXRDY (0x1u << 11) /**< \brief (SAMHS_DEV_EPTCTLDIS) TX Packet Ready Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCTLDIS) Received SETUP Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCTLDIS) Stall Sent Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCTLDIS) NAKIN Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (SAMHS_DEV_EPTCTLDIS) NAKOUT Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (SAMHS_DEV_EPTCTLDIS) Busy Bank Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (SAMHS_DEV_EPTCTLDIS) Short Packet Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (SAMHS_DEV_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ +#define SAMHS_DEV_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (SAMHS_DEV_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ +#define SAMHS_DEV_EPTCTLDIS_TXRDY_TRER (0x1u << 11) /**< \brief (SAMHS_DEV_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCTLDIS) Error Flow Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_ERR_CRC_NTR (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCTLDIS) ISO CRC Error/Number of Transaction Error Interrupt Disable */ +#define SAMHS_DEV_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCTLDIS) bank flush error Interrupt Disable */ +/* -------- SAMHS_DEV_EPTCTL : (SAMHS Offset: N/A) SAMHS Endpoint Control Register -------- */ +#define SAMHS_DEV_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (SAMHS_DEV_EPTCTL) Endpoint Enable */ +#define SAMHS_DEV_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (SAMHS_DEV_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ +#define SAMHS_DEV_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (SAMHS_DEV_EPTCTL) Interrupt Disables DMA */ +#define SAMHS_DEV_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (SAMHS_DEV_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */ +#define SAMHS_DEV_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (SAMHS_DEV_EPTCTL) Overflow Error Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_RXRDY_TXKL (0x1u << 9) /**< \brief (SAMHS_DEV_EPTCTL) Received OUT Data Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (SAMHS_DEV_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_TXRDY (0x1u << 11) /**< \brief (SAMHS_DEV_EPTCTL) TX Packet Ready Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCTL) Received SETUP Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCTL) Stall Sent Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCTL) NAKIN Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (SAMHS_DEV_EPTCTL) NAKOUT Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (SAMHS_DEV_EPTCTL) Busy Bank Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (SAMHS_DEV_EPTCTL) Short Packet Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (SAMHS_DEV_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ +#define SAMHS_DEV_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (SAMHS_DEV_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ +#define SAMHS_DEV_EPTCTL_TXRDY_TRER (0x1u << 11) /**< \brief (SAMHS_DEV_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCTL) Error Flow Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_ERR_CRC_NTR (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCTL) ISO CRC Error/Number of Transaction Error Interrupt Enabled */ +#define SAMHS_DEV_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCTL) Bank Flush Error Interrupt Enabled */ +/* -------- SAMHS_DEV_EPTSETSTA : (SAMHS Offset: N/A) SAMHS Endpoint Set Status Register -------- */ +#define SAMHS_DEV_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (SAMHS_DEV_EPTSETSTA) Stall Handshake Request Set */ +#define SAMHS_DEV_EPTSETSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (SAMHS_DEV_EPTSETSTA) KILL Bank Set (for IN Endpoint) */ +#define SAMHS_DEV_EPTSETSTA_TXRDY (0x1u << 11) /**< \brief (SAMHS_DEV_EPTSETSTA) TX Packet Ready Set */ +#define SAMHS_DEV_EPTSETSTA_TXRDY_TRER (0x1u << 11) /**< \brief (SAMHS_DEV_EPTSETSTA) TX Packet Ready Set */ +/* -------- SAMHS_DEV_EPTCLRSTA : (SAMHS Offset: N/A) SAMHS Endpoint Clear Status Register -------- */ +#define SAMHS_DEV_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (SAMHS_DEV_EPTCLRSTA) Stall Handshake Request Clear */ +#define SAMHS_DEV_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (SAMHS_DEV_EPTCLRSTA) Data Toggle Clear */ +#define SAMHS_DEV_EPTCLRSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (SAMHS_DEV_EPTCLRSTA) Received OUT Data Clear */ +#define SAMHS_DEV_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (SAMHS_DEV_EPTCLRSTA) Transmitted IN Data Complete Clear */ +#define SAMHS_DEV_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCLRSTA) Received SETUP Clear */ +#define SAMHS_DEV_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCLRSTA) Stall Sent Clear */ +#define SAMHS_DEV_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCLRSTA) NAKIN Clear */ +#define SAMHS_DEV_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (SAMHS_DEV_EPTCLRSTA) NAKOUT Clear */ +#define SAMHS_DEV_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (SAMHS_DEV_EPTCLRSTA) Error Flow Clear */ +#define SAMHS_DEV_EPTCLRSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (SAMHS_DEV_EPTCLRSTA) Number of Transaction Error Clear */ +#define SAMHS_DEV_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (SAMHS_DEV_EPTCLRSTA) Bank Flush Error Clear */ +/* -------- SAMHS_DEV_EPTSTA : (SAMHS Offset: N/A) SAMHS Endpoint Status Register -------- */ +#define SAMHS_DEV_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (SAMHS_DEV_EPTSTA) Stall Handshake Request */ +#define SAMHS_DEV_EPTSTA_TOGGLESQ_STA_Pos 6 +#define SAMHS_DEV_EPTSTA_TOGGLESQ_STA_Msk (0x3u << SAMHS_DEV_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (SAMHS_DEV_EPTSTA) Toggle Sequencing */ +#define SAMHS_DEV_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (SAMHS_DEV_EPTSTA) DATA0 */ +#define SAMHS_DEV_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (SAMHS_DEV_EPTSTA) DATA1 */ +#define SAMHS_DEV_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (SAMHS_DEV_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */ +#define SAMHS_DEV_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (SAMHS_DEV_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */ +#define SAMHS_DEV_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (SAMHS_DEV_EPTSTA) Overflow Error */ +#define SAMHS_DEV_EPTSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (SAMHS_DEV_EPTSTA) Received OUT Data/KILL Bank */ +#define SAMHS_DEV_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (SAMHS_DEV_EPTSTA) Transmitted IN Data Complete */ +#define SAMHS_DEV_EPTSTA_TXRDY (0x1u << 11) /**< \brief (SAMHS_DEV_EPTSTA) TX Packet Ready */ +#define SAMHS_DEV_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (SAMHS_DEV_EPTSTA) Received SETUP */ +#define SAMHS_DEV_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (SAMHS_DEV_EPTSTA) Stall Sent */ +#define SAMHS_DEV_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (SAMHS_DEV_EPTSTA) NAK IN */ +#define SAMHS_DEV_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (SAMHS_DEV_EPTSTA) NAK OUT */ +#define SAMHS_DEV_EPTSTA_CURBK_CTLDIR_Pos 16 +#define SAMHS_DEV_EPTSTA_CURBK_CTLDIR_Msk (0x3u << SAMHS_DEV_EPTSTA_CURBK_CTLDIR_Pos) /**< \brief (SAMHS_DEV_EPTSTA) Current Bank/Control Direction */ +#define SAMHS_DEV_EPTSTA_BUSY_BANK_STA_Pos 18 +#define SAMHS_DEV_EPTSTA_BUSY_BANK_STA_Msk (0x3u << SAMHS_DEV_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (SAMHS_DEV_EPTSTA) Busy Bank Number */ +#define SAMHS_DEV_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (SAMHS_DEV_EPTSTA) 1 busy bank */ +#define SAMHS_DEV_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (SAMHS_DEV_EPTSTA) 2 busy banks */ +#define SAMHS_DEV_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (SAMHS_DEV_EPTSTA) 3 busy banks */ +#define SAMHS_DEV_EPTSTA_BYTE_COUNT_Pos 20 +#define SAMHS_DEV_EPTSTA_BYTE_COUNT_Msk (0x7ffu << SAMHS_DEV_EPTSTA_BYTE_COUNT_Pos) /**< \brief (SAMHS_DEV_EPTSTA) SAMHS Byte Count */ +#define SAMHS_DEV_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (SAMHS_DEV_EPTSTA) Short Packet */ +#define SAMHS_DEV_EPTSTA_TXRDY_TRER (0x1u << 11) /**< \brief (SAMHS_DEV_EPTSTA) TX Packet Ready/Transaction Error */ +#define SAMHS_DEV_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (SAMHS_DEV_EPTSTA) Error Flow */ +#define SAMHS_DEV_EPTSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (SAMHS_DEV_EPTSTA) CRC ISO Error/Number of Transaction Error */ +#define SAMHS_DEV_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (SAMHS_DEV_EPTSTA) Bank Flush Error */ +#define SAMHS_DEV_EPTSTA_CURBK_Pos 16 +#define SAMHS_DEV_EPTSTA_CURBK_Msk (0x3u << SAMHS_DEV_EPTSTA_CURBK_Pos) /**< \brief (SAMHS_DEV_EPTSTA) Current Bank */ +#define SAMHS_DEV_EPTSTA_CURBK_BANK0 (0x0u << 16) /**< \brief (SAMHS_DEV_EPTSTA) Bank 0 (or single bank) */ +#define SAMHS_DEV_EPTSTA_CURBK_BANK1 (0x1u << 16) /**< \brief (SAMHS_DEV_EPTSTA) Bank 1 */ +#define SAMHS_DEV_EPTSTA_CURBK_BANK2 (0x2u << 16) /**< \brief (SAMHS_DEV_EPTSTA) Bank 2 */ +/* -------- SAMHS_DEV_DMANXTDSC : (SAMHS Offset: N/A) SAMHS DMA Next Descriptor Address Register -------- */ +#define SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Pos 0 +#define SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (SAMHS_DEV_DMANXTDSC) Next Descriptor Address */ +#define SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD(value) ((SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- SAMHS_DEV_DMAADDRESS : (SAMHS Offset: N/A) SAMHS DMA Channel Address Register -------- */ +#define SAMHS_DEV_DMAADDRESS_BUFF_ADD_Pos 0 +#define SAMHS_DEV_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << SAMHS_DEV_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (SAMHS_DEV_DMAADDRESS) Buffer Address */ +#define SAMHS_DEV_DMAADDRESS_BUFF_ADD(value) ((SAMHS_DEV_DMAADDRESS_BUFF_ADD_Msk & ((value) << SAMHS_DEV_DMAADDRESS_BUFF_ADD_Pos))) +/* -------- SAMHS_DEV_DMACONTROL : (SAMHS Offset: N/A) SAMHS DMA Channel Control Register -------- */ +#define SAMHS_DEV_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (SAMHS_DEV_DMACONTROL) (Channel Enable Command) */ +#define SAMHS_DEV_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (SAMHS_DEV_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */ +#define SAMHS_DEV_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (SAMHS_DEV_DMACONTROL) End of Transfer Enable (Control) */ +#define SAMHS_DEV_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (SAMHS_DEV_DMACONTROL) End of Buffer Enable (Control) */ +#define SAMHS_DEV_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (SAMHS_DEV_DMACONTROL) End of Transfer Interrupt Enable */ +#define SAMHS_DEV_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (SAMHS_DEV_DMACONTROL) End of Buffer Interrupt Enable */ +#define SAMHS_DEV_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (SAMHS_DEV_DMACONTROL) Descriptor Loaded Interrupt Enable */ +#define SAMHS_DEV_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (SAMHS_DEV_DMACONTROL) Burst Lock Enable */ +#define SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos 16 +#define SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (SAMHS_DEV_DMACONTROL) Buffer Byte Length (Write-only) */ +#define SAMHS_DEV_DMACONTROL_BUFF_LENGTH(value) ((SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Msk & ((value) << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos))) +/* -------- SAMHS_DEV_DMASTATUS : (SAMHS Offset: N/A) SAMHS DMA Channel Status Register -------- */ +#define SAMHS_DEV_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (SAMHS_DEV_DMASTATUS) Channel Enable Status */ +#define SAMHS_DEV_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (SAMHS_DEV_DMASTATUS) Channel Active Status */ +#define SAMHS_DEV_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (SAMHS_DEV_DMASTATUS) End of Channel Transfer Status */ +#define SAMHS_DEV_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (SAMHS_DEV_DMASTATUS) End of Channel Buffer Status */ +#define SAMHS_DEV_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (SAMHS_DEV_DMASTATUS) Descriptor Loaded Status */ +#define SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos 16 +#define SAMHS_DEV_DMASTATUS_BUFF_COUNT_Msk (0xffffu << SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (SAMHS_DEV_DMASTATUS) Buffer Byte Count */ +#define SAMHS_DEV_DMASTATUS_BUFF_COUNT(value) ((SAMHS_DEV_DMASTATUS_BUFF_COUNT_Msk & ((value) << SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos))) + + +/** \brief samhs_dma hardware registers */ +typedef struct { + __IO uint32_t SAMHS_DEV_DMANXTDSC; /**< \brief (samhs_dma Offset: 0x0) SAMHS DMA Next Descriptor Address Register */ + __IO uint32_t SAMHS_DEV_DMAADDRESS; /**< \brief (samhs_dma Offset: 0x4) SAMHS DMA Channel Address Register */ + __IO uint32_t SAMHS_DEV_DMACONTROL; /**< \brief (samhs_dma Offset: 0x8) SAMHS DMA Channel Control Register */ + __IO uint32_t SAMHS_DEV_DMASTATUS; /**< \brief (samhs_dma Offset: 0xC) SAMHS DMA Channel Status Register */ +} samhs_dma_t; + +/** \brief samhs_ept hardware registers */ +typedef struct { + __IO uint32_t SAMHS_DEV_EPTCFG; /**< \brief (samhs_ept Offset: 0x0) SAMHS Endpoint Configuration Register */ + __O uint32_t SAMHS_DEV_EPTCTLENB; /**< \brief (samhs_ept Offset: 0x4) SAMHS Endpoint Control Enable Register */ + __O uint32_t SAMHS_DEV_EPTCTLDIS; /**< \brief (samhs_ept Offset: 0x8) SAMHS Endpoint Control Disable Register */ + __I uint32_t SAMHS_DEV_EPTCTL; /**< \brief (samhs_ept Offset: 0xC) SAMHS Endpoint Control Register */ + __I uint32_t Reserved1[1]; + __O uint32_t SAMHS_DEV_EPTSETSTA; /**< \brief (samhs_ept Offset: 0x14) SAMHS Endpoint Set Status Register */ + __O uint32_t SAMHS_DEV_EPTCLRSTA; /**< \brief (samhs_ept Offset: 0x18) SAMHS Endpoint Clear Status Register */ + __I uint32_t SAMHS_DEV_EPTSTA; /**< \brief (samhs_ept Offset: 0x1C) SAMHS Endpoint Status Register */ +} samhs_ept_t; + +/** \brief samhs_reg hardware registers */ +#define SAMHS_EPT_NUMBER 7 +#define SAMHS_DMA_NUMBER 6 + +typedef struct { + __IO uint32_t SAMHS_DEV_CTRL; /**< \brief (samhs_reg Offset: 0x00) SAMHS Control Register */ + __I uint32_t SAMHS_DEV_FNUM; /**< \brief (samhs_reg Offset: 0x04) SAMHS Frame Number Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SAMHS_DEV_IEN; /**< \brief (samhs_reg Offset: 0x10) SAMHS Interrupt Enable Register */ + __I uint32_t SAMHS_DEV_INTSTA; /**< \brief (samhs_reg Offset: 0x14) SAMHS Interrupt Status Register */ + __O uint32_t SAMHS_DEV_CLRINT; /**< \brief (samhs_reg Offset: 0x18) SAMHS Clear Interrupt Register */ + __O uint32_t SAMHS_DEV_EPTRST; /**< \brief (samhs_reg Offset: 0x1C) SAMHS Endpoints Reset Register */ + __I uint32_t Reserved2[48]; + __IO uint32_t SAMHS_DEV_TST; /**< \brief (samhs_reg Offset: 0xE0) SAMHS Test Register */ + __I uint32_t Reserved3[7]; + samhs_ept_t SAMHS_DEV_EPT[SAMHS_EPT_NUMBER]; /**< \brief (samhs_reg Offset: 0x100) endpoint = 0 .. 6 */ + __I uint32_t Reserved4[72]; + samhs_dma_t SAMHS_DEV_DMA[SAMHS_DMA_NUMBER]; /**< \brief (samhs_reg Offset: 0x300) channel = 0 .. 5 */ +} samhs_reg_t; + +#define SAMHS_BASE_REG (0x400A4000U) /**< \brief (USBHS) Base Address */ + +#define EP_MAX 7 + +#define FIFO_RAM_ADDR (0x20180000U) + +// Errata: The DMA feature is not available for Pipe/Endpoint 7 +#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6) + +#endif /* _SAMHS_SAM3U_H_ */ diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samhs/dcd_samhs.c similarity index 64% rename from src/portable/microchip/samx7x/dcd_samx7x.c rename to src/portable/microchip/samhs/dcd_samhs.c index 7507c0f69c..751a2d2dfe 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samhs/dcd_samhs.c @@ -27,15 +27,21 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X +#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_SAMX7X) #include "device/dcd.h" #include "sam.h" -#include "common_usb_regs.h" + +#if TU_CHECK_MCU(OPT_MCU_SAMX7X) +#include "samhs_samx7x.h" +#endif //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ +// SAMHS registers +#define SAMHS_REG ((samhs_reg_t*) SAMHS_BASE_REG) + // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) // We disable SOF for now until needed later on #ifndef USE_SOF @@ -43,7 +49,7 @@ #endif // Dual bank can imporve performance, but need 2 times bigger packet buffer -// As SAM7x has only 4KB packet buffer, use with caution ! +// Only 4KB packet buffer, use with caution ! // Enable in FS mode as packets are smaller #ifndef USE_DUAL_BANK # if TUD_OPT_HIGH_SPEED @@ -138,7 +144,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup (uint8_t rhport) { (void) rhport; - USB_REG->DEVCTRL |= DEVCTRL_RMWKUP; + SAMHS_REG->SAMHS_DEV_CTRL |= SAMHS_DEV_CTRL_RMWKUP; } // Connect by enabling internal pull-up resistor on D+/D- @@ -147,28 +153,28 @@ void dcd_connect(uint8_t rhport) (void) rhport; dcd_int_disable(rhport); // Enable the USB controller in device mode - USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE; - while (!(USB_REG->SR & SR_CLKUSABLE)); + SAMHS_REG->SAMHS_CTRL = CTRL_UIMOD | CTRL_USBE; + while (!(SAMHS_REG->SAMHS_SR & SR_CLKUSABLE)); #if TUD_OPT_HIGH_SPEED - USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF; + SAMHS_REG->SAMHS_DEV_CTRL &= ~SAMHS_DEV_CTRL_SPDCONF; #else - USB_REG->DEVCTRL |= DEVCTRL_SPDCONF_LOW_POWER; + SAMHS_REG->SAMHS_DEV_CTRL |= SAMHS_DEV_CTRL_SPDCONF_LOW_POWER; #endif // Enable the End Of Reset, Suspend & Wakeup interrupts - USB_REG->DEVIER = (DEVIER_EORSTES | DEVIER_SUSPES | DEVIER_WAKEUPES); + SAMHS_REG->SAMHS_DEV_IER = (SAMHS_DEV_IER_EORSTES | SAMHS_DEV_IER_SUSPES | SAMHS_DEV_IER_WAKEUPES); #if USE_SOF - USB_REG->DEVIER = DEVIER_SOFES; + SAMHS_REG->SAMHS_DEV_IER |= SAMHS_DEV_IER_SOFES; #endif // Clear the End Of Reset, SOF & Wakeup interrupts - USB_REG->DEVICR = (DEVICR_EORSTC | DEVICR_SOFC | DEVICR_WAKEUPC); + SAMHS_REG->SAMHS_DEV_ICR = (SAMHS_DEV_ICR_EORSTC | SAMHS_DEV_ICR_SOFC | SAMHS_DEV_ICR_WAKEUPC); // Manually set the Suspend Interrupt - USB_REG->DEVIFR |= DEVIFR_SUSPS; + SAMHS_REG->SAMHS_DEV_IFR |= SAMHS_DEV_IFR_SUSPS; // Ack the Wakeup Interrupt - USB_REG->DEVICR = DEVICR_WAKEUPC; + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_WAKEUPC; // Attach the device - USB_REG->DEVCTRL &= ~DEVCTRL_DETACH; + SAMHS_REG->SAMHS_DEV_CTRL &= ~SAMHS_DEV_CTRL_DETACH; // Freeze USB clock - USB_REG->CTRL |= CTRL_FRZCLK; + SAMHS_REG->SAMHS_CTRL |= CTRL_FRZCLK; } // Disconnect by disabling internal pull-up resistor on D+/D- @@ -177,18 +183,18 @@ void dcd_disconnect(uint8_t rhport) (void) rhport; dcd_int_disable(rhport); // Disable all endpoints - USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos); + SAMHS_REG->SAMHS_DEV_EPT &= ~(0x3FF << SAMHS_DEV_EPT_EPEN0_Pos); // Unfreeze USB clock - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)); + SAMHS_REG->SAMHS_CTRL &= ~CTRL_FRZCLK; + while (!(SAMHS_REG->SAMHS_SR & SR_CLKUSABLE)); // Clear all the pending interrupts - USB_REG->DEVICR = DEVICR_Msk; + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_Msk; // Disable all interrupts - USB_REG->DEVIDR = DEVIDR_Msk; + SAMHS_REG->SAMHS_DEV_IDR = SAMHS_DEV_IDR_Msk; // Detach the device - USB_REG->DEVCTRL |= DEVCTRL_DETACH; + SAMHS_REG->SAMHS_DEV_CTRL |= SAMHS_DEV_CTRL_DETACH; // Disable the device address - USB_REG->DEVCTRL &=~(DEVCTRL_ADDEN | DEVCTRL_UADD); + SAMHS_REG->SAMHS_DEV_CTRL &=~(SAMHS_DEV_CTRL_ADDEN | SAMHS_DEV_CTRL_UADD); } void dcd_sof_enable(uint8_t rhport, bool en) @@ -201,7 +207,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) static tusb_speed_t get_speed(void) { - switch (USB_REG->SR & SR_SPEED) { + switch (SAMHS_REG->SAMHS_SR & SR_SPEED) { case SR_SPEED_FULL_SPEED: default: return TUSB_SPEED_FULL; @@ -214,20 +220,20 @@ static tusb_speed_t get_speed(void) static void dcd_ep_handler(uint8_t ep_ix) { - uint32_t int_status = USB_REG->DEVEPTISR[ep_ix]; - int_status &= USB_REG->DEVEPTIMR[ep_ix]; + uint32_t int_status = SAMHS_REG->SAMHS_DEV_EPTISR[ep_ix]; + int_status &= SAMHS_REG->SAMHS_DEV_EPTIMR[ep_ix]; - uint16_t count = (USB_REG->DEVEPTISR[ep_ix] & - DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos; + uint16_t count = (SAMHS_REG->SAMHS_DEV_EPTISR[ep_ix] & + SAMHS_DEV_EPTISR_BYCT) >> SAMHS_DEV_EPTISR_BYCT_Pos; xfer_ctl_t *xfer = &xfer_status[ep_ix]; if (ep_ix == 0U) { static uint8_t ctrl_dir; - if (int_status & DEVEPTISR_CTRL_RXSTPI) + if (int_status & SAMHS_DEV_EPTISR_CTRL_RXSTPI) { - ctrl_dir = (USB_REG->DEVEPTISR[0] & DEVEPTISR_CTRL_CTRLDIR) >> DEVEPTISR_CTRL_CTRLDIR_Pos; + ctrl_dir = (SAMHS_REG->SAMHS_DEV_EPTISR[0] & SAMHS_DEV_EPTISR_CTRL_CTRLDIR) >> SAMHS_DEV_EPTISR_CTRL_CTRLDIR_Pos; // Setup packet should always be 8 bytes. If not, ignore it, and try again. if (count == 8) { @@ -235,10 +241,10 @@ static void dcd_ep_handler(uint8_t ep_ix) dcd_event_setup_received(0, ptr, true); } // Ack and disable SETUP interrupt - USB_REG->DEVEPTICR[0] = DEVEPTICR_CTRL_RXSTPIC; - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_RXSTPEC; + SAMHS_REG->SAMHS_DEV_EPTICR[0] = SAMHS_DEV_EPTICR_CTRL_RXSTPIC; + SAMHS_REG->SAMHS_DEV_EPTIDR[0] = SAMHS_DEV_EPTIDR_CTRL_RXSTPEC; } - if (int_status & DEVEPTISR_RXOUTI) + if (int_status & SAMHS_DEV_EPTISR_RXOUTI) { uint8_t *ptr = EP_GET_FIFO_PTR(0,8); @@ -259,24 +265,24 @@ static void dcd_ep_handler(uint8_t ep_ix) xfer->queued_len = (uint16_t)(xfer->queued_len + count); } // Acknowledge the interrupt - USB_REG->DEVEPTICR[0] = DEVEPTICR_RXOUTIC; + SAMHS_REG->SAMHS_DEV_EPTICR[0] = SAMHS_DEV_EPTICR_RXOUTIC; if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) { // RX COMPLETE dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true); // Disable the interrupt - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_RXOUTEC; + SAMHS_REG->SAMHS_DEV_EPTIDR[0] = SAMHS_DEV_EPTIDR_RXOUTEC; // Re-enable SETUP interrupt if (ctrl_dir == 1) { - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; + SAMHS_REG->SAMHS_DEV_EPTIER[0] = SAMHS_DEV_EPTIER_CTRL_RXSTPES; } } } - if (int_status & DEVEPTISR_TXINI) + if (int_status & SAMHS_DEV_EPTISR_TXINI) { // Disable the interrupt - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_TXINEC; + SAMHS_REG->SAMHS_DEV_EPTIDR[0] = SAMHS_DEV_EPTIDR_TXINEC; if ((xfer->total_len != xfer->queued_len)) { // TX not complete @@ -288,13 +294,13 @@ static void dcd_ep_handler(uint8_t ep_ix) // Re-enable SETUP interrupt if (ctrl_dir == 0) { - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; + SAMHS_REG->SAMHS_DEV_EPTIER[0] = SAMHS_DEV_EPTIER_CTRL_RXSTPES; } } } } else { - if (int_status & DEVEPTISR_RXOUTI) + if (int_status & SAMHS_DEV_EPTISR_RXOUTI) { if (count && xfer->total_len) { @@ -313,22 +319,22 @@ static void dcd_ep_handler(uint8_t ep_ix) xfer->queued_len = (uint16_t)(xfer->queued_len + count); } // Clear the FIFO control flag to receive more data. - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; + SAMHS_REG->SAMHS_DEV_EPTIDR[ep_ix] = SAMHS_DEV_EPTIDR_FIFOCONC; // Acknowledge the interrupt - USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_RXOUTIC; + SAMHS_REG->SAMHS_DEV_EPTICR[ep_ix] = SAMHS_DEV_EPTICR_RXOUTIC; if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) { // RX COMPLETE dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true); // Disable the interrupt - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_RXOUTEC; + SAMHS_REG->SAMHS_DEV_EPTIDR[ep_ix] = SAMHS_DEV_EPTIDR_RXOUTEC; // Though the host could still send, we don't know. } } - if (int_status & DEVEPTISR_TXINI) + if (int_status & SAMHS_DEV_EPTISR_TXINI) { // Acknowledge the interrupt - USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_TXINIC; + SAMHS_REG->SAMHS_DEV_EPTICR[ep_ix] = SAMHS_DEV_EPTICR_TXINIC; if ((xfer->total_len != xfer->queued_len)) { // TX not complete @@ -338,7 +344,7 @@ static void dcd_ep_handler(uint8_t ep_ix) // TX complete dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true); // Disable the interrupt - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_TXINEC; + SAMHS_REG->SAMHS_DEV_EPTIDR[ep_ix] = SAMHS_DEV_EPTIDR_TXINEC; } } } @@ -346,17 +352,17 @@ static void dcd_ep_handler(uint8_t ep_ix) static void dcd_dma_handler(uint8_t ep_ix) { - uint32_t status = USB_REG->DEVDMA[ep_ix - 1].DEVDMASTATUS; - if (status & DEVDMASTATUS_CHANN_ENB) + uint32_t status = SAMHS_REG->SAMHS_DEV_DMA[ep_ix - 1].SAMHS_DEV_DMASTATUS; + if (status & SAMHS_DEV_DMASTATUS_CHANN_ENB) { return; // Ignore EOT_STA interrupt } // Disable DMA interrupt - USB_REG->DEVIDR = DEVIDR_DMA_1 << (ep_ix - 1); + SAMHS_REG->SAMHS_DEV_IDR = SAMHS_DEV_IDR_DMA_1 << (ep_ix - 1); xfer_ctl_t *xfer = &xfer_status[ep_ix]; - uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos); - if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR) + uint16_t count = xfer->total_len - ((status & SAMHS_DEV_DMASTATUS_BUFF_COUNT) >> SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos); + if(SAMHS_REG->SAMHS_DEV_EPTCFG[ep_ix] & SAMHS_DEV_EPTCFG_EPDIR) { dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true); } else @@ -368,56 +374,56 @@ static void dcd_dma_handler(uint8_t ep_ix) void dcd_int_handler(uint8_t rhport) { (void) rhport; - uint32_t int_status = USB_REG->DEVISR; - int_status &= USB_REG->DEVIMR; + uint32_t int_status = SAMHS_REG->SAMHS_DEV_ISR; + int_status &= SAMHS_REG->SAMHS_DEV_IMR; // End of reset interrupt - if (int_status & DEVISR_EORST) + if (int_status & SAMHS_DEV_ISR_EORST) { // Unfreeze USB clock - USB_REG->CTRL &= ~CTRL_FRZCLK; - while(!(USB_REG->SR & SR_CLKUSABLE)); + SAMHS_REG->SAMHS_CTRL &= ~CTRL_FRZCLK; + while(!(SAMHS_REG->SAMHS_SR & SR_CLKUSABLE)); // Reset all endpoints for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) { - USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + ep_ix); - USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + ep_ix)); + SAMHS_REG->SAMHS_DEV_EPT |= 1 << (SAMHS_DEV_EPT_EPRST0_Pos + ep_ix); + SAMHS_REG->SAMHS_DEV_EPT &=~(1 << (SAMHS_DEV_EPT_EPRST0_Pos + ep_ix)); } dcd_edpt_open (0, &ep0_desc); - USB_REG->DEVICR = DEVICR_EORSTC; - USB_REG->DEVICR = DEVICR_WAKEUPC; - USB_REG->DEVICR = DEVICR_SUSPC; - USB_REG->DEVIER = DEVIER_SUSPES; + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_EORSTC; + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_WAKEUPC; + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_SUSPC; + SAMHS_REG->SAMHS_DEV_IER = SAMHS_DEV_IER_SUSPES; dcd_event_bus_reset(rhport, get_speed(), true); } // End of Wakeup interrupt - if (int_status & DEVISR_WAKEUP) + if (int_status & SAMHS_DEV_ISR_WAKEUP) { - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)); - USB_REG->DEVICR = DEVICR_WAKEUPC; - USB_REG->DEVIDR = DEVIDR_WAKEUPEC; - USB_REG->DEVIER = DEVIER_SUSPES; + SAMHS_REG->SAMHS_CTRL &= ~CTRL_FRZCLK; + while (!(SAMHS_REG->SAMHS_SR & SR_CLKUSABLE)); + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_WAKEUPC; + SAMHS_REG->SAMHS_DEV_IDR = SAMHS_DEV_IDR_WAKEUPEC; + SAMHS_REG->SAMHS_DEV_IER = SAMHS_DEV_IER_SUSPES; dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } // Suspend interrupt - if (int_status & DEVISR_SUSP) + if (int_status & SAMHS_DEV_ISR_SUSP) { // Unfreeze USB clock - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)); - USB_REG->DEVICR = DEVICR_SUSPC; - USB_REG->DEVIDR = DEVIDR_SUSPEC; - USB_REG->DEVIER = DEVIER_WAKEUPES; - USB_REG->CTRL |= CTRL_FRZCLK; + SAMHS_REG->SAMHS_CTRL &= ~CTRL_FRZCLK; + while (!(SAMHS_REG->SAMHS_SR & SR_CLKUSABLE)); + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_SUSPC; + SAMHS_REG->SAMHS_DEV_IDR = SAMHS_DEV_IDR_SUSPEC; + SAMHS_REG->SAMHS_DEV_IER = SAMHS_DEV_IER_WAKEUPES; + SAMHS_REG->SAMHS_CTRL |= CTRL_FRZCLK; dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } #if USE_SOF - if(int_status & DEVISR_SOF) + if(int_status & SAMHS_DEV_ISR_SOF) { - USB_REG->DEVICR = DEVICR_SOFC; + SAMHS_REG->SAMHS_DEV_ICR = SAMHS_DEV_ICR_SOFC; dcd_event_bus_signal(0, DCD_EVENT_SOF, true); } @@ -425,7 +431,7 @@ void dcd_int_handler(uint8_t rhport) // Endpoints interrupt for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) { - if (int_status & (DEVISR_PEP_0 << ep_ix)) + if (int_status & (SAMHS_DEV_ISR_PEP_0 << ep_ix)) { dcd_ep_handler(ep_ix); } @@ -435,7 +441,7 @@ void dcd_int_handler(uint8_t rhport) { if (EP_DMA_SUPPORT(ep_ix)) { - if (int_status & (DEVISR_DMA_1 << (ep_ix - 1))) + if (int_status & (SAMHS_DEV_ISR_DMA_1 << (ep_ix - 1))) { dcd_dma_handler(ep_ix); } @@ -458,7 +464,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re { uint8_t const dev_addr = (uint8_t) request->wValue; - USB_REG->DEVCTRL |= dev_addr | DEVCTRL_ADDEN; + SAMHS_REG->SAMHS_DEV_CTRL |= dev_addr | SAMHS_DEV_CTRL_ADDEN; } } @@ -483,29 +489,29 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) } xfer_status[epnum].max_packet_size = epMaxPktSize; - USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + epnum); - USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + epnum)); + SAMHS_REG->SAMHS_DEV_EPT |= 1 << (SAMHS_DEV_EPT_EPRST0_Pos + epnum); + SAMHS_REG->SAMHS_DEV_EPT &=~(1 << (SAMHS_DEV_EPT_EPRST0_Pos + epnum)); if (epnum == 0) { // Enable the control endpoint - Endpoint 0 - USB_REG->DEVEPT |= DEVEPT_EPEN0; + SAMHS_REG->SAMHS_DEV_EPT |= SAMHS_DEV_EPT_EPEN0; // Configure the Endpoint 0 configuration register - USB_REG->DEVEPTCFG[0] = + SAMHS_REG->SAMHS_DEV_EPTCFG[0] = ( - (fifoSize << DEVEPTCFG_EPSIZE_Pos) | - (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos) | - (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | - DEVEPTCFG_ALLOC + (fifoSize << SAMHS_DEV_EPTCFG_EPSIZE_Pos) | + (TUSB_XFER_CONTROL << SAMHS_DEV_EPTCFG_EPTYPE_Pos) | + (SAMHS_DEV_EPTCFG_EPBK_1_BANK << SAMHS_DEV_EPTCFG_EPBK_Pos) | + SAMHS_DEV_EPTCFG_ALLOC ); - USB_REG->DEVEPTIER[0] = DEVEPTIER_RSTDTS; - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_STALLRQC; - if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK)) + SAMHS_REG->SAMHS_DEV_EPTIER[0] = SAMHS_DEV_EPTIER_RSTDTS; + SAMHS_REG->SAMHS_DEV_EPTIDR[0] = SAMHS_DEV_EPTIDR_CTRL_STALLRQC; + if (SAMHS_DEV_EPTISR_CFGOK == (SAMHS_REG->SAMHS_DEV_EPTISR[0] & SAMHS_DEV_EPTISR_CFGOK)) { // Endpoint configuration is successful - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; + SAMHS_REG->SAMHS_DEV_EPTIER[0] = SAMHS_DEV_EPTIER_CTRL_RXSTPES; // Enable Endpoint 0 Interrupts - USB_REG->DEVIER = DEVIER_PEP_0; + SAMHS_REG->SAMHS_DEV_IER = SAMHS_DEV_IER_PEP_0; return true; } else { @@ -515,34 +521,34 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) } else { // Enable the endpoint - USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos); + SAMHS_REG->SAMHS_DEV_EPT |= ((0x01 << epnum) << SAMHS_DEV_EPT_EPEN0_Pos); // Set up the maxpacket size, fifo start address fifosize // and enable the interrupt. CLear the data toggle. // AUTOSW is needed for DMA ack ! - USB_REG->DEVEPTCFG[epnum] = + SAMHS_REG->SAMHS_DEV_EPTCFG[epnum] = ( - (fifoSize << DEVEPTCFG_EPSIZE_Pos) | - (eptype << DEVEPTCFG_EPTYPE_Pos) | - (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | - DEVEPTCFG_AUTOSW | - ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos) + (fifoSize << SAMHS_DEV_EPTCFG_EPSIZE_Pos) | + (eptype << SAMHS_DEV_EPTCFG_EPTYPE_Pos) | + (SAMHS_DEV_EPTCFG_EPBK_1_BANK << SAMHS_DEV_EPTCFG_EPBK_Pos) | + SAMHS_DEV_EPTCFG_AUTOSW | + ((dir & 0x01) << SAMHS_DEV_EPTCFG_EPDIR_Pos) ); if (eptype == TUSB_XFER_ISOCHRONOUS) { - USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_NBTRANS_1_TRANS; + SAMHS_REG->SAMHS_DEV_EPTCFG[epnum] |= SAMHS_DEV_EPTCFG_NBTRANS_1_TRANS; } #if USE_DUAL_BANK if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK) { - USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_EPBK_2_BANK; + SAMHS_REG->SAMHS_DEV_EPTCFG[epnum] |= SAMHS_DEV_EPTCFG_EPBK_2_BANK; } #endif - USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_ALLOC; - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS; - USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC; - if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK)) + SAMHS_REG->SAMHS_DEV_EPTCFG[epnum] |= SAMHS_DEV_EPTCFG_ALLOC; + SAMHS_REG->SAMHS_DEV_EPTIER[epnum] = SAMHS_DEV_EPTIER_RSTDTS; + SAMHS_REG->SAMHS_DEV_EPTIDR[epnum] = SAMHS_DEV_EPTIDR_CTRL_STALLRQC; + if (SAMHS_DEV_EPTISR_CFGOK == (SAMHS_REG->SAMHS_DEV_EPTISR[epnum] & SAMHS_DEV_EPTISR_CFGOK)) { - USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos); + SAMHS_REG->SAMHS_DEV_IER = ((0x01 << epnum) << SAMHS_DEV_IER_PEP_0_Pos); return true; } else { @@ -564,9 +570,9 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) uint8_t const epnum = tu_edpt_number(ep_addr); // Disable endpoint interrupt - USB_REG->DEVIDR = 1 << (DEVIDR_PEP_0_Pos + epnum); + SAMHS_REG->SAMHS_DEV_IDR = 1 << (SAMHS_DEV_IDR_PEP_0_Pos + epnum); // Disable EP - USB_REG->DEVEPT &=~(1 << (DEVEPT_EPEN0_Pos + epnum)); + SAMHS_REG->SAMHS_DEV_EPT &=~(1 << (SAMHS_DEV_EPT_EPEN0_Pos + epnum)); } static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) @@ -594,13 +600,13 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) if (ep_ix == 0U) { // Control endpoint: clear the interrupt flag to send the data - USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC; + SAMHS_REG->SAMHS_DEV_EPTICR[0] = SAMHS_DEV_EPTICR_TXINIC; } else { // Other endpoint types: clear the FIFO control flag to send the data - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; + SAMHS_REG->SAMHS_DEV_EPTIDR[ep_ix] = SAMHS_DEV_EPTIDR_FIFOCONC; } - USB_REG->DEVEPTIER[ep_ix] = DEVEPTIER_TXINES; + SAMHS_REG->SAMHS_DEV_EPTIER[ep_ix] = SAMHS_DEV_EPTIER_TXINES; } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack @@ -622,23 +628,23 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the // address to 32-byte boundaries. CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31); - uint32_t udd_dma_ctrl = total_bytes << DEVDMACONTROL_BUFF_LENGTH_Pos; + uint32_t udd_dma_ctrl = total_bytes << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos; if (dir == TUSB_DIR_OUT) { - udd_dma_ctrl |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; + udd_dma_ctrl |= SAMHS_DEV_DMACONTROL_END_TR_IT | SAMHS_DEV_DMACONTROL_END_TR_EN; } else { - udd_dma_ctrl |= DEVDMACONTROL_END_B_EN; + udd_dma_ctrl |= SAMHS_DEV_DMACONTROL_END_B_EN; } - USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)buffer; - udd_dma_ctrl |= DEVDMACONTROL_END_BUFFIT | DEVDMACONTROL_CHANN_ENB; + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMAADDRESS = (uint32_t)buffer; + udd_dma_ctrl |= SAMHS_DEV_DMACONTROL_END_BUFFIT | SAMHS_DEV_DMACONTROL_CHANN_ENB; // Disable IRQs to have a short sequence // between read of EOT_STA and DMA enable uint32_t irq_state = __get_PRIMASK(); __disable_irq(); - if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST)) + if (!(SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMASTATUS & SAMHS_DEV_DMASTATUS_END_TR_ST)) { - USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl; - USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMACONTROL = udd_dma_ctrl; + SAMHS_REG->SAMHS_DEV_IER = SAMHS_DEV_IER_DMA_1 << (epnum - 1); __set_PRIMASK(irq_state); return true; } @@ -652,7 +658,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { if (dir == TUSB_DIR_OUT) { - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; + SAMHS_REG->SAMHS_DEV_EPTIER[epnum] = SAMHS_DEV_EPTIER_RXOUTES; } else { dcd_transmit_packet(xfer,epnum); @@ -683,26 +689,26 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) { tu_fifo_buffer_info_t info; - uint32_t udd_dma_ctrl_lin = DEVDMACONTROL_CHANN_ENB; - uint32_t udd_dma_ctrl_wrap = DEVDMACONTROL_CHANN_ENB | DEVDMACONTROL_END_BUFFIT; + uint32_t udd_dma_ctrl_lin = SAMHS_DEV_DMACONTROL_CHANN_ENB; + uint32_t udd_dma_ctrl_wrap = SAMHS_DEV_DMACONTROL_CHANN_ENB | SAMHS_DEV_DMACONTROL_END_BUFFIT; if (dir == TUSB_DIR_OUT) { tu_fifo_get_write_info(ff, &info); - udd_dma_ctrl_lin |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; - udd_dma_ctrl_wrap |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; + udd_dma_ctrl_lin |= SAMHS_DEV_DMACONTROL_END_TR_IT | SAMHS_DEV_DMACONTROL_END_TR_EN; + udd_dma_ctrl_wrap |= SAMHS_DEV_DMACONTROL_END_TR_IT | SAMHS_DEV_DMACONTROL_END_TR_EN; } else { tu_fifo_get_read_info(ff, &info); if(info.len_wrap == 0) { - udd_dma_ctrl_lin |= DEVDMACONTROL_END_B_EN; + udd_dma_ctrl_lin |= SAMHS_DEV_DMACONTROL_END_B_EN; } - udd_dma_ctrl_wrap |= DEVDMACONTROL_END_B_EN; + udd_dma_ctrl_wrap |= SAMHS_DEV_DMACONTROL_END_B_EN; } // Clean invalidate cache of linear part CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31); - USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin; + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMAADDRESS = (uint32_t)info.ptr_lin; if (info.len_wrap) { // Clean invalidate cache of wrapped part @@ -711,24 +717,24 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 dma_desc[epnum - 1].next_desc = 0; dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap; dma_desc[epnum - 1].chnl_ctrl = - udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos); + udd_dma_ctrl_wrap | (info.len_wrap << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos); // Clean cache of wrapped DMA descriptor CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t)); - udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST; - USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1]; + udd_dma_ctrl_lin |= SAMHS_DEV_DMASTATUS_DESC_LDST; + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMANXTDSC = (uint32_t)&dma_desc[epnum - 1]; } else { - udd_dma_ctrl_lin |= DEVDMACONTROL_END_BUFFIT; + udd_dma_ctrl_lin |= SAMHS_DEV_DMACONTROL_END_BUFFIT; } - udd_dma_ctrl_lin |= (info.len_lin << DEVDMACONTROL_BUFF_LENGTH_Pos); + udd_dma_ctrl_lin |= (info.len_lin << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos); // Disable IRQs to have a short sequence // between read of EOT_STA and DMA enable uint32_t irq_state = __get_PRIMASK(); __disable_irq(); - if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST)) + if (!(SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMASTATUS & SAMHS_DEV_DMASTATUS_END_TR_ST)) { - USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl_lin; - USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); + SAMHS_REG->SAMHS_DEV_DMA[epnum - 1].SAMHS_DEV_DMACONTROL = udd_dma_ctrl_lin; + SAMHS_REG->SAMHS_DEV_IER = SAMHS_DEV_IER_DMA_1 << (epnum - 1); __set_PRIMASK(irq_state); return true; } @@ -742,7 +748,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 { if (dir == TUSB_DIR_OUT) { - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; + SAMHS_REG->SAMHS_DEV_EPTIER[epnum] = SAMHS_DEV_EPTIER_RXOUTES; } else { dcd_transmit_packet(xfer,epnum); @@ -756,11 +762,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_CTRL_STALLRQS; + SAMHS_REG->SAMHS_DEV_EPTIER[epnum] = SAMHS_DEV_EPTIER_CTRL_STALLRQS; // Re-enable SETUP interrupt if (epnum == 0) { - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; + SAMHS_REG->SAMHS_DEV_EPTIER[0] = SAMHS_DEV_EPTIER_CTRL_RXSTPES; } } @@ -769,8 +775,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC; - USB_REG->DEVEPTIER[epnum] = HSTPIPIER_RSTDTS; + SAMHS_REG->SAMHS_DEV_EPTIDR[epnum] = SAMHS_DEV_EPTIDR_CTRL_STALLRQC; + SAMHS_REG->SAMHS_DEV_EPTIER[epnum] = SAMHS_HST_PIPIER_RSTDTS; } #endif diff --git a/src/portable/microchip/samhs/samhs_samx7x.h b/src/portable/microchip/samhs/samhs_samx7x.h new file mode 100644 index 0000000000..1c669f0327 --- /dev/null +++ b/src/portable/microchip/samhs/samhs_samx7x.h @@ -0,0 +1,2101 @@ + /* +* The MIT License (MIT) +* +* Copyright (c) 2019 Microchip Technology Inc. +* Copyright (c) 2018, hathach (tinyusb.org) +* Copyright (c) 2021, HiFiPhile +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +* +* This file is part of the TinyUSB stack. +*/ + +#ifndef _SAMHS_SAMX7X_H_ +#define _SAMHS_SAMX7X_H_ + +/* -------- SAMHS_DEV_DMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */ + +#define SAMHS_DEV_DMANXTDSC_OFFSET (0x00) /**< (SAMHS_DEV_DMANXTDSC) Device DMA Channel Next Descriptor Address Register Offset */ + +#define SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (SAMHS_DEV_DMANXTDSC) Next Descriptor Address Position */ +#define SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD (_U_(0xFFFFFFFF) << SAMHS_DEV_DMANXTDSC_NXT_DSC_ADD_Pos) /**< (SAMHS_DEV_DMANXTDSC) Next Descriptor Address Mask */ +#define SAMHS_DEV_DMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (SAMHS_DEV_DMANXTDSC) Register Mask */ + + +/* -------- SAMHS_DEV_DMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */ + +#define SAMHS_DEV_DMAADDRESS_OFFSET (0x04) /**< (SAMHS_DEV_DMAADDRESS) Device DMA Channel Address Register Offset */ + +#define SAMHS_DEV_DMAADDRESS_BUFF_ADD_Pos 0 /**< (SAMHS_DEV_DMAADDRESS) Buffer Address Position */ +#define SAMHS_DEV_DMAADDRESS_BUFF_ADD (_U_(0xFFFFFFFF) << SAMHS_DEV_DMAADDRESS_BUFF_ADD_Pos) /**< (SAMHS_DEV_DMAADDRESS) Buffer Address Mask */ +#define SAMHS_DEV_DMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (SAMHS_DEV_DMAADDRESS) Register Mask */ + + +/* -------- SAMHS_DEV_DMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */ + +#define SAMHS_DEV_DMACONTROL_OFFSET (0x08) /**< (SAMHS_DEV_DMACONTROL) Device DMA Channel Control Register Offset */ + +#define SAMHS_DEV_DMACONTROL_CHANN_ENB_Pos 0 /**< (SAMHS_DEV_DMACONTROL) Channel Enable Command Position */ +#define SAMHS_DEV_DMACONTROL_CHANN_ENB (_U_(0x1) << SAMHS_DEV_DMACONTROL_CHANN_ENB_Pos) /**< (SAMHS_DEV_DMACONTROL) Channel Enable Command Mask */ +#define SAMHS_DEV_DMACONTROL_LDNXT_DSC_Pos 1 /**< (SAMHS_DEV_DMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define SAMHS_DEV_DMACONTROL_LDNXT_DSC (_U_(0x1) << SAMHS_DEV_DMACONTROL_LDNXT_DSC_Pos) /**< (SAMHS_DEV_DMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define SAMHS_DEV_DMACONTROL_END_TR_EN_Pos 2 /**< (SAMHS_DEV_DMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define SAMHS_DEV_DMACONTROL_END_TR_EN (_U_(0x1) << SAMHS_DEV_DMACONTROL_END_TR_EN_Pos) /**< (SAMHS_DEV_DMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define SAMHS_DEV_DMACONTROL_END_B_EN_Pos 3 /**< (SAMHS_DEV_DMACONTROL) End of Buffer Enable Control Position */ +#define SAMHS_DEV_DMACONTROL_END_B_EN (_U_(0x1) << SAMHS_DEV_DMACONTROL_END_B_EN_Pos) /**< (SAMHS_DEV_DMACONTROL) End of Buffer Enable Control Mask */ +#define SAMHS_DEV_DMACONTROL_END_TR_IT_Pos 4 /**< (SAMHS_DEV_DMACONTROL) End of Transfer Interrupt Enable Position */ +#define SAMHS_DEV_DMACONTROL_END_TR_IT (_U_(0x1) << SAMHS_DEV_DMACONTROL_END_TR_IT_Pos) /**< (SAMHS_DEV_DMACONTROL) End of Transfer Interrupt Enable Mask */ +#define SAMHS_DEV_DMACONTROL_END_BUFFIT_Pos 5 /**< (SAMHS_DEV_DMACONTROL) End of Buffer Interrupt Enable Position */ +#define SAMHS_DEV_DMACONTROL_END_BUFFIT (_U_(0x1) << SAMHS_DEV_DMACONTROL_END_BUFFIT_Pos) /**< (SAMHS_DEV_DMACONTROL) End of Buffer Interrupt Enable Mask */ +#define SAMHS_DEV_DMACONTROL_DESC_LD_IT_Pos 6 /**< (SAMHS_DEV_DMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define SAMHS_DEV_DMACONTROL_DESC_LD_IT (_U_(0x1) << SAMHS_DEV_DMACONTROL_DESC_LD_IT_Pos) /**< (SAMHS_DEV_DMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define SAMHS_DEV_DMACONTROL_BURST_LCK_Pos 7 /**< (SAMHS_DEV_DMACONTROL) Burst Lock Enable Position */ +#define SAMHS_DEV_DMACONTROL_BURST_LCK (_U_(0x1) << SAMHS_DEV_DMACONTROL_BURST_LCK_Pos) /**< (SAMHS_DEV_DMACONTROL) Burst Lock Enable Mask */ +#define SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos 16 /**< (SAMHS_DEV_DMACONTROL) Buffer Byte Length (Write-only) Position */ +#define SAMHS_DEV_DMACONTROL_BUFF_LENGTH (_U_(0xFFFF) << SAMHS_DEV_DMACONTROL_BUFF_LENGTH_Pos) /**< (SAMHS_DEV_DMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define SAMHS_DEV_DMACONTROL_Msk _U_(0xFFFF00FF) /**< (SAMHS_DEV_DMACONTROL) Register Mask */ + + +/* -------- SAMHS_DEV_DMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */ + +#define SAMHS_DEV_DMASTATUS_OFFSET (0x0C) /**< (SAMHS_DEV_DMASTATUS) Device DMA Channel Status Register Offset */ + +#define SAMHS_DEV_DMASTATUS_CHANN_ENB_Pos 0 /**< (SAMHS_DEV_DMASTATUS) Channel Enable Status Position */ +#define SAMHS_DEV_DMASTATUS_CHANN_ENB (_U_(0x1) << SAMHS_DEV_DMASTATUS_CHANN_ENB_Pos) /**< (SAMHS_DEV_DMASTATUS) Channel Enable Status Mask */ +#define SAMHS_DEV_DMASTATUS_CHANN_ACT_Pos 1 /**< (SAMHS_DEV_DMASTATUS) Channel Active Status Position */ +#define SAMHS_DEV_DMASTATUS_CHANN_ACT (_U_(0x1) << SAMHS_DEV_DMASTATUS_CHANN_ACT_Pos) /**< (SAMHS_DEV_DMASTATUS) Channel Active Status Mask */ +#define SAMHS_DEV_DMASTATUS_END_TR_ST_Pos 4 /**< (SAMHS_DEV_DMASTATUS) End of Channel Transfer Status Position */ +#define SAMHS_DEV_DMASTATUS_END_TR_ST (_U_(0x1) << SAMHS_DEV_DMASTATUS_END_TR_ST_Pos) /**< (SAMHS_DEV_DMASTATUS) End of Channel Transfer Status Mask */ +#define SAMHS_DEV_DMASTATUS_END_BF_ST_Pos 5 /**< (SAMHS_DEV_DMASTATUS) End of Channel Buffer Status Position */ +#define SAMHS_DEV_DMASTATUS_END_BF_ST (_U_(0x1) << SAMHS_DEV_DMASTATUS_END_BF_ST_Pos) /**< (SAMHS_DEV_DMASTATUS) End of Channel Buffer Status Mask */ +#define SAMHS_DEV_DMASTATUS_DESC_LDST_Pos 6 /**< (SAMHS_DEV_DMASTATUS) Descriptor Loaded Status Position */ +#define SAMHS_DEV_DMASTATUS_DESC_LDST (_U_(0x1) << SAMHS_DEV_DMASTATUS_DESC_LDST_Pos) /**< (SAMHS_DEV_DMASTATUS) Descriptor Loaded Status Mask */ +#define SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos 16 /**< (SAMHS_DEV_DMASTATUS) Buffer Byte Count Position */ +#define SAMHS_DEV_DMASTATUS_BUFF_COUNT (_U_(0xFFFF) << SAMHS_DEV_DMASTATUS_BUFF_COUNT_Pos) /**< (SAMHS_DEV_DMASTATUS) Buffer Byte Count Mask */ +#define SAMHS_DEV_DMASTATUS_Msk _U_(0xFFFF0073) /**< (SAMHS_DEV_DMASTATUS) Register Mask */ + + +/* -------- SAMHS_HST_DMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */ + +#define SAMHS_HST_DMANXTDSC_OFFSET (0x00) /**< (SAMHS_HST_DMANXTDSC) Host DMA Channel Next Descriptor Address Register Offset */ + +#define SAMHS_HST_DMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (SAMHS_HST_DMANXTDSC) Next Descriptor Address Position */ +#define SAMHS_HST_DMANXTDSC_NXT_DSC_ADD (_U_(0xFFFFFFFF) << SAMHS_HST_DMANXTDSC_NXT_DSC_ADD_Pos) /**< (SAMHS_HST_DMANXTDSC) Next Descriptor Address Mask */ +#define SAMHS_HST_DMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (SAMHS_HST_DMANXTDSC) Register Mask */ + + +/* -------- SAMHS_HST_DMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */ + +#define SAMHS_HST_DMAADDRESS_OFFSET (0x04) /**< (SAMHS_HST_DMAADDRESS) Host DMA Channel Address Register Offset */ + +#define SAMHS_HST_DMAADDRESS_BUFF_ADD_Pos 0 /**< (SAMHS_HST_DMAADDRESS) Buffer Address Position */ +#define SAMHS_HST_DMAADDRESS_BUFF_ADD (_U_(0xFFFFFFFF) << SAMHS_HST_DMAADDRESS_BUFF_ADD_Pos) /**< (SAMHS_HST_DMAADDRESS) Buffer Address Mask */ +#define SAMHS_HST_DMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (SAMHS_HST_DMAADDRESS) Register Mask */ + + +/* -------- SAMHS_HST_DMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */ + +#define SAMHS_HST_DMACONTROL_OFFSET (0x08) /**< (SAMHS_HST_DMACONTROL) Host DMA Channel Control Register Offset */ + +#define SAMHS_HST_DMACONTROL_CHANN_ENB_Pos 0 /**< (SAMHS_HST_DMACONTROL) Channel Enable Command Position */ +#define SAMHS_HST_DMACONTROL_CHANN_ENB (_U_(0x1) << SAMHS_HST_DMACONTROL_CHANN_ENB_Pos) /**< (SAMHS_HST_DMACONTROL) Channel Enable Command Mask */ +#define SAMHS_HST_DMACONTROL_LDNXT_DSC_Pos 1 /**< (SAMHS_HST_DMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define SAMHS_HST_DMACONTROL_LDNXT_DSC (_U_(0x1) << SAMHS_HST_DMACONTROL_LDNXT_DSC_Pos) /**< (SAMHS_HST_DMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define SAMHS_HST_DMACONTROL_END_TR_EN_Pos 2 /**< (SAMHS_HST_DMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define SAMHS_HST_DMACONTROL_END_TR_EN (_U_(0x1) << SAMHS_HST_DMACONTROL_END_TR_EN_Pos) /**< (SAMHS_HST_DMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define SAMHS_HST_DMACONTROL_END_B_EN_Pos 3 /**< (SAMHS_HST_DMACONTROL) End of Buffer Enable Control Position */ +#define SAMHS_HST_DMACONTROL_END_B_EN (_U_(0x1) << SAMHS_HST_DMACONTROL_END_B_EN_Pos) /**< (SAMHS_HST_DMACONTROL) End of Buffer Enable Control Mask */ +#define SAMHS_HST_DMACONTROL_END_TR_IT_Pos 4 /**< (SAMHS_HST_DMACONTROL) End of Transfer Interrupt Enable Position */ +#define SAMHS_HST_DMACONTROL_END_TR_IT (_U_(0x1) << SAMHS_HST_DMACONTROL_END_TR_IT_Pos) /**< (SAMHS_HST_DMACONTROL) End of Transfer Interrupt Enable Mask */ +#define SAMHS_HST_DMACONTROL_END_BUFFIT_Pos 5 /**< (SAMHS_HST_DMACONTROL) End of Buffer Interrupt Enable Position */ +#define SAMHS_HST_DMACONTROL_END_BUFFIT (_U_(0x1) << SAMHS_HST_DMACONTROL_END_BUFFIT_Pos) /**< (SAMHS_HST_DMACONTROL) End of Buffer Interrupt Enable Mask */ +#define SAMHS_HST_DMACONTROL_DESC_LD_IT_Pos 6 /**< (SAMHS_HST_DMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define SAMHS_HST_DMACONTROL_DESC_LD_IT (_U_(0x1) << SAMHS_HST_DMACONTROL_DESC_LD_IT_Pos) /**< (SAMHS_HST_DMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define SAMHS_HST_DMACONTROL_BURST_LCK_Pos 7 /**< (SAMHS_HST_DMACONTROL) Burst Lock Enable Position */ +#define SAMHS_HST_DMACONTROL_BURST_LCK (_U_(0x1) << SAMHS_HST_DMACONTROL_BURST_LCK_Pos) /**< (SAMHS_HST_DMACONTROL) Burst Lock Enable Mask */ +#define SAMHS_HST_DMACONTROL_BUFF_LENGTH_Pos 16 /**< (SAMHS_HST_DMACONTROL) Buffer Byte Length (Write-only) Position */ +#define SAMHS_HST_DMACONTROL_BUFF_LENGTH (_U_(0xFFFF) << SAMHS_HST_DMACONTROL_BUFF_LENGTH_Pos) /**< (SAMHS_HST_DMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define SAMHS_HST_DMACONTROL_Msk _U_(0xFFFF00FF) /**< (SAMHS_HST_DMACONTROL) Register Mask */ + + +/* -------- SAMHS_HST_DMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */ + +#define SAMHS_HST_DMASTATUS_OFFSET (0x0C) /**< (SAMHS_HST_DMASTATUS) Host DMA Channel Status Register Offset */ + +#define SAMHS_HST_DMASTATUS_CHANN_ENB_Pos 0 /**< (SAMHS_HST_DMASTATUS) Channel Enable Status Position */ +#define SAMHS_HST_DMASTATUS_CHANN_ENB (_U_(0x1) << SAMHS_HST_DMASTATUS_CHANN_ENB_Pos) /**< (SAMHS_HST_DMASTATUS) Channel Enable Status Mask */ +#define SAMHS_HST_DMASTATUS_CHANN_ACT_Pos 1 /**< (SAMHS_HST_DMASTATUS) Channel Active Status Position */ +#define SAMHS_HST_DMASTATUS_CHANN_ACT (_U_(0x1) << SAMHS_HST_DMASTATUS_CHANN_ACT_Pos) /**< (SAMHS_HST_DMASTATUS) Channel Active Status Mask */ +#define SAMHS_HST_DMASTATUS_END_TR_ST_Pos 4 /**< (SAMHS_HST_DMASTATUS) End of Channel Transfer Status Position */ +#define SAMHS_HST_DMASTATUS_END_TR_ST (_U_(0x1) << SAMHS_HST_DMASTATUS_END_TR_ST_Pos) /**< (SAMHS_HST_DMASTATUS) End of Channel Transfer Status Mask */ +#define SAMHS_HST_DMASTATUS_END_BF_ST_Pos 5 /**< (SAMHS_HST_DMASTATUS) End of Channel Buffer Status Position */ +#define SAMHS_HST_DMASTATUS_END_BF_ST (_U_(0x1) << SAMHS_HST_DMASTATUS_END_BF_ST_Pos) /**< (SAMHS_HST_DMASTATUS) End of Channel Buffer Status Mask */ +#define SAMHS_HST_DMASTATUS_DESC_LDST_Pos 6 /**< (SAMHS_HST_DMASTATUS) Descriptor Loaded Status Position */ +#define SAMHS_HST_DMASTATUS_DESC_LDST (_U_(0x1) << SAMHS_HST_DMASTATUS_DESC_LDST_Pos) /**< (SAMHS_HST_DMASTATUS) Descriptor Loaded Status Mask */ +#define SAMHS_HST_DMASTATUS_BUFF_COUNT_Pos 16 /**< (SAMHS_HST_DMASTATUS) Buffer Byte Count Position */ +#define SAMHS_HST_DMASTATUS_BUFF_COUNT (_U_(0xFFFF) << SAMHS_HST_DMASTATUS_BUFF_COUNT_Pos) /**< (SAMHS_HST_DMASTATUS) Buffer Byte Count Mask */ +#define SAMHS_HST_DMASTATUS_Msk _U_(0xFFFF0073) /**< (SAMHS_HST_DMASTATUS) Register Mask */ + + +/* -------- SAMHS_DEV_CTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ + +#define SAMHS_DEV_CTRL_OFFSET (0x00) /**< (SAMHS_DEV_CTRL) Device General Control Register Offset */ + +#define SAMHS_DEV_CTRL_UADD_Pos 0 /**< (SAMHS_DEV_CTRL) USB Address Position */ +#define SAMHS_DEV_CTRL_UADD (_U_(0x7F) << SAMHS_DEV_CTRL_UADD_Pos) /**< (SAMHS_DEV_CTRL) USB Address Mask */ +#define SAMHS_DEV_CTRL_ADDEN_Pos 7 /**< (SAMHS_DEV_CTRL) Address Enable Position */ +#define SAMHS_DEV_CTRL_ADDEN (_U_(0x1) << SAMHS_DEV_CTRL_ADDEN_Pos) /**< (SAMHS_DEV_CTRL) Address Enable Mask */ +#define SAMHS_DEV_CTRL_DETACH_Pos 8 /**< (SAMHS_DEV_CTRL) Detach Position */ +#define SAMHS_DEV_CTRL_DETACH (_U_(0x1) << SAMHS_DEV_CTRL_DETACH_Pos) /**< (SAMHS_DEV_CTRL) Detach Mask */ +#define SAMHS_DEV_CTRL_RMWKUP_Pos 9 /**< (SAMHS_DEV_CTRL) Remote Wake-Up Position */ +#define SAMHS_DEV_CTRL_RMWKUP (_U_(0x1) << SAMHS_DEV_CTRL_RMWKUP_Pos) /**< (SAMHS_DEV_CTRL) Remote Wake-Up Mask */ +#define SAMHS_DEV_CTRL_SPDCONF_Pos 10 /**< (SAMHS_DEV_CTRL) Mode Configuration Position */ +#define SAMHS_DEV_CTRL_SPDCONF (_U_(0x3) << SAMHS_DEV_CTRL_SPDCONF_Pos) /**< (SAMHS_DEV_CTRL) Mode Configuration Mask */ +#define SAMHS_DEV_CTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (SAMHS_DEV_CTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define SAMHS_DEV_CTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (SAMHS_DEV_CTRL) For a better consumption, if high speed is not needed. */ +#define SAMHS_DEV_CTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (SAMHS_DEV_CTRL) Forced high speed. */ +#define SAMHS_DEV_CTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (SAMHS_DEV_CTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define SAMHS_DEV_CTRL_SPDCONF_NORMAL (SAMHS_DEV_CTRL_SPDCONF_NORMAL_Val << SAMHS_DEV_CTRL_SPDCONF_Pos) /**< (SAMHS_DEV_CTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ +#define SAMHS_DEV_CTRL_SPDCONF_LOW_POWER (SAMHS_DEV_CTRL_SPDCONF_LOW_POWER_Val << SAMHS_DEV_CTRL_SPDCONF_Pos) /**< (SAMHS_DEV_CTRL) For a better consumption, if high speed is not needed. Position */ +#define SAMHS_DEV_CTRL_SPDCONF_HIGH_SPEED (SAMHS_DEV_CTRL_SPDCONF_HIGH_SPEED_Val << SAMHS_DEV_CTRL_SPDCONF_Pos) /**< (SAMHS_DEV_CTRL) Forced high speed. Position */ +#define SAMHS_DEV_CTRL_SPDCONF_FORCED_FS (SAMHS_DEV_CTRL_SPDCONF_FORCED_FS_Val << SAMHS_DEV_CTRL_SPDCONF_Pos) /**< (SAMHS_DEV_CTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position */ +#define SAMHS_DEV_CTRL_LS_Pos 12 /**< (SAMHS_DEV_CTRL) Low-Speed Mode Force Position */ +#define SAMHS_DEV_CTRL_LS (_U_(0x1) << SAMHS_DEV_CTRL_LS_Pos) /**< (SAMHS_DEV_CTRL) Low-Speed Mode Force Mask */ +#define SAMHS_DEV_CTRL_TSTJ_Pos 13 /**< (SAMHS_DEV_CTRL) Test mode J Position */ +#define SAMHS_DEV_CTRL_TSTJ (_U_(0x1) << SAMHS_DEV_CTRL_TSTJ_Pos) /**< (SAMHS_DEV_CTRL) Test mode J Mask */ +#define SAMHS_DEV_CTRL_TSTK_Pos 14 /**< (SAMHS_DEV_CTRL) Test mode K Position */ +#define SAMHS_DEV_CTRL_TSTK (_U_(0x1) << SAMHS_DEV_CTRL_TSTK_Pos) /**< (SAMHS_DEV_CTRL) Test mode K Mask */ +#define SAMHS_DEV_CTRL_TSTPCKT_Pos 15 /**< (SAMHS_DEV_CTRL) Test packet mode Position */ +#define SAMHS_DEV_CTRL_TSTPCKT (_U_(0x1) << SAMHS_DEV_CTRL_TSTPCKT_Pos) /**< (SAMHS_DEV_CTRL) Test packet mode Mask */ +#define SAMHS_DEV_CTRL_OPMODE2_Pos 16 /**< (SAMHS_DEV_CTRL) Specific Operational mode Position */ +#define SAMHS_DEV_CTRL_OPMODE2 (_U_(0x1) << SAMHS_DEV_CTRL_OPMODE2_Pos) /**< (SAMHS_DEV_CTRL) Specific Operational mode Mask */ +#define SAMHS_DEV_CTRL_Msk _U_(0x1FFFF) /**< (SAMHS_DEV_CTRL) Register Mask */ + +#define SAMHS_DEV_CTRL_OPMODE_Pos 16 /**< (SAMHS_DEV_CTRL Position) Specific Operational mode */ +#define SAMHS_DEV_CTRL_OPMODE (_U_(0x1) << SAMHS_DEV_CTRL_OPMODE_Pos) /**< (SAMHS_DEV_CTRL Mask) OPMODE */ + +/* -------- SAMHS_DEV_ISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */ + +#define SAMHS_DEV_ISR_OFFSET (0x04) /**< (SAMHS_DEV_ISR) Device Global Interrupt Status Register Offset */ + +#define SAMHS_DEV_ISR_SUSP_Pos 0 /**< (SAMHS_DEV_ISR) Suspend Interrupt Position */ +#define SAMHS_DEV_ISR_SUSP (_U_(0x1) << SAMHS_DEV_ISR_SUSP_Pos) /**< (SAMHS_DEV_ISR) Suspend Interrupt Mask */ +#define SAMHS_DEV_ISR_MSOF_Pos 1 /**< (SAMHS_DEV_ISR) Micro Start of Frame Interrupt Position */ +#define SAMHS_DEV_ISR_MSOF (_U_(0x1) << SAMHS_DEV_ISR_MSOF_Pos) /**< (SAMHS_DEV_ISR) Micro Start of Frame Interrupt Mask */ +#define SAMHS_DEV_ISR_SOF_Pos 2 /**< (SAMHS_DEV_ISR) Start of Frame Interrupt Position */ +#define SAMHS_DEV_ISR_SOF (_U_(0x1) << SAMHS_DEV_ISR_SOF_Pos) /**< (SAMHS_DEV_ISR) Start of Frame Interrupt Mask */ +#define SAMHS_DEV_ISR_EORST_Pos 3 /**< (SAMHS_DEV_ISR) End of Reset Interrupt Position */ +#define SAMHS_DEV_ISR_EORST (_U_(0x1) << SAMHS_DEV_ISR_EORST_Pos) /**< (SAMHS_DEV_ISR) End of Reset Interrupt Mask */ +#define SAMHS_DEV_ISR_WAKEUP_Pos 4 /**< (SAMHS_DEV_ISR) Wake-Up Interrupt Position */ +#define SAMHS_DEV_ISR_WAKEUP (_U_(0x1) << SAMHS_DEV_ISR_WAKEUP_Pos) /**< (SAMHS_DEV_ISR) Wake-Up Interrupt Mask */ +#define SAMHS_DEV_ISR_EORSM_Pos 5 /**< (SAMHS_DEV_ISR) End of Resume Interrupt Position */ +#define SAMHS_DEV_ISR_EORSM (_U_(0x1) << SAMHS_DEV_ISR_EORSM_Pos) /**< (SAMHS_DEV_ISR) End of Resume Interrupt Mask */ +#define SAMHS_DEV_ISR_UPRSM_Pos 6 /**< (SAMHS_DEV_ISR) Upstream Resume Interrupt Position */ +#define SAMHS_DEV_ISR_UPRSM (_U_(0x1) << SAMHS_DEV_ISR_UPRSM_Pos) /**< (SAMHS_DEV_ISR) Upstream Resume Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_0_Pos 12 /**< (SAMHS_DEV_ISR) Endpoint 0 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_0 (_U_(0x1) << SAMHS_DEV_ISR_PEP_0_Pos) /**< (SAMHS_DEV_ISR) Endpoint 0 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_1_Pos 13 /**< (SAMHS_DEV_ISR) Endpoint 1 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_1 (_U_(0x1) << SAMHS_DEV_ISR_PEP_1_Pos) /**< (SAMHS_DEV_ISR) Endpoint 1 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_2_Pos 14 /**< (SAMHS_DEV_ISR) Endpoint 2 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_2 (_U_(0x1) << SAMHS_DEV_ISR_PEP_2_Pos) /**< (SAMHS_DEV_ISR) Endpoint 2 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_3_Pos 15 /**< (SAMHS_DEV_ISR) Endpoint 3 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_3 (_U_(0x1) << SAMHS_DEV_ISR_PEP_3_Pos) /**< (SAMHS_DEV_ISR) Endpoint 3 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_4_Pos 16 /**< (SAMHS_DEV_ISR) Endpoint 4 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_4 (_U_(0x1) << SAMHS_DEV_ISR_PEP_4_Pos) /**< (SAMHS_DEV_ISR) Endpoint 4 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_5_Pos 17 /**< (SAMHS_DEV_ISR) Endpoint 5 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_5 (_U_(0x1) << SAMHS_DEV_ISR_PEP_5_Pos) /**< (SAMHS_DEV_ISR) Endpoint 5 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_6_Pos 18 /**< (SAMHS_DEV_ISR) Endpoint 6 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_6 (_U_(0x1) << SAMHS_DEV_ISR_PEP_6_Pos) /**< (SAMHS_DEV_ISR) Endpoint 6 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_7_Pos 19 /**< (SAMHS_DEV_ISR) Endpoint 7 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_7 (_U_(0x1) << SAMHS_DEV_ISR_PEP_7_Pos) /**< (SAMHS_DEV_ISR) Endpoint 7 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_8_Pos 20 /**< (SAMHS_DEV_ISR) Endpoint 8 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_8 (_U_(0x1) << SAMHS_DEV_ISR_PEP_8_Pos) /**< (SAMHS_DEV_ISR) Endpoint 8 Interrupt Mask */ +#define SAMHS_DEV_ISR_PEP_9_Pos 21 /**< (SAMHS_DEV_ISR) Endpoint 9 Interrupt Position */ +#define SAMHS_DEV_ISR_PEP_9 (_U_(0x1) << SAMHS_DEV_ISR_PEP_9_Pos) /**< (SAMHS_DEV_ISR) Endpoint 9 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_1_Pos 25 /**< (SAMHS_DEV_ISR) DMA Channel 1 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_1 (_U_(0x1) << SAMHS_DEV_ISR_DMA_1_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 1 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_2_Pos 26 /**< (SAMHS_DEV_ISR) DMA Channel 2 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_2 (_U_(0x1) << SAMHS_DEV_ISR_DMA_2_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 2 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_3_Pos 27 /**< (SAMHS_DEV_ISR) DMA Channel 3 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_3 (_U_(0x1) << SAMHS_DEV_ISR_DMA_3_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 3 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_4_Pos 28 /**< (SAMHS_DEV_ISR) DMA Channel 4 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_4 (_U_(0x1) << SAMHS_DEV_ISR_DMA_4_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 4 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_5_Pos 29 /**< (SAMHS_DEV_ISR) DMA Channel 5 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_5 (_U_(0x1) << SAMHS_DEV_ISR_DMA_5_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 5 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_6_Pos 30 /**< (SAMHS_DEV_ISR) DMA Channel 6 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_6 (_U_(0x1) << SAMHS_DEV_ISR_DMA_6_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 6 Interrupt Mask */ +#define SAMHS_DEV_ISR_DMA_7_Pos 31 /**< (SAMHS_DEV_ISR) DMA Channel 7 Interrupt Position */ +#define SAMHS_DEV_ISR_DMA_7 (_U_(0x1) << SAMHS_DEV_ISR_DMA_7_Pos) /**< (SAMHS_DEV_ISR) DMA Channel 7 Interrupt Mask */ +#define SAMHS_DEV_ISR_Msk _U_(0xFE3FF07F) /**< (SAMHS_DEV_ISR) Register Mask */ + +#define SAMHS_DEV_ISR_PEP__Pos 12 /**< (SAMHS_DEV_ISR Position) Endpoint x Interrupt */ +#define SAMHS_DEV_ISR_PEP_ (_U_(0x3FF) << SAMHS_DEV_ISR_PEP__Pos) /**< (SAMHS_DEV_ISR Mask) PEP_ */ +#define SAMHS_DEV_ISR_DMA__Pos 25 /**< (SAMHS_DEV_ISR Position) DMA Channel 7 Interrupt */ +#define SAMHS_DEV_ISR_DMA_ (_U_(0x7F) << SAMHS_DEV_ISR_DMA__Pos) /**< (SAMHS_DEV_ISR Mask) DMA_ */ + +/* -------- SAMHS_DEV_ICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */ + +#define SAMHS_DEV_ICR_OFFSET (0x08) /**< (SAMHS_DEV_ICR) Device Global Interrupt Clear Register Offset */ + +#define SAMHS_DEV_ICR_SUSPC_Pos 0 /**< (SAMHS_DEV_ICR) Suspend Interrupt Clear Position */ +#define SAMHS_DEV_ICR_SUSPC (_U_(0x1) << SAMHS_DEV_ICR_SUSPC_Pos) /**< (SAMHS_DEV_ICR) Suspend Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_MSOFC_Pos 1 /**< (SAMHS_DEV_ICR) Micro Start of Frame Interrupt Clear Position */ +#define SAMHS_DEV_ICR_MSOFC (_U_(0x1) << SAMHS_DEV_ICR_MSOFC_Pos) /**< (SAMHS_DEV_ICR) Micro Start of Frame Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_SOFC_Pos 2 /**< (SAMHS_DEV_ICR) Start of Frame Interrupt Clear Position */ +#define SAMHS_DEV_ICR_SOFC (_U_(0x1) << SAMHS_DEV_ICR_SOFC_Pos) /**< (SAMHS_DEV_ICR) Start of Frame Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_EORSTC_Pos 3 /**< (SAMHS_DEV_ICR) End of Reset Interrupt Clear Position */ +#define SAMHS_DEV_ICR_EORSTC (_U_(0x1) << SAMHS_DEV_ICR_EORSTC_Pos) /**< (SAMHS_DEV_ICR) End of Reset Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_WAKEUPC_Pos 4 /**< (SAMHS_DEV_ICR) Wake-Up Interrupt Clear Position */ +#define SAMHS_DEV_ICR_WAKEUPC (_U_(0x1) << SAMHS_DEV_ICR_WAKEUPC_Pos) /**< (SAMHS_DEV_ICR) Wake-Up Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_EORSMC_Pos 5 /**< (SAMHS_DEV_ICR) End of Resume Interrupt Clear Position */ +#define SAMHS_DEV_ICR_EORSMC (_U_(0x1) << SAMHS_DEV_ICR_EORSMC_Pos) /**< (SAMHS_DEV_ICR) End of Resume Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_UPRSMC_Pos 6 /**< (SAMHS_DEV_ICR) Upstream Resume Interrupt Clear Position */ +#define SAMHS_DEV_ICR_UPRSMC (_U_(0x1) << SAMHS_DEV_ICR_UPRSMC_Pos) /**< (SAMHS_DEV_ICR) Upstream Resume Interrupt Clear Mask */ +#define SAMHS_DEV_ICR_Msk _U_(0x7F) /**< (SAMHS_DEV_ICR) Register Mask */ + + +/* -------- SAMHS_DEV_IFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */ + +#define SAMHS_DEV_IFR_OFFSET (0x0C) /**< (SAMHS_DEV_IFR) Device Global Interrupt Set Register Offset */ + +#define SAMHS_DEV_IFR_SUSPS_Pos 0 /**< (SAMHS_DEV_IFR) Suspend Interrupt Set Position */ +#define SAMHS_DEV_IFR_SUSPS (_U_(0x1) << SAMHS_DEV_IFR_SUSPS_Pos) /**< (SAMHS_DEV_IFR) Suspend Interrupt Set Mask */ +#define SAMHS_DEV_IFR_MSOFS_Pos 1 /**< (SAMHS_DEV_IFR) Micro Start of Frame Interrupt Set Position */ +#define SAMHS_DEV_IFR_MSOFS (_U_(0x1) << SAMHS_DEV_IFR_MSOFS_Pos) /**< (SAMHS_DEV_IFR) Micro Start of Frame Interrupt Set Mask */ +#define SAMHS_DEV_IFR_SOFS_Pos 2 /**< (SAMHS_DEV_IFR) Start of Frame Interrupt Set Position */ +#define SAMHS_DEV_IFR_SOFS (_U_(0x1) << SAMHS_DEV_IFR_SOFS_Pos) /**< (SAMHS_DEV_IFR) Start of Frame Interrupt Set Mask */ +#define SAMHS_DEV_IFR_EORSTS_Pos 3 /**< (SAMHS_DEV_IFR) End of Reset Interrupt Set Position */ +#define SAMHS_DEV_IFR_EORSTS (_U_(0x1) << SAMHS_DEV_IFR_EORSTS_Pos) /**< (SAMHS_DEV_IFR) End of Reset Interrupt Set Mask */ +#define SAMHS_DEV_IFR_WAKEUPS_Pos 4 /**< (SAMHS_DEV_IFR) Wake-Up Interrupt Set Position */ +#define SAMHS_DEV_IFR_WAKEUPS (_U_(0x1) << SAMHS_DEV_IFR_WAKEUPS_Pos) /**< (SAMHS_DEV_IFR) Wake-Up Interrupt Set Mask */ +#define SAMHS_DEV_IFR_EORSMS_Pos 5 /**< (SAMHS_DEV_IFR) End of Resume Interrupt Set Position */ +#define SAMHS_DEV_IFR_EORSMS (_U_(0x1) << SAMHS_DEV_IFR_EORSMS_Pos) /**< (SAMHS_DEV_IFR) End of Resume Interrupt Set Mask */ +#define SAMHS_DEV_IFR_UPRSMS_Pos 6 /**< (SAMHS_DEV_IFR) Upstream Resume Interrupt Set Position */ +#define SAMHS_DEV_IFR_UPRSMS (_U_(0x1) << SAMHS_DEV_IFR_UPRSMS_Pos) /**< (SAMHS_DEV_IFR) Upstream Resume Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_1_Pos 25 /**< (SAMHS_DEV_IFR) DMA Channel 1 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_1 (_U_(0x1) << SAMHS_DEV_IFR_DMA_1_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 1 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_2_Pos 26 /**< (SAMHS_DEV_IFR) DMA Channel 2 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_2 (_U_(0x1) << SAMHS_DEV_IFR_DMA_2_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 2 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_3_Pos 27 /**< (SAMHS_DEV_IFR) DMA Channel 3 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_3 (_U_(0x1) << SAMHS_DEV_IFR_DMA_3_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 3 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_4_Pos 28 /**< (SAMHS_DEV_IFR) DMA Channel 4 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_4 (_U_(0x1) << SAMHS_DEV_IFR_DMA_4_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 4 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_5_Pos 29 /**< (SAMHS_DEV_IFR) DMA Channel 5 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_5 (_U_(0x1) << SAMHS_DEV_IFR_DMA_5_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 5 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_6_Pos 30 /**< (SAMHS_DEV_IFR) DMA Channel 6 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_6 (_U_(0x1) << SAMHS_DEV_IFR_DMA_6_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 6 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_DMA_7_Pos 31 /**< (SAMHS_DEV_IFR) DMA Channel 7 Interrupt Set Position */ +#define SAMHS_DEV_IFR_DMA_7 (_U_(0x1) << SAMHS_DEV_IFR_DMA_7_Pos) /**< (SAMHS_DEV_IFR) DMA Channel 7 Interrupt Set Mask */ +#define SAMHS_DEV_IFR_Msk _U_(0xFE00007F) /**< (SAMHS_DEV_IFR) Register Mask */ + +#define SAMHS_DEV_IFR_DMA__Pos 25 /**< (SAMHS_DEV_IFR Position) DMA Channel 7 Interrupt Set */ +#define SAMHS_DEV_IFR_DMA_ (_U_(0x7F) << SAMHS_DEV_IFR_DMA__Pos) /**< (SAMHS_DEV_IFR Mask) DMA_ */ + +/* -------- SAMHS_DEV_IMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */ + +#define SAMHS_DEV_IMR_OFFSET (0x10) /**< (SAMHS_DEV_IMR) Device Global Interrupt Mask Register Offset */ + +#define SAMHS_DEV_IMR_SUSPE_Pos 0 /**< (SAMHS_DEV_IMR) Suspend Interrupt Mask Position */ +#define SAMHS_DEV_IMR_SUSPE (_U_(0x1) << SAMHS_DEV_IMR_SUSPE_Pos) /**< (SAMHS_DEV_IMR) Suspend Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_MSOFE_Pos 1 /**< (SAMHS_DEV_IMR) Micro Start of Frame Interrupt Mask Position */ +#define SAMHS_DEV_IMR_MSOFE (_U_(0x1) << SAMHS_DEV_IMR_MSOFE_Pos) /**< (SAMHS_DEV_IMR) Micro Start of Frame Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_SOFE_Pos 2 /**< (SAMHS_DEV_IMR) Start of Frame Interrupt Mask Position */ +#define SAMHS_DEV_IMR_SOFE (_U_(0x1) << SAMHS_DEV_IMR_SOFE_Pos) /**< (SAMHS_DEV_IMR) Start of Frame Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_EORSTE_Pos 3 /**< (SAMHS_DEV_IMR) End of Reset Interrupt Mask Position */ +#define SAMHS_DEV_IMR_EORSTE (_U_(0x1) << SAMHS_DEV_IMR_EORSTE_Pos) /**< (SAMHS_DEV_IMR) End of Reset Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_WAKEUPE_Pos 4 /**< (SAMHS_DEV_IMR) Wake-Up Interrupt Mask Position */ +#define SAMHS_DEV_IMR_WAKEUPE (_U_(0x1) << SAMHS_DEV_IMR_WAKEUPE_Pos) /**< (SAMHS_DEV_IMR) Wake-Up Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_EORSME_Pos 5 /**< (SAMHS_DEV_IMR) End of Resume Interrupt Mask Position */ +#define SAMHS_DEV_IMR_EORSME (_U_(0x1) << SAMHS_DEV_IMR_EORSME_Pos) /**< (SAMHS_DEV_IMR) End of Resume Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_UPRSME_Pos 6 /**< (SAMHS_DEV_IMR) Upstream Resume Interrupt Mask Position */ +#define SAMHS_DEV_IMR_UPRSME (_U_(0x1) << SAMHS_DEV_IMR_UPRSME_Pos) /**< (SAMHS_DEV_IMR) Upstream Resume Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_0_Pos 12 /**< (SAMHS_DEV_IMR) Endpoint 0 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_0 (_U_(0x1) << SAMHS_DEV_IMR_PEP_0_Pos) /**< (SAMHS_DEV_IMR) Endpoint 0 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_1_Pos 13 /**< (SAMHS_DEV_IMR) Endpoint 1 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_1 (_U_(0x1) << SAMHS_DEV_IMR_PEP_1_Pos) /**< (SAMHS_DEV_IMR) Endpoint 1 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_2_Pos 14 /**< (SAMHS_DEV_IMR) Endpoint 2 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_2 (_U_(0x1) << SAMHS_DEV_IMR_PEP_2_Pos) /**< (SAMHS_DEV_IMR) Endpoint 2 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_3_Pos 15 /**< (SAMHS_DEV_IMR) Endpoint 3 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_3 (_U_(0x1) << SAMHS_DEV_IMR_PEP_3_Pos) /**< (SAMHS_DEV_IMR) Endpoint 3 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_4_Pos 16 /**< (SAMHS_DEV_IMR) Endpoint 4 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_4 (_U_(0x1) << SAMHS_DEV_IMR_PEP_4_Pos) /**< (SAMHS_DEV_IMR) Endpoint 4 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_5_Pos 17 /**< (SAMHS_DEV_IMR) Endpoint 5 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_5 (_U_(0x1) << SAMHS_DEV_IMR_PEP_5_Pos) /**< (SAMHS_DEV_IMR) Endpoint 5 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_6_Pos 18 /**< (SAMHS_DEV_IMR) Endpoint 6 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_6 (_U_(0x1) << SAMHS_DEV_IMR_PEP_6_Pos) /**< (SAMHS_DEV_IMR) Endpoint 6 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_7_Pos 19 /**< (SAMHS_DEV_IMR) Endpoint 7 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_7 (_U_(0x1) << SAMHS_DEV_IMR_PEP_7_Pos) /**< (SAMHS_DEV_IMR) Endpoint 7 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_8_Pos 20 /**< (SAMHS_DEV_IMR) Endpoint 8 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_8 (_U_(0x1) << SAMHS_DEV_IMR_PEP_8_Pos) /**< (SAMHS_DEV_IMR) Endpoint 8 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_PEP_9_Pos 21 /**< (SAMHS_DEV_IMR) Endpoint 9 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_PEP_9 (_U_(0x1) << SAMHS_DEV_IMR_PEP_9_Pos) /**< (SAMHS_DEV_IMR) Endpoint 9 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_1_Pos 25 /**< (SAMHS_DEV_IMR) DMA Channel 1 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_1 (_U_(0x1) << SAMHS_DEV_IMR_DMA_1_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 1 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_2_Pos 26 /**< (SAMHS_DEV_IMR) DMA Channel 2 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_2 (_U_(0x1) << SAMHS_DEV_IMR_DMA_2_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 2 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_3_Pos 27 /**< (SAMHS_DEV_IMR) DMA Channel 3 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_3 (_U_(0x1) << SAMHS_DEV_IMR_DMA_3_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 3 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_4_Pos 28 /**< (SAMHS_DEV_IMR) DMA Channel 4 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_4 (_U_(0x1) << SAMHS_DEV_IMR_DMA_4_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 4 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_5_Pos 29 /**< (SAMHS_DEV_IMR) DMA Channel 5 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_5 (_U_(0x1) << SAMHS_DEV_IMR_DMA_5_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 5 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_6_Pos 30 /**< (SAMHS_DEV_IMR) DMA Channel 6 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_6 (_U_(0x1) << SAMHS_DEV_IMR_DMA_6_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 6 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_DMA_7_Pos 31 /**< (SAMHS_DEV_IMR) DMA Channel 7 Interrupt Mask Position */ +#define SAMHS_DEV_IMR_DMA_7 (_U_(0x1) << SAMHS_DEV_IMR_DMA_7_Pos) /**< (SAMHS_DEV_IMR) DMA Channel 7 Interrupt Mask Mask */ +#define SAMHS_DEV_IMR_Msk _U_(0xFE3FF07F) /**< (SAMHS_DEV_IMR) Register Mask */ + +#define SAMHS_DEV_IMR_PEP__Pos 12 /**< (SAMHS_DEV_IMR Position) Endpoint x Interrupt Mask */ +#define SAMHS_DEV_IMR_PEP_ (_U_(0x3FF) << SAMHS_DEV_IMR_PEP__Pos) /**< (SAMHS_DEV_IMR Mask) PEP_ */ +#define SAMHS_DEV_IMR_DMA__Pos 25 /**< (SAMHS_DEV_IMR Position) DMA Channel 7 Interrupt Mask */ +#define SAMHS_DEV_IMR_DMA_ (_U_(0x7F) << SAMHS_DEV_IMR_DMA__Pos) /**< (SAMHS_DEV_IMR Mask) DMA_ */ + +/* -------- SAMHS_DEV_IDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */ + +#define SAMHS_DEV_IDR_OFFSET (0x14) /**< (SAMHS_DEV_IDR) Device Global Interrupt Disable Register Offset */ + +#define SAMHS_DEV_IDR_SUSPEC_Pos 0 /**< (SAMHS_DEV_IDR) Suspend Interrupt Disable Position */ +#define SAMHS_DEV_IDR_SUSPEC (_U_(0x1) << SAMHS_DEV_IDR_SUSPEC_Pos) /**< (SAMHS_DEV_IDR) Suspend Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_MSOFEC_Pos 1 /**< (SAMHS_DEV_IDR) Micro Start of Frame Interrupt Disable Position */ +#define SAMHS_DEV_IDR_MSOFEC (_U_(0x1) << SAMHS_DEV_IDR_MSOFEC_Pos) /**< (SAMHS_DEV_IDR) Micro Start of Frame Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_SOFEC_Pos 2 /**< (SAMHS_DEV_IDR) Start of Frame Interrupt Disable Position */ +#define SAMHS_DEV_IDR_SOFEC (_U_(0x1) << SAMHS_DEV_IDR_SOFEC_Pos) /**< (SAMHS_DEV_IDR) Start of Frame Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_EORSTEC_Pos 3 /**< (SAMHS_DEV_IDR) End of Reset Interrupt Disable Position */ +#define SAMHS_DEV_IDR_EORSTEC (_U_(0x1) << SAMHS_DEV_IDR_EORSTEC_Pos) /**< (SAMHS_DEV_IDR) End of Reset Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_WAKEUPEC_Pos 4 /**< (SAMHS_DEV_IDR) Wake-Up Interrupt Disable Position */ +#define SAMHS_DEV_IDR_WAKEUPEC (_U_(0x1) << SAMHS_DEV_IDR_WAKEUPEC_Pos) /**< (SAMHS_DEV_IDR) Wake-Up Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_EORSMEC_Pos 5 /**< (SAMHS_DEV_IDR) End of Resume Interrupt Disable Position */ +#define SAMHS_DEV_IDR_EORSMEC (_U_(0x1) << SAMHS_DEV_IDR_EORSMEC_Pos) /**< (SAMHS_DEV_IDR) End of Resume Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_UPRSMEC_Pos 6 /**< (SAMHS_DEV_IDR) Upstream Resume Interrupt Disable Position */ +#define SAMHS_DEV_IDR_UPRSMEC (_U_(0x1) << SAMHS_DEV_IDR_UPRSMEC_Pos) /**< (SAMHS_DEV_IDR) Upstream Resume Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_0_Pos 12 /**< (SAMHS_DEV_IDR) Endpoint 0 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_0 (_U_(0x1) << SAMHS_DEV_IDR_PEP_0_Pos) /**< (SAMHS_DEV_IDR) Endpoint 0 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_1_Pos 13 /**< (SAMHS_DEV_IDR) Endpoint 1 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_1 (_U_(0x1) << SAMHS_DEV_IDR_PEP_1_Pos) /**< (SAMHS_DEV_IDR) Endpoint 1 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_2_Pos 14 /**< (SAMHS_DEV_IDR) Endpoint 2 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_2 (_U_(0x1) << SAMHS_DEV_IDR_PEP_2_Pos) /**< (SAMHS_DEV_IDR) Endpoint 2 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_3_Pos 15 /**< (SAMHS_DEV_IDR) Endpoint 3 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_3 (_U_(0x1) << SAMHS_DEV_IDR_PEP_3_Pos) /**< (SAMHS_DEV_IDR) Endpoint 3 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_4_Pos 16 /**< (SAMHS_DEV_IDR) Endpoint 4 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_4 (_U_(0x1) << SAMHS_DEV_IDR_PEP_4_Pos) /**< (SAMHS_DEV_IDR) Endpoint 4 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_5_Pos 17 /**< (SAMHS_DEV_IDR) Endpoint 5 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_5 (_U_(0x1) << SAMHS_DEV_IDR_PEP_5_Pos) /**< (SAMHS_DEV_IDR) Endpoint 5 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_6_Pos 18 /**< (SAMHS_DEV_IDR) Endpoint 6 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_6 (_U_(0x1) << SAMHS_DEV_IDR_PEP_6_Pos) /**< (SAMHS_DEV_IDR) Endpoint 6 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_7_Pos 19 /**< (SAMHS_DEV_IDR) Endpoint 7 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_7 (_U_(0x1) << SAMHS_DEV_IDR_PEP_7_Pos) /**< (SAMHS_DEV_IDR) Endpoint 7 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_8_Pos 20 /**< (SAMHS_DEV_IDR) Endpoint 8 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_8 (_U_(0x1) << SAMHS_DEV_IDR_PEP_8_Pos) /**< (SAMHS_DEV_IDR) Endpoint 8 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_PEP_9_Pos 21 /**< (SAMHS_DEV_IDR) Endpoint 9 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_PEP_9 (_U_(0x1) << SAMHS_DEV_IDR_PEP_9_Pos) /**< (SAMHS_DEV_IDR) Endpoint 9 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_1_Pos 25 /**< (SAMHS_DEV_IDR) DMA Channel 1 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_1 (_U_(0x1) << SAMHS_DEV_IDR_DMA_1_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 1 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_2_Pos 26 /**< (SAMHS_DEV_IDR) DMA Channel 2 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_2 (_U_(0x1) << SAMHS_DEV_IDR_DMA_2_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 2 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_3_Pos 27 /**< (SAMHS_DEV_IDR) DMA Channel 3 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_3 (_U_(0x1) << SAMHS_DEV_IDR_DMA_3_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 3 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_4_Pos 28 /**< (SAMHS_DEV_IDR) DMA Channel 4 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_4 (_U_(0x1) << SAMHS_DEV_IDR_DMA_4_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 4 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_5_Pos 29 /**< (SAMHS_DEV_IDR) DMA Channel 5 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_5 (_U_(0x1) << SAMHS_DEV_IDR_DMA_5_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 5 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_6_Pos 30 /**< (SAMHS_DEV_IDR) DMA Channel 6 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_6 (_U_(0x1) << SAMHS_DEV_IDR_DMA_6_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 6 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_DMA_7_Pos 31 /**< (SAMHS_DEV_IDR) DMA Channel 7 Interrupt Disable Position */ +#define SAMHS_DEV_IDR_DMA_7 (_U_(0x1) << SAMHS_DEV_IDR_DMA_7_Pos) /**< (SAMHS_DEV_IDR) DMA Channel 7 Interrupt Disable Mask */ +#define SAMHS_DEV_IDR_Msk _U_(0xFE3FF07F) /**< (SAMHS_DEV_IDR) Register Mask */ + +#define SAMHS_DEV_IDR_PEP__Pos 12 /**< (SAMHS_DEV_IDR Position) Endpoint x Interrupt Disable */ +#define SAMHS_DEV_IDR_PEP_ (_U_(0x3FF) << SAMHS_DEV_IDR_PEP__Pos) /**< (SAMHS_DEV_IDR Mask) PEP_ */ +#define SAMHS_DEV_IDR_DMA__Pos 25 /**< (SAMHS_DEV_IDR Position) DMA Channel 7 Interrupt Disable */ +#define SAMHS_DEV_IDR_DMA_ (_U_(0x7F) << SAMHS_DEV_IDR_DMA__Pos) /**< (SAMHS_DEV_IDR Mask) DMA_ */ + +/* -------- SAMHS_DEV_IER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */ + +#define SAMHS_DEV_IER_OFFSET (0x18) /**< (SAMHS_DEV_IER) Device Global Interrupt Enable Register Offset */ + +#define SAMHS_DEV_IER_SUSPES_Pos 0 /**< (SAMHS_DEV_IER) Suspend Interrupt Enable Position */ +#define SAMHS_DEV_IER_SUSPES (_U_(0x1) << SAMHS_DEV_IER_SUSPES_Pos) /**< (SAMHS_DEV_IER) Suspend Interrupt Enable Mask */ +#define SAMHS_DEV_IER_MSOFES_Pos 1 /**< (SAMHS_DEV_IER) Micro Start of Frame Interrupt Enable Position */ +#define SAMHS_DEV_IER_MSOFES (_U_(0x1) << SAMHS_DEV_IER_MSOFES_Pos) /**< (SAMHS_DEV_IER) Micro Start of Frame Interrupt Enable Mask */ +#define SAMHS_DEV_IER_SOFES_Pos 2 /**< (SAMHS_DEV_IER) Start of Frame Interrupt Enable Position */ +#define SAMHS_DEV_IER_SOFES (_U_(0x1) << SAMHS_DEV_IER_SOFES_Pos) /**< (SAMHS_DEV_IER) Start of Frame Interrupt Enable Mask */ +#define SAMHS_DEV_IER_EORSTES_Pos 3 /**< (SAMHS_DEV_IER) End of Reset Interrupt Enable Position */ +#define SAMHS_DEV_IER_EORSTES (_U_(0x1) << SAMHS_DEV_IER_EORSTES_Pos) /**< (SAMHS_DEV_IER) End of Reset Interrupt Enable Mask */ +#define SAMHS_DEV_IER_WAKEUPES_Pos 4 /**< (SAMHS_DEV_IER) Wake-Up Interrupt Enable Position */ +#define SAMHS_DEV_IER_WAKEUPES (_U_(0x1) << SAMHS_DEV_IER_WAKEUPES_Pos) /**< (SAMHS_DEV_IER) Wake-Up Interrupt Enable Mask */ +#define SAMHS_DEV_IER_EORSMES_Pos 5 /**< (SAMHS_DEV_IER) End of Resume Interrupt Enable Position */ +#define SAMHS_DEV_IER_EORSMES (_U_(0x1) << SAMHS_DEV_IER_EORSMES_Pos) /**< (SAMHS_DEV_IER) End of Resume Interrupt Enable Mask */ +#define SAMHS_DEV_IER_UPRSMES_Pos 6 /**< (SAMHS_DEV_IER) Upstream Resume Interrupt Enable Position */ +#define SAMHS_DEV_IER_UPRSMES (_U_(0x1) << SAMHS_DEV_IER_UPRSMES_Pos) /**< (SAMHS_DEV_IER) Upstream Resume Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_0_Pos 12 /**< (SAMHS_DEV_IER) Endpoint 0 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_0 (_U_(0x1) << SAMHS_DEV_IER_PEP_0_Pos) /**< (SAMHS_DEV_IER) Endpoint 0 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_1_Pos 13 /**< (SAMHS_DEV_IER) Endpoint 1 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_1 (_U_(0x1) << SAMHS_DEV_IER_PEP_1_Pos) /**< (SAMHS_DEV_IER) Endpoint 1 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_2_Pos 14 /**< (SAMHS_DEV_IER) Endpoint 2 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_2 (_U_(0x1) << SAMHS_DEV_IER_PEP_2_Pos) /**< (SAMHS_DEV_IER) Endpoint 2 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_3_Pos 15 /**< (SAMHS_DEV_IER) Endpoint 3 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_3 (_U_(0x1) << SAMHS_DEV_IER_PEP_3_Pos) /**< (SAMHS_DEV_IER) Endpoint 3 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_4_Pos 16 /**< (SAMHS_DEV_IER) Endpoint 4 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_4 (_U_(0x1) << SAMHS_DEV_IER_PEP_4_Pos) /**< (SAMHS_DEV_IER) Endpoint 4 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_5_Pos 17 /**< (SAMHS_DEV_IER) Endpoint 5 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_5 (_U_(0x1) << SAMHS_DEV_IER_PEP_5_Pos) /**< (SAMHS_DEV_IER) Endpoint 5 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_6_Pos 18 /**< (SAMHS_DEV_IER) Endpoint 6 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_6 (_U_(0x1) << SAMHS_DEV_IER_PEP_6_Pos) /**< (SAMHS_DEV_IER) Endpoint 6 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_7_Pos 19 /**< (SAMHS_DEV_IER) Endpoint 7 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_7 (_U_(0x1) << SAMHS_DEV_IER_PEP_7_Pos) /**< (SAMHS_DEV_IER) Endpoint 7 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_8_Pos 20 /**< (SAMHS_DEV_IER) Endpoint 8 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_8 (_U_(0x1) << SAMHS_DEV_IER_PEP_8_Pos) /**< (SAMHS_DEV_IER) Endpoint 8 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_PEP_9_Pos 21 /**< (SAMHS_DEV_IER) Endpoint 9 Interrupt Enable Position */ +#define SAMHS_DEV_IER_PEP_9 (_U_(0x1) << SAMHS_DEV_IER_PEP_9_Pos) /**< (SAMHS_DEV_IER) Endpoint 9 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_1_Pos 25 /**< (SAMHS_DEV_IER) DMA Channel 1 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_1 (_U_(0x1) << SAMHS_DEV_IER_DMA_1_Pos) /**< (SAMHS_DEV_IER) DMA Channel 1 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_2_Pos 26 /**< (SAMHS_DEV_IER) DMA Channel 2 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_2 (_U_(0x1) << SAMHS_DEV_IER_DMA_2_Pos) /**< (SAMHS_DEV_IER) DMA Channel 2 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_3_Pos 27 /**< (SAMHS_DEV_IER) DMA Channel 3 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_3 (_U_(0x1) << SAMHS_DEV_IER_DMA_3_Pos) /**< (SAMHS_DEV_IER) DMA Channel 3 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_4_Pos 28 /**< (SAMHS_DEV_IER) DMA Channel 4 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_4 (_U_(0x1) << SAMHS_DEV_IER_DMA_4_Pos) /**< (SAMHS_DEV_IER) DMA Channel 4 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_5_Pos 29 /**< (SAMHS_DEV_IER) DMA Channel 5 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_5 (_U_(0x1) << SAMHS_DEV_IER_DMA_5_Pos) /**< (SAMHS_DEV_IER) DMA Channel 5 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_6_Pos 30 /**< (SAMHS_DEV_IER) DMA Channel 6 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_6 (_U_(0x1) << SAMHS_DEV_IER_DMA_6_Pos) /**< (SAMHS_DEV_IER) DMA Channel 6 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_DMA_7_Pos 31 /**< (SAMHS_DEV_IER) DMA Channel 7 Interrupt Enable Position */ +#define SAMHS_DEV_IER_DMA_7 (_U_(0x1) << SAMHS_DEV_IER_DMA_7_Pos) /**< (SAMHS_DEV_IER) DMA Channel 7 Interrupt Enable Mask */ +#define SAMHS_DEV_IER_Msk _U_(0xFE3FF07F) /**< (SAMHS_DEV_IER) Register Mask */ + +#define SAMHS_DEV_IER_PEP__Pos 12 /**< (SAMHS_DEV_IER Position) Endpoint x Interrupt Enable */ +#define SAMHS_DEV_IER_PEP_ (_U_(0x3FF) << SAMHS_DEV_IER_PEP__Pos) /**< (SAMHS_DEV_IER Mask) PEP_ */ +#define SAMHS_DEV_IER_DMA__Pos 25 /**< (SAMHS_DEV_IER Position) DMA Channel 7 Interrupt Enable */ +#define SAMHS_DEV_IER_DMA_ (_U_(0x7F) << SAMHS_DEV_IER_DMA__Pos) /**< (SAMHS_DEV_IER Mask) DMA_ */ + +/* -------- SAMHS_DEV_EPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */ + +#define SAMHS_DEV_EPT_OFFSET (0x1C) /**< (SAMHS_DEV_EPT) Device Endpoint Register Offset */ + +#define SAMHS_DEV_EPT_EPEN0_Pos 0 /**< (SAMHS_DEV_EPT) Endpoint 0 Enable Position */ +#define SAMHS_DEV_EPT_EPEN0 (_U_(0x1) << SAMHS_DEV_EPT_EPEN0_Pos) /**< (SAMHS_DEV_EPT) Endpoint 0 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN1_Pos 1 /**< (SAMHS_DEV_EPT) Endpoint 1 Enable Position */ +#define SAMHS_DEV_EPT_EPEN1 (_U_(0x1) << SAMHS_DEV_EPT_EPEN1_Pos) /**< (SAMHS_DEV_EPT) Endpoint 1 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN2_Pos 2 /**< (SAMHS_DEV_EPT) Endpoint 2 Enable Position */ +#define SAMHS_DEV_EPT_EPEN2 (_U_(0x1) << SAMHS_DEV_EPT_EPEN2_Pos) /**< (SAMHS_DEV_EPT) Endpoint 2 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN3_Pos 3 /**< (SAMHS_DEV_EPT) Endpoint 3 Enable Position */ +#define SAMHS_DEV_EPT_EPEN3 (_U_(0x1) << SAMHS_DEV_EPT_EPEN3_Pos) /**< (SAMHS_DEV_EPT) Endpoint 3 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN4_Pos 4 /**< (SAMHS_DEV_EPT) Endpoint 4 Enable Position */ +#define SAMHS_DEV_EPT_EPEN4 (_U_(0x1) << SAMHS_DEV_EPT_EPEN4_Pos) /**< (SAMHS_DEV_EPT) Endpoint 4 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN5_Pos 5 /**< (SAMHS_DEV_EPT) Endpoint 5 Enable Position */ +#define SAMHS_DEV_EPT_EPEN5 (_U_(0x1) << SAMHS_DEV_EPT_EPEN5_Pos) /**< (SAMHS_DEV_EPT) Endpoint 5 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN6_Pos 6 /**< (SAMHS_DEV_EPT) Endpoint 6 Enable Position */ +#define SAMHS_DEV_EPT_EPEN6 (_U_(0x1) << SAMHS_DEV_EPT_EPEN6_Pos) /**< (SAMHS_DEV_EPT) Endpoint 6 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN7_Pos 7 /**< (SAMHS_DEV_EPT) Endpoint 7 Enable Position */ +#define SAMHS_DEV_EPT_EPEN7 (_U_(0x1) << SAMHS_DEV_EPT_EPEN7_Pos) /**< (SAMHS_DEV_EPT) Endpoint 7 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN8_Pos 8 /**< (SAMHS_DEV_EPT) Endpoint 8 Enable Position */ +#define SAMHS_DEV_EPT_EPEN8 (_U_(0x1) << SAMHS_DEV_EPT_EPEN8_Pos) /**< (SAMHS_DEV_EPT) Endpoint 8 Enable Mask */ +#define SAMHS_DEV_EPT_EPEN9_Pos 9 /**< (SAMHS_DEV_EPT) Endpoint 9 Enable Position */ +#define SAMHS_DEV_EPT_EPEN9 (_U_(0x1) << SAMHS_DEV_EPT_EPEN9_Pos) /**< (SAMHS_DEV_EPT) Endpoint 9 Enable Mask */ +#define SAMHS_DEV_EPT_EPRST0_Pos 16 /**< (SAMHS_DEV_EPT) Endpoint 0 Reset Position */ +#define SAMHS_DEV_EPT_EPRST0 (_U_(0x1) << SAMHS_DEV_EPT_EPRST0_Pos) /**< (SAMHS_DEV_EPT) Endpoint 0 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST1_Pos 17 /**< (SAMHS_DEV_EPT) Endpoint 1 Reset Position */ +#define SAMHS_DEV_EPT_EPRST1 (_U_(0x1) << SAMHS_DEV_EPT_EPRST1_Pos) /**< (SAMHS_DEV_EPT) Endpoint 1 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST2_Pos 18 /**< (SAMHS_DEV_EPT) Endpoint 2 Reset Position */ +#define SAMHS_DEV_EPT_EPRST2 (_U_(0x1) << SAMHS_DEV_EPT_EPRST2_Pos) /**< (SAMHS_DEV_EPT) Endpoint 2 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST3_Pos 19 /**< (SAMHS_DEV_EPT) Endpoint 3 Reset Position */ +#define SAMHS_DEV_EPT_EPRST3 (_U_(0x1) << SAMHS_DEV_EPT_EPRST3_Pos) /**< (SAMHS_DEV_EPT) Endpoint 3 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST4_Pos 20 /**< (SAMHS_DEV_EPT) Endpoint 4 Reset Position */ +#define SAMHS_DEV_EPT_EPRST4 (_U_(0x1) << SAMHS_DEV_EPT_EPRST4_Pos) /**< (SAMHS_DEV_EPT) Endpoint 4 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST5_Pos 21 /**< (SAMHS_DEV_EPT) Endpoint 5 Reset Position */ +#define SAMHS_DEV_EPT_EPRST5 (_U_(0x1) << SAMHS_DEV_EPT_EPRST5_Pos) /**< (SAMHS_DEV_EPT) Endpoint 5 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST6_Pos 22 /**< (SAMHS_DEV_EPT) Endpoint 6 Reset Position */ +#define SAMHS_DEV_EPT_EPRST6 (_U_(0x1) << SAMHS_DEV_EPT_EPRST6_Pos) /**< (SAMHS_DEV_EPT) Endpoint 6 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST7_Pos 23 /**< (SAMHS_DEV_EPT) Endpoint 7 Reset Position */ +#define SAMHS_DEV_EPT_EPRST7 (_U_(0x1) << SAMHS_DEV_EPT_EPRST7_Pos) /**< (SAMHS_DEV_EPT) Endpoint 7 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST8_Pos 24 /**< (SAMHS_DEV_EPT) Endpoint 8 Reset Position */ +#define SAMHS_DEV_EPT_EPRST8 (_U_(0x1) << SAMHS_DEV_EPT_EPRST8_Pos) /**< (SAMHS_DEV_EPT) Endpoint 8 Reset Mask */ +#define SAMHS_DEV_EPT_EPRST9_Pos 25 /**< (SAMHS_DEV_EPT) Endpoint 9 Reset Position */ +#define SAMHS_DEV_EPT_EPRST9 (_U_(0x1) << SAMHS_DEV_EPT_EPRST9_Pos) /**< (SAMHS_DEV_EPT) Endpoint 9 Reset Mask */ +#define SAMHS_DEV_EPT_Msk _U_(0x3FF03FF) /**< (SAMHS_DEV_EPT) Register Mask */ + +#define SAMHS_DEV_EPT_EPEN_Pos 0 /**< (SAMHS_DEV_EPT Position) Endpoint x Enable */ +#define SAMHS_DEV_EPT_EPEN (_U_(0x3FF) << SAMHS_DEV_EPT_EPEN_Pos) /**< (SAMHS_DEV_EPT Mask) EPEN */ +#define SAMHS_DEV_EPT_EPRST_Pos 16 /**< (SAMHS_DEV_EPT Position) Endpoint 9 Reset */ +#define SAMHS_DEV_EPT_EPRST (_U_(0x3FF) << SAMHS_DEV_EPT_EPRST_Pos) /**< (SAMHS_DEV_EPT Mask) EPRST */ + +/* -------- SAMHS_DEV_FNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */ + +#define SAMHS_DEV_FNUM_OFFSET (0x20) /**< (SAMHS_DEV_FNUM) Device Frame Number Register Offset */ + +#define SAMHS_DEV_FNUM_MFNUM_Pos 0 /**< (SAMHS_DEV_FNUM) Micro Frame Number Position */ +#define SAMHS_DEV_FNUM_MFNUM (_U_(0x7) << SAMHS_DEV_FNUM_MFNUM_Pos) /**< (SAMHS_DEV_FNUM) Micro Frame Number Mask */ +#define SAMHS_DEV_FNUM_FNUM_Pos 3 /**< (SAMHS_DEV_FNUM) Frame Number Position */ +#define SAMHS_DEV_FNUM_FNUM (_U_(0x7FF) << SAMHS_DEV_FNUM_FNUM_Pos) /**< (SAMHS_DEV_FNUM) Frame Number Mask */ +#define SAMHS_DEV_FNUM_FNCERR_Pos 15 /**< (SAMHS_DEV_FNUM) Frame Number CRC Error Position */ +#define SAMHS_DEV_FNUM_FNCERR (_U_(0x1) << SAMHS_DEV_FNUM_FNCERR_Pos) /**< (SAMHS_DEV_FNUM) Frame Number CRC Error Mask */ +#define SAMHS_DEV_FNUM_Msk _U_(0xBFFF) /**< (SAMHS_DEV_FNUM) Register Mask */ + + +/* -------- SAMHS_DEV_EPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */ + +#define SAMHS_DEV_EPTCFG_OFFSET (0x100) /**< (SAMHS_DEV_EPTCFG) Device Endpoint Configuration Register Offset */ + +#define SAMHS_DEV_EPTCFG_ALLOC_Pos 1 /**< (SAMHS_DEV_EPTCFG) Endpoint Memory Allocate Position */ +#define SAMHS_DEV_EPTCFG_ALLOC (_U_(0x1) << SAMHS_DEV_EPTCFG_ALLOC_Pos) /**< (SAMHS_DEV_EPTCFG) Endpoint Memory Allocate Mask */ +#define SAMHS_DEV_EPTCFG_EPBK_Pos 2 /**< (SAMHS_DEV_EPTCFG) Endpoint Banks Position */ +#define SAMHS_DEV_EPTCFG_EPBK (_U_(0x3) << SAMHS_DEV_EPTCFG_EPBK_Pos) /**< (SAMHS_DEV_EPTCFG) Endpoint Banks Mask */ +#define SAMHS_DEV_EPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (SAMHS_DEV_EPTCFG) Single-bank endpoint */ +#define SAMHS_DEV_EPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (SAMHS_DEV_EPTCFG) Double-bank endpoint */ +#define SAMHS_DEV_EPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (SAMHS_DEV_EPTCFG) Triple-bank endpoint */ +#define SAMHS_DEV_EPTCFG_EPBK_1_BANK (SAMHS_DEV_EPTCFG_EPBK_1_BANK_Val << SAMHS_DEV_EPTCFG_EPBK_Pos) /**< (SAMHS_DEV_EPTCFG) Single-bank endpoint Position */ +#define SAMHS_DEV_EPTCFG_EPBK_2_BANK (SAMHS_DEV_EPTCFG_EPBK_2_BANK_Val << SAMHS_DEV_EPTCFG_EPBK_Pos) /**< (SAMHS_DEV_EPTCFG) Double-bank endpoint Position */ +#define SAMHS_DEV_EPTCFG_EPBK_3_BANK (SAMHS_DEV_EPTCFG_EPBK_3_BANK_Val << SAMHS_DEV_EPTCFG_EPBK_Pos) /**< (SAMHS_DEV_EPTCFG) Triple-bank endpoint Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_Pos 4 /**< (SAMHS_DEV_EPTCFG) Endpoint Size Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE (_U_(0x7) << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) Endpoint Size Mask */ +#define SAMHS_DEV_EPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (SAMHS_DEV_EPTCFG) 8 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (SAMHS_DEV_EPTCFG) 16 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (SAMHS_DEV_EPTCFG) 32 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (SAMHS_DEV_EPTCFG) 64 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (SAMHS_DEV_EPTCFG) 128 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (SAMHS_DEV_EPTCFG) 256 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (SAMHS_DEV_EPTCFG) 512 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (SAMHS_DEV_EPTCFG) 1024 bytes */ +#define SAMHS_DEV_EPTCFG_EPSIZE_8_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_8_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 8 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_16_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_16_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 16 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_32_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_32_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 32 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_64_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_64_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 64 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_128_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_128_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 128 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_256_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_256_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 256 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_512_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_512_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 512 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPSIZE_1024_BYTE (SAMHS_DEV_EPTCFG_EPSIZE_1024_BYTE_Val << SAMHS_DEV_EPTCFG_EPSIZE_Pos) /**< (SAMHS_DEV_EPTCFG) 1024 bytes Position */ +#define SAMHS_DEV_EPTCFG_EPDIR_Pos 8 /**< (SAMHS_DEV_EPTCFG) Endpoint Direction Position */ +#define SAMHS_DEV_EPTCFG_EPDIR (_U_(0x1) << SAMHS_DEV_EPTCFG_EPDIR_Pos) /**< (SAMHS_DEV_EPTCFG) Endpoint Direction Mask */ +#define SAMHS_DEV_EPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (SAMHS_DEV_EPTCFG) The endpoint direction is OUT. */ +#define SAMHS_DEV_EPTCFG_EPDIR_IN_Val _U_(0x1) /**< (SAMHS_DEV_EPTCFG) The endpoint direction is IN (nor for control endpoints). */ +#define SAMHS_DEV_EPTCFG_EPDIR_OUT (SAMHS_DEV_EPTCFG_EPDIR_OUT_Val << SAMHS_DEV_EPTCFG_EPDIR_Pos) /**< (SAMHS_DEV_EPTCFG) The endpoint direction is OUT. Position */ +#define SAMHS_DEV_EPTCFG_EPDIR_IN (SAMHS_DEV_EPTCFG_EPDIR_IN_Val << SAMHS_DEV_EPTCFG_EPDIR_Pos) /**< (SAMHS_DEV_EPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ +#define SAMHS_DEV_EPTCFG_AUTOSW_Pos 9 /**< (SAMHS_DEV_EPTCFG) Automatic Switch Position */ +#define SAMHS_DEV_EPTCFG_AUTOSW (_U_(0x1) << SAMHS_DEV_EPTCFG_AUTOSW_Pos) /**< (SAMHS_DEV_EPTCFG) Automatic Switch Mask */ +#define SAMHS_DEV_EPTCFG_EPTYPE_Pos 11 /**< (SAMHS_DEV_EPTCFG) Endpoint Type Position */ +#define SAMHS_DEV_EPTCFG_EPTYPE (_U_(0x3) << SAMHS_DEV_EPTCFG_EPTYPE_Pos) /**< (SAMHS_DEV_EPTCFG) Endpoint Type Mask */ +#define SAMHS_DEV_EPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (SAMHS_DEV_EPTCFG) Control */ +#define SAMHS_DEV_EPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (SAMHS_DEV_EPTCFG) Isochronous */ +#define SAMHS_DEV_EPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (SAMHS_DEV_EPTCFG) Bulk */ +#define SAMHS_DEV_EPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (SAMHS_DEV_EPTCFG) Interrupt */ +#define SAMHS_DEV_EPTCFG_EPTYPE_CTRL (SAMHS_DEV_EPTCFG_EPTYPE_CTRL_Val << SAMHS_DEV_EPTCFG_EPTYPE_Pos) /**< (SAMHS_DEV_EPTCFG) Control Position */ +#define SAMHS_DEV_EPTCFG_EPTYPE_ISO (SAMHS_DEV_EPTCFG_EPTYPE_ISO_Val << SAMHS_DEV_EPTCFG_EPTYPE_Pos) /**< (SAMHS_DEV_EPTCFG) Isochronous Position */ +#define SAMHS_DEV_EPTCFG_EPTYPE_BLK (SAMHS_DEV_EPTCFG_EPTYPE_BLK_Val << SAMHS_DEV_EPTCFG_EPTYPE_Pos) /**< (SAMHS_DEV_EPTCFG) Bulk Position */ +#define SAMHS_DEV_EPTCFG_EPTYPE_INTRPT (SAMHS_DEV_EPTCFG_EPTYPE_INTRPT_Val << SAMHS_DEV_EPTCFG_EPTYPE_Pos) /**< (SAMHS_DEV_EPTCFG) Interrupt Position */ +#define SAMHS_DEV_EPTCFG_NBTRANS_Pos 13 /**< (SAMHS_DEV_EPTCFG) Number of transactions per microframe for isochronous endpoint Position */ +#define SAMHS_DEV_EPTCFG_NBTRANS (_U_(0x3) << SAMHS_DEV_EPTCFG_NBTRANS_Pos) /**< (SAMHS_DEV_EPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ +#define SAMHS_DEV_EPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (SAMHS_DEV_EPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define SAMHS_DEV_EPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (SAMHS_DEV_EPTCFG) Default value: one transaction per microframe. */ +#define SAMHS_DEV_EPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (SAMHS_DEV_EPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define SAMHS_DEV_EPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (SAMHS_DEV_EPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +#define SAMHS_DEV_EPTCFG_NBTRANS_0_TRANS (SAMHS_DEV_EPTCFG_NBTRANS_0_TRANS_Val << SAMHS_DEV_EPTCFG_NBTRANS_Pos) /**< (SAMHS_DEV_EPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ +#define SAMHS_DEV_EPTCFG_NBTRANS_1_TRANS (SAMHS_DEV_EPTCFG_NBTRANS_1_TRANS_Val << SAMHS_DEV_EPTCFG_NBTRANS_Pos) /**< (SAMHS_DEV_EPTCFG) Default value: one transaction per microframe. Position */ +#define SAMHS_DEV_EPTCFG_NBTRANS_2_TRANS (SAMHS_DEV_EPTCFG_NBTRANS_2_TRANS_Val << SAMHS_DEV_EPTCFG_NBTRANS_Pos) /**< (SAMHS_DEV_EPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ +#define SAMHS_DEV_EPTCFG_NBTRANS_3_TRANS (SAMHS_DEV_EPTCFG_NBTRANS_3_TRANS_Val << SAMHS_DEV_EPTCFG_NBTRANS_Pos) /**< (SAMHS_DEV_EPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ +#define SAMHS_DEV_EPTCFG_Msk _U_(0x7B7E) /**< (SAMHS_DEV_EPTCFG) Register Mask */ + + +/* -------- SAMHS_DEV_EPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */ + +#define SAMHS_DEV_EPTISR_OFFSET (0x130) /**< (SAMHS_DEV_EPTISR) Device Endpoint Interrupt Status Register Offset */ + +#define SAMHS_DEV_EPTISR_TXINI_Pos 0 /**< (SAMHS_DEV_EPTISR) Transmitted IN Data Interrupt Position */ +#define SAMHS_DEV_EPTISR_TXINI (_U_(0x1) << SAMHS_DEV_EPTISR_TXINI_Pos) /**< (SAMHS_DEV_EPTISR) Transmitted IN Data Interrupt Mask */ +#define SAMHS_DEV_EPTISR_RXOUTI_Pos 1 /**< (SAMHS_DEV_EPTISR) Received OUT Data Interrupt Position */ +#define SAMHS_DEV_EPTISR_RXOUTI (_U_(0x1) << SAMHS_DEV_EPTISR_RXOUTI_Pos) /**< (SAMHS_DEV_EPTISR) Received OUT Data Interrupt Mask */ +#define SAMHS_DEV_EPTISR_OVERFI_Pos 5 /**< (SAMHS_DEV_EPTISR) Overflow Interrupt Position */ +#define SAMHS_DEV_EPTISR_OVERFI (_U_(0x1) << SAMHS_DEV_EPTISR_OVERFI_Pos) /**< (SAMHS_DEV_EPTISR) Overflow Interrupt Mask */ +#define SAMHS_DEV_EPTISR_SHORTPACKET_Pos 7 /**< (SAMHS_DEV_EPTISR) Short Packet Interrupt Position */ +#define SAMHS_DEV_EPTISR_SHORTPACKET (_U_(0x1) << SAMHS_DEV_EPTISR_SHORTPACKET_Pos) /**< (SAMHS_DEV_EPTISR) Short Packet Interrupt Mask */ +#define SAMHS_DEV_EPTISR_DTSEQ_Pos 8 /**< (SAMHS_DEV_EPTISR) Data Toggle Sequence Position */ +#define SAMHS_DEV_EPTISR_DTSEQ (_U_(0x3) << SAMHS_DEV_EPTISR_DTSEQ_Pos) /**< (SAMHS_DEV_EPTISR) Data Toggle Sequence Mask */ +#define SAMHS_DEV_EPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (SAMHS_DEV_EPTISR) Data0 toggle sequence */ +#define SAMHS_DEV_EPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (SAMHS_DEV_EPTISR) Data1 toggle sequence */ +#define SAMHS_DEV_EPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (SAMHS_DEV_EPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define SAMHS_DEV_EPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (SAMHS_DEV_EPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define SAMHS_DEV_EPTISR_DTSEQ_DATA0 (SAMHS_DEV_EPTISR_DTSEQ_DATA0_Val << SAMHS_DEV_EPTISR_DTSEQ_Pos) /**< (SAMHS_DEV_EPTISR) Data0 toggle sequence Position */ +#define SAMHS_DEV_EPTISR_DTSEQ_DATA1 (SAMHS_DEV_EPTISR_DTSEQ_DATA1_Val << SAMHS_DEV_EPTISR_DTSEQ_Pos) /**< (SAMHS_DEV_EPTISR) Data1 toggle sequence Position */ +#define SAMHS_DEV_EPTISR_DTSEQ_DATA2 (SAMHS_DEV_EPTISR_DTSEQ_DATA2_Val << SAMHS_DEV_EPTISR_DTSEQ_Pos) /**< (SAMHS_DEV_EPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define SAMHS_DEV_EPTISR_DTSEQ_MDATA (SAMHS_DEV_EPTISR_DTSEQ_MDATA_Val << SAMHS_DEV_EPTISR_DTSEQ_Pos) /**< (SAMHS_DEV_EPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define SAMHS_DEV_EPTISR_NBUSYBK_Pos 12 /**< (SAMHS_DEV_EPTISR) Number of Busy Banks Position */ +#define SAMHS_DEV_EPTISR_NBUSYBK (_U_(0x3) << SAMHS_DEV_EPTISR_NBUSYBK_Pos) /**< (SAMHS_DEV_EPTISR) Number of Busy Banks Mask */ +#define SAMHS_DEV_EPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (SAMHS_DEV_EPTISR) 0 busy bank (all banks free) */ +#define SAMHS_DEV_EPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (SAMHS_DEV_EPTISR) 1 busy bank */ +#define SAMHS_DEV_EPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (SAMHS_DEV_EPTISR) 2 busy banks */ +#define SAMHS_DEV_EPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (SAMHS_DEV_EPTISR) 3 busy banks */ +#define SAMHS_DEV_EPTISR_NBUSYBK_0_BUSY (SAMHS_DEV_EPTISR_NBUSYBK_0_BUSY_Val << SAMHS_DEV_EPTISR_NBUSYBK_Pos) /**< (SAMHS_DEV_EPTISR) 0 busy bank (all banks free) Position */ +#define SAMHS_DEV_EPTISR_NBUSYBK_1_BUSY (SAMHS_DEV_EPTISR_NBUSYBK_1_BUSY_Val << SAMHS_DEV_EPTISR_NBUSYBK_Pos) /**< (SAMHS_DEV_EPTISR) 1 busy bank Position */ +#define SAMHS_DEV_EPTISR_NBUSYBK_2_BUSY (SAMHS_DEV_EPTISR_NBUSYBK_2_BUSY_Val << SAMHS_DEV_EPTISR_NBUSYBK_Pos) /**< (SAMHS_DEV_EPTISR) 2 busy banks Position */ +#define SAMHS_DEV_EPTISR_NBUSYBK_3_BUSY (SAMHS_DEV_EPTISR_NBUSYBK_3_BUSY_Val << SAMHS_DEV_EPTISR_NBUSYBK_Pos) /**< (SAMHS_DEV_EPTISR) 3 busy banks Position */ +#define SAMHS_DEV_EPTISR_CURRBK_Pos 14 /**< (SAMHS_DEV_EPTISR) Current Bank Position */ +#define SAMHS_DEV_EPTISR_CURRBK (_U_(0x3) << SAMHS_DEV_EPTISR_CURRBK_Pos) /**< (SAMHS_DEV_EPTISR) Current Bank Mask */ +#define SAMHS_DEV_EPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (SAMHS_DEV_EPTISR) Current bank is bank0 */ +#define SAMHS_DEV_EPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (SAMHS_DEV_EPTISR) Current bank is bank1 */ +#define SAMHS_DEV_EPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (SAMHS_DEV_EPTISR) Current bank is bank2 */ +#define SAMHS_DEV_EPTISR_CURRBK_BANK0 (SAMHS_DEV_EPTISR_CURRBK_BANK0_Val << SAMHS_DEV_EPTISR_CURRBK_Pos) /**< (SAMHS_DEV_EPTISR) Current bank is bank0 Position */ +#define SAMHS_DEV_EPTISR_CURRBK_BANK1 (SAMHS_DEV_EPTISR_CURRBK_BANK1_Val << SAMHS_DEV_EPTISR_CURRBK_Pos) /**< (SAMHS_DEV_EPTISR) Current bank is bank1 Position */ +#define SAMHS_DEV_EPTISR_CURRBK_BANK2 (SAMHS_DEV_EPTISR_CURRBK_BANK2_Val << SAMHS_DEV_EPTISR_CURRBK_Pos) /**< (SAMHS_DEV_EPTISR) Current bank is bank2 Position */ +#define SAMHS_DEV_EPTISR_RWALL_Pos 16 /**< (SAMHS_DEV_EPTISR) Read/Write Allowed Position */ +#define SAMHS_DEV_EPTISR_RWALL (_U_(0x1) << SAMHS_DEV_EPTISR_RWALL_Pos) /**< (SAMHS_DEV_EPTISR) Read/Write Allowed Mask */ +#define SAMHS_DEV_EPTISR_CFGOK_Pos 18 /**< (SAMHS_DEV_EPTISR) Configuration OK Status Position */ +#define SAMHS_DEV_EPTISR_CFGOK (_U_(0x1) << SAMHS_DEV_EPTISR_CFGOK_Pos) /**< (SAMHS_DEV_EPTISR) Configuration OK Status Mask */ +#define SAMHS_DEV_EPTISR_BYCT_Pos 20 /**< (SAMHS_DEV_EPTISR) Byte Count Position */ +#define SAMHS_DEV_EPTISR_BYCT (_U_(0x7FF) << SAMHS_DEV_EPTISR_BYCT_Pos) /**< (SAMHS_DEV_EPTISR) Byte Count Mask */ +#define SAMHS_DEV_EPTISR_Msk _U_(0x7FF5F3A3) /**< (SAMHS_DEV_EPTISR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_DEV_EPTISR_CTRL_RXSTPI_Pos 2 /**< (SAMHS_DEV_EPTISR) Received SETUP Interrupt Position */ +#define SAMHS_DEV_EPTISR_CTRL_RXSTPI (_U_(0x1) << SAMHS_DEV_EPTISR_CTRL_RXSTPI_Pos) /**< (SAMHS_DEV_EPTISR) Received SETUP Interrupt Mask */ +#define SAMHS_DEV_EPTISR_CTRL_NAKOUTI_Pos 3 /**< (SAMHS_DEV_EPTISR) NAKed OUT Interrupt Position */ +#define SAMHS_DEV_EPTISR_CTRL_NAKOUTI (_U_(0x1) << SAMHS_DEV_EPTISR_CTRL_NAKOUTI_Pos) /**< (SAMHS_DEV_EPTISR) NAKed OUT Interrupt Mask */ +#define SAMHS_DEV_EPTISR_CTRL_NAKINI_Pos 4 /**< (SAMHS_DEV_EPTISR) NAKed IN Interrupt Position */ +#define SAMHS_DEV_EPTISR_CTRL_NAKINI (_U_(0x1) << SAMHS_DEV_EPTISR_CTRL_NAKINI_Pos) /**< (SAMHS_DEV_EPTISR) NAKed IN Interrupt Mask */ +#define SAMHS_DEV_EPTISR_CTRL_STALLEDI_Pos 6 /**< (SAMHS_DEV_EPTISR) STALLed Interrupt Position */ +#define SAMHS_DEV_EPTISR_CTRL_STALLEDI (_U_(0x1) << SAMHS_DEV_EPTISR_CTRL_STALLEDI_Pos) /**< (SAMHS_DEV_EPTISR) STALLed Interrupt Mask */ +#define SAMHS_DEV_EPTISR_CTRL_CTRLDIR_Pos 17 /**< (SAMHS_DEV_EPTISR) Control Direction Position */ +#define SAMHS_DEV_EPTISR_CTRL_CTRLDIR (_U_(0x1) << SAMHS_DEV_EPTISR_CTRL_CTRLDIR_Pos) /**< (SAMHS_DEV_EPTISR) Control Direction Mask */ +#define SAMHS_DEV_EPTISR_CTRL_Msk _U_(0x2005C) /**< (SAMHS_DEV_EPTISR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_DEV_EPTISR_ISO_UNDERFI_Pos 2 /**< (SAMHS_DEV_EPTISR) Underflow Interrupt Position */ +#define SAMHS_DEV_EPTISR_ISO_UNDERFI (_U_(0x1) << SAMHS_DEV_EPTISR_ISO_UNDERFI_Pos) /**< (SAMHS_DEV_EPTISR) Underflow Interrupt Mask */ +#define SAMHS_DEV_EPTISR_ISO_HBISOINERRI_Pos 3 /**< (SAMHS_DEV_EPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ +#define SAMHS_DEV_EPTISR_ISO_HBISOINERRI (_U_(0x1) << SAMHS_DEV_EPTISR_ISO_HBISOINERRI_Pos) /**< (SAMHS_DEV_EPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ +#define SAMHS_DEV_EPTISR_ISO_HBISOFLUSHI_Pos 4 /**< (SAMHS_DEV_EPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */ +#define SAMHS_DEV_EPTISR_ISO_HBISOFLUSHI (_U_(0x1) << SAMHS_DEV_EPTISR_ISO_HBISOFLUSHI_Pos) /**< (SAMHS_DEV_EPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */ +#define SAMHS_DEV_EPTISR_ISO_CRCERRI_Pos 6 /**< (SAMHS_DEV_EPTISR) CRC Error Interrupt Position */ +#define SAMHS_DEV_EPTISR_ISO_CRCERRI (_U_(0x1) << SAMHS_DEV_EPTISR_ISO_CRCERRI_Pos) /**< (SAMHS_DEV_EPTISR) CRC Error Interrupt Mask */ +#define SAMHS_DEV_EPTISR_ISO_ERRORTRANS_Pos 10 /**< (SAMHS_DEV_EPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */ +#define SAMHS_DEV_EPTISR_ISO_ERRORTRANS (_U_(0x1) << SAMHS_DEV_EPTISR_ISO_ERRORTRANS_Pos) /**< (SAMHS_DEV_EPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */ +#define SAMHS_DEV_EPTISR_ISO_Msk _U_(0x45C) /**< (SAMHS_DEV_EPTISR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_DEV_EPTISR_BLK_RXSTPI_Pos 2 /**< (SAMHS_DEV_EPTISR) Received SETUP Interrupt Position */ +#define SAMHS_DEV_EPTISR_BLK_RXSTPI (_U_(0x1) << SAMHS_DEV_EPTISR_BLK_RXSTPI_Pos) /**< (SAMHS_DEV_EPTISR) Received SETUP Interrupt Mask */ +#define SAMHS_DEV_EPTISR_BLK_NAKOUTI_Pos 3 /**< (SAMHS_DEV_EPTISR) NAKed OUT Interrupt Position */ +#define SAMHS_DEV_EPTISR_BLK_NAKOUTI (_U_(0x1) << SAMHS_DEV_EPTISR_BLK_NAKOUTI_Pos) /**< (SAMHS_DEV_EPTISR) NAKed OUT Interrupt Mask */ +#define SAMHS_DEV_EPTISR_BLK_NAKINI_Pos 4 /**< (SAMHS_DEV_EPTISR) NAKed IN Interrupt Position */ +#define SAMHS_DEV_EPTISR_BLK_NAKINI (_U_(0x1) << SAMHS_DEV_EPTISR_BLK_NAKINI_Pos) /**< (SAMHS_DEV_EPTISR) NAKed IN Interrupt Mask */ +#define SAMHS_DEV_EPTISR_BLK_STALLEDI_Pos 6 /**< (SAMHS_DEV_EPTISR) STALLed Interrupt Position */ +#define SAMHS_DEV_EPTISR_BLK_STALLEDI (_U_(0x1) << SAMHS_DEV_EPTISR_BLK_STALLEDI_Pos) /**< (SAMHS_DEV_EPTISR) STALLed Interrupt Mask */ +#define SAMHS_DEV_EPTISR_BLK_CTRLDIR_Pos 17 /**< (SAMHS_DEV_EPTISR) Control Direction Position */ +#define SAMHS_DEV_EPTISR_BLK_CTRLDIR (_U_(0x1) << SAMHS_DEV_EPTISR_BLK_CTRLDIR_Pos) /**< (SAMHS_DEV_EPTISR) Control Direction Mask */ +#define SAMHS_DEV_EPTISR_BLK_Msk _U_(0x2005C) /**< (SAMHS_DEV_EPTISR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_DEV_EPTISR_INTRPT_RXSTPI_Pos 2 /**< (SAMHS_DEV_EPTISR) Received SETUP Interrupt Position */ +#define SAMHS_DEV_EPTISR_INTRPT_RXSTPI (_U_(0x1) << SAMHS_DEV_EPTISR_INTRPT_RXSTPI_Pos) /**< (SAMHS_DEV_EPTISR) Received SETUP Interrupt Mask */ +#define SAMHS_DEV_EPTISR_INTRPT_NAKOUTI_Pos 3 /**< (SAMHS_DEV_EPTISR) NAKed OUT Interrupt Position */ +#define SAMHS_DEV_EPTISR_INTRPT_NAKOUTI (_U_(0x1) << SAMHS_DEV_EPTISR_INTRPT_NAKOUTI_Pos) /**< (SAMHS_DEV_EPTISR) NAKed OUT Interrupt Mask */ +#define SAMHS_DEV_EPTISR_INTRPT_NAKINI_Pos 4 /**< (SAMHS_DEV_EPTISR) NAKed IN Interrupt Position */ +#define SAMHS_DEV_EPTISR_INTRPT_NAKINI (_U_(0x1) << SAMHS_DEV_EPTISR_INTRPT_NAKINI_Pos) /**< (SAMHS_DEV_EPTISR) NAKed IN Interrupt Mask */ +#define SAMHS_DEV_EPTISR_INTRPT_STALLEDI_Pos 6 /**< (SAMHS_DEV_EPTISR) STALLed Interrupt Position */ +#define SAMHS_DEV_EPTISR_INTRPT_STALLEDI (_U_(0x1) << SAMHS_DEV_EPTISR_INTRPT_STALLEDI_Pos) /**< (SAMHS_DEV_EPTISR) STALLed Interrupt Mask */ +#define SAMHS_DEV_EPTISR_INTRPT_CTRLDIR_Pos 17 /**< (SAMHS_DEV_EPTISR) Control Direction Position */ +#define SAMHS_DEV_EPTISR_INTRPT_CTRLDIR (_U_(0x1) << SAMHS_DEV_EPTISR_INTRPT_CTRLDIR_Pos) /**< (SAMHS_DEV_EPTISR) Control Direction Mask */ +#define SAMHS_DEV_EPTISR_INTRPT_Msk _U_(0x2005C) /**< (SAMHS_DEV_EPTISR_INTRPT) Register Mask */ + + +/* -------- SAMHS_DEV_EPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */ + +#define SAMHS_DEV_EPTICR_OFFSET (0x160) /**< (SAMHS_DEV_EPTICR) Device Endpoint Interrupt Clear Register Offset */ + +#define SAMHS_DEV_EPTICR_TXINIC_Pos 0 /**< (SAMHS_DEV_EPTICR) Transmitted IN Data Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_TXINIC (_U_(0x1) << SAMHS_DEV_EPTICR_TXINIC_Pos) /**< (SAMHS_DEV_EPTICR) Transmitted IN Data Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_RXOUTIC_Pos 1 /**< (SAMHS_DEV_EPTICR) Received OUT Data Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_RXOUTIC (_U_(0x1) << SAMHS_DEV_EPTICR_RXOUTIC_Pos) /**< (SAMHS_DEV_EPTICR) Received OUT Data Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_OVERFIC_Pos 5 /**< (SAMHS_DEV_EPTICR) Overflow Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_OVERFIC (_U_(0x1) << SAMHS_DEV_EPTICR_OVERFIC_Pos) /**< (SAMHS_DEV_EPTICR) Overflow Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_SHORTPACKETC_Pos 7 /**< (SAMHS_DEV_EPTICR) Short Packet Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_SHORTPACKETC (_U_(0x1) << SAMHS_DEV_EPTICR_SHORTPACKETC_Pos) /**< (SAMHS_DEV_EPTICR) Short Packet Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_Msk _U_(0xA3) /**< (SAMHS_DEV_EPTICR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_DEV_EPTICR_CTRL_RXSTPIC_Pos 2 /**< (SAMHS_DEV_EPTICR) Received SETUP Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_CTRL_RXSTPIC (_U_(0x1) << SAMHS_DEV_EPTICR_CTRL_RXSTPIC_Pos) /**< (SAMHS_DEV_EPTICR) Received SETUP Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_CTRL_NAKOUTIC_Pos 3 /**< (SAMHS_DEV_EPTICR) NAKed OUT Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_CTRL_NAKOUTIC (_U_(0x1) << SAMHS_DEV_EPTICR_CTRL_NAKOUTIC_Pos) /**< (SAMHS_DEV_EPTICR) NAKed OUT Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_CTRL_NAKINIC_Pos 4 /**< (SAMHS_DEV_EPTICR) NAKed IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_CTRL_NAKINIC (_U_(0x1) << SAMHS_DEV_EPTICR_CTRL_NAKINIC_Pos) /**< (SAMHS_DEV_EPTICR) NAKed IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_CTRL_STALLEDIC_Pos 6 /**< (SAMHS_DEV_EPTICR) STALLed Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_CTRL_STALLEDIC (_U_(0x1) << SAMHS_DEV_EPTICR_CTRL_STALLEDIC_Pos) /**< (SAMHS_DEV_EPTICR) STALLed Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_CTRL_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTICR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_DEV_EPTICR_ISO_UNDERFIC_Pos 2 /**< (SAMHS_DEV_EPTICR) Underflow Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_ISO_UNDERFIC (_U_(0x1) << SAMHS_DEV_EPTICR_ISO_UNDERFIC_Pos) /**< (SAMHS_DEV_EPTICR) Underflow Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_ISO_HBISOINERRIC_Pos 3 /**< (SAMHS_DEV_EPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_ISO_HBISOINERRIC (_U_(0x1) << SAMHS_DEV_EPTICR_ISO_HBISOINERRIC_Pos) /**< (SAMHS_DEV_EPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_ISO_HBISOFLUSHIC_Pos 4 /**< (SAMHS_DEV_EPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_ISO_HBISOFLUSHIC (_U_(0x1) << SAMHS_DEV_EPTICR_ISO_HBISOFLUSHIC_Pos) /**< (SAMHS_DEV_EPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_ISO_CRCERRIC_Pos 6 /**< (SAMHS_DEV_EPTICR) CRC Error Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_ISO_CRCERRIC (_U_(0x1) << SAMHS_DEV_EPTICR_ISO_CRCERRIC_Pos) /**< (SAMHS_DEV_EPTICR) CRC Error Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_ISO_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTICR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_DEV_EPTICR_BLK_RXSTPIC_Pos 2 /**< (SAMHS_DEV_EPTICR) Received SETUP Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_BLK_RXSTPIC (_U_(0x1) << SAMHS_DEV_EPTICR_BLK_RXSTPIC_Pos) /**< (SAMHS_DEV_EPTICR) Received SETUP Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_BLK_NAKOUTIC_Pos 3 /**< (SAMHS_DEV_EPTICR) NAKed OUT Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_BLK_NAKOUTIC (_U_(0x1) << SAMHS_DEV_EPTICR_BLK_NAKOUTIC_Pos) /**< (SAMHS_DEV_EPTICR) NAKed OUT Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_BLK_NAKINIC_Pos 4 /**< (SAMHS_DEV_EPTICR) NAKed IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_BLK_NAKINIC (_U_(0x1) << SAMHS_DEV_EPTICR_BLK_NAKINIC_Pos) /**< (SAMHS_DEV_EPTICR) NAKed IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_BLK_STALLEDIC_Pos 6 /**< (SAMHS_DEV_EPTICR) STALLed Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_BLK_STALLEDIC (_U_(0x1) << SAMHS_DEV_EPTICR_BLK_STALLEDIC_Pos) /**< (SAMHS_DEV_EPTICR) STALLed Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_BLK_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTICR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_DEV_EPTICR_INTRPT_RXSTPIC_Pos 2 /**< (SAMHS_DEV_EPTICR) Received SETUP Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_INTRPT_RXSTPIC (_U_(0x1) << SAMHS_DEV_EPTICR_INTRPT_RXSTPIC_Pos) /**< (SAMHS_DEV_EPTICR) Received SETUP Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_INTRPT_NAKOUTIC_Pos 3 /**< (SAMHS_DEV_EPTICR) NAKed OUT Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_INTRPT_NAKOUTIC (_U_(0x1) << SAMHS_DEV_EPTICR_INTRPT_NAKOUTIC_Pos) /**< (SAMHS_DEV_EPTICR) NAKed OUT Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_INTRPT_NAKINIC_Pos 4 /**< (SAMHS_DEV_EPTICR) NAKed IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_INTRPT_NAKINIC (_U_(0x1) << SAMHS_DEV_EPTICR_INTRPT_NAKINIC_Pos) /**< (SAMHS_DEV_EPTICR) NAKed IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_INTRPT_STALLEDIC_Pos 6 /**< (SAMHS_DEV_EPTICR) STALLed Interrupt Clear Position */ +#define SAMHS_DEV_EPTICR_INTRPT_STALLEDIC (_U_(0x1) << SAMHS_DEV_EPTICR_INTRPT_STALLEDIC_Pos) /**< (SAMHS_DEV_EPTICR) STALLed Interrupt Clear Mask */ +#define SAMHS_DEV_EPTICR_INTRPT_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTICR_INTRPT) Register Mask */ + + +/* -------- SAMHS_DEV_EPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */ + +#define SAMHS_DEV_EPTIFR_OFFSET (0x190) /**< (SAMHS_DEV_EPTIFR) Device Endpoint Interrupt Set Register Offset */ + +#define SAMHS_DEV_EPTIFR_TXINIS_Pos 0 /**< (SAMHS_DEV_EPTIFR) Transmitted IN Data Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_TXINIS (_U_(0x1) << SAMHS_DEV_EPTIFR_TXINIS_Pos) /**< (SAMHS_DEV_EPTIFR) Transmitted IN Data Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_RXOUTIS_Pos 1 /**< (SAMHS_DEV_EPTIFR) Received OUT Data Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_RXOUTIS (_U_(0x1) << SAMHS_DEV_EPTIFR_RXOUTIS_Pos) /**< (SAMHS_DEV_EPTIFR) Received OUT Data Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_OVERFIS_Pos 5 /**< (SAMHS_DEV_EPTIFR) Overflow Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_OVERFIS (_U_(0x1) << SAMHS_DEV_EPTIFR_OVERFIS_Pos) /**< (SAMHS_DEV_EPTIFR) Overflow Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_SHORTPACKETS_Pos 7 /**< (SAMHS_DEV_EPTIFR) Short Packet Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_SHORTPACKETS (_U_(0x1) << SAMHS_DEV_EPTIFR_SHORTPACKETS_Pos) /**< (SAMHS_DEV_EPTIFR) Short Packet Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_NBUSYBKS_Pos 12 /**< (SAMHS_DEV_EPTIFR) Number of Busy Banks Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_NBUSYBKS (_U_(0x1) << SAMHS_DEV_EPTIFR_NBUSYBKS_Pos) /**< (SAMHS_DEV_EPTIFR) Number of Busy Banks Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_Msk _U_(0x10A3) /**< (SAMHS_DEV_EPTIFR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_DEV_EPTIFR_CTRL_RXSTPIS_Pos 2 /**< (SAMHS_DEV_EPTIFR) Received SETUP Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_CTRL_RXSTPIS (_U_(0x1) << SAMHS_DEV_EPTIFR_CTRL_RXSTPIS_Pos) /**< (SAMHS_DEV_EPTIFR) Received SETUP Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_CTRL_NAKOUTIS_Pos 3 /**< (SAMHS_DEV_EPTIFR) NAKed OUT Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_CTRL_NAKOUTIS (_U_(0x1) << SAMHS_DEV_EPTIFR_CTRL_NAKOUTIS_Pos) /**< (SAMHS_DEV_EPTIFR) NAKed OUT Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_CTRL_NAKINIS_Pos 4 /**< (SAMHS_DEV_EPTIFR) NAKed IN Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_CTRL_NAKINIS (_U_(0x1) << SAMHS_DEV_EPTIFR_CTRL_NAKINIS_Pos) /**< (SAMHS_DEV_EPTIFR) NAKed IN Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_CTRL_STALLEDIS_Pos 6 /**< (SAMHS_DEV_EPTIFR) STALLed Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_CTRL_STALLEDIS (_U_(0x1) << SAMHS_DEV_EPTIFR_CTRL_STALLEDIS_Pos) /**< (SAMHS_DEV_EPTIFR) STALLed Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_CTRL_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTIFR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_DEV_EPTIFR_ISO_UNDERFIS_Pos 2 /**< (SAMHS_DEV_EPTIFR) Underflow Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_ISO_UNDERFIS (_U_(0x1) << SAMHS_DEV_EPTIFR_ISO_UNDERFIS_Pos) /**< (SAMHS_DEV_EPTIFR) Underflow Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_ISO_HBISOINERRIS_Pos 3 /**< (SAMHS_DEV_EPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_ISO_HBISOINERRIS (_U_(0x1) << SAMHS_DEV_EPTIFR_ISO_HBISOINERRIS_Pos) /**< (SAMHS_DEV_EPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_ISO_HBISOFLUSHIS_Pos 4 /**< (SAMHS_DEV_EPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_ISO_HBISOFLUSHIS (_U_(0x1) << SAMHS_DEV_EPTIFR_ISO_HBISOFLUSHIS_Pos) /**< (SAMHS_DEV_EPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_ISO_CRCERRIS_Pos 6 /**< (SAMHS_DEV_EPTIFR) CRC Error Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_ISO_CRCERRIS (_U_(0x1) << SAMHS_DEV_EPTIFR_ISO_CRCERRIS_Pos) /**< (SAMHS_DEV_EPTIFR) CRC Error Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_ISO_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTIFR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_DEV_EPTIFR_BLK_RXSTPIS_Pos 2 /**< (SAMHS_DEV_EPTIFR) Received SETUP Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_BLK_RXSTPIS (_U_(0x1) << SAMHS_DEV_EPTIFR_BLK_RXSTPIS_Pos) /**< (SAMHS_DEV_EPTIFR) Received SETUP Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_BLK_NAKOUTIS_Pos 3 /**< (SAMHS_DEV_EPTIFR) NAKed OUT Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_BLK_NAKOUTIS (_U_(0x1) << SAMHS_DEV_EPTIFR_BLK_NAKOUTIS_Pos) /**< (SAMHS_DEV_EPTIFR) NAKed OUT Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_BLK_NAKINIS_Pos 4 /**< (SAMHS_DEV_EPTIFR) NAKed IN Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_BLK_NAKINIS (_U_(0x1) << SAMHS_DEV_EPTIFR_BLK_NAKINIS_Pos) /**< (SAMHS_DEV_EPTIFR) NAKed IN Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_BLK_STALLEDIS_Pos 6 /**< (SAMHS_DEV_EPTIFR) STALLed Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_BLK_STALLEDIS (_U_(0x1) << SAMHS_DEV_EPTIFR_BLK_STALLEDIS_Pos) /**< (SAMHS_DEV_EPTIFR) STALLed Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_BLK_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTIFR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_DEV_EPTIFR_INTRPT_RXSTPIS_Pos 2 /**< (SAMHS_DEV_EPTIFR) Received SETUP Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_INTRPT_RXSTPIS (_U_(0x1) << SAMHS_DEV_EPTIFR_INTRPT_RXSTPIS_Pos) /**< (SAMHS_DEV_EPTIFR) Received SETUP Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_INTRPT_NAKOUTIS_Pos 3 /**< (SAMHS_DEV_EPTIFR) NAKed OUT Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_INTRPT_NAKOUTIS (_U_(0x1) << SAMHS_DEV_EPTIFR_INTRPT_NAKOUTIS_Pos) /**< (SAMHS_DEV_EPTIFR) NAKed OUT Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_INTRPT_NAKINIS_Pos 4 /**< (SAMHS_DEV_EPTIFR) NAKed IN Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_INTRPT_NAKINIS (_U_(0x1) << SAMHS_DEV_EPTIFR_INTRPT_NAKINIS_Pos) /**< (SAMHS_DEV_EPTIFR) NAKed IN Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_INTRPT_STALLEDIS_Pos 6 /**< (SAMHS_DEV_EPTIFR) STALLed Interrupt Set Position */ +#define SAMHS_DEV_EPTIFR_INTRPT_STALLEDIS (_U_(0x1) << SAMHS_DEV_EPTIFR_INTRPT_STALLEDIS_Pos) /**< (SAMHS_DEV_EPTIFR) STALLed Interrupt Set Mask */ +#define SAMHS_DEV_EPTIFR_INTRPT_Msk _U_(0x5C) /**< (SAMHS_DEV_EPTIFR_INTRPT) Register Mask */ + + +/* -------- SAMHS_DEV_EPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */ + +#define SAMHS_DEV_EPTIMR_OFFSET (0x1C0) /**< (SAMHS_DEV_EPTIMR) Device Endpoint Interrupt Mask Register Offset */ + +#define SAMHS_DEV_EPTIMR_TXINE_Pos 0 /**< (SAMHS_DEV_EPTIMR) Transmitted IN Data Interrupt Position */ +#define SAMHS_DEV_EPTIMR_TXINE (_U_(0x1) << SAMHS_DEV_EPTIMR_TXINE_Pos) /**< (SAMHS_DEV_EPTIMR) Transmitted IN Data Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_RXOUTE_Pos 1 /**< (SAMHS_DEV_EPTIMR) Received OUT Data Interrupt Position */ +#define SAMHS_DEV_EPTIMR_RXOUTE (_U_(0x1) << SAMHS_DEV_EPTIMR_RXOUTE_Pos) /**< (SAMHS_DEV_EPTIMR) Received OUT Data Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_OVERFE_Pos 5 /**< (SAMHS_DEV_EPTIMR) Overflow Interrupt Position */ +#define SAMHS_DEV_EPTIMR_OVERFE (_U_(0x1) << SAMHS_DEV_EPTIMR_OVERFE_Pos) /**< (SAMHS_DEV_EPTIMR) Overflow Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_SHORTPACKETE_Pos 7 /**< (SAMHS_DEV_EPTIMR) Short Packet Interrupt Position */ +#define SAMHS_DEV_EPTIMR_SHORTPACKETE (_U_(0x1) << SAMHS_DEV_EPTIMR_SHORTPACKETE_Pos) /**< (SAMHS_DEV_EPTIMR) Short Packet Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_NBUSYBKE_Pos 12 /**< (SAMHS_DEV_EPTIMR) Number of Busy Banks Interrupt Position */ +#define SAMHS_DEV_EPTIMR_NBUSYBKE (_U_(0x1) << SAMHS_DEV_EPTIMR_NBUSYBKE_Pos) /**< (SAMHS_DEV_EPTIMR) Number of Busy Banks Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_KILLBK_Pos 13 /**< (SAMHS_DEV_EPTIMR) Kill IN Bank Position */ +#define SAMHS_DEV_EPTIMR_KILLBK (_U_(0x1) << SAMHS_DEV_EPTIMR_KILLBK_Pos) /**< (SAMHS_DEV_EPTIMR) Kill IN Bank Mask */ +#define SAMHS_DEV_EPTIMR_FIFOCON_Pos 14 /**< (SAMHS_DEV_EPTIMR) FIFO Control Position */ +#define SAMHS_DEV_EPTIMR_FIFOCON (_U_(0x1) << SAMHS_DEV_EPTIMR_FIFOCON_Pos) /**< (SAMHS_DEV_EPTIMR) FIFO Control Mask */ +#define SAMHS_DEV_EPTIMR_EPDISHDMA_Pos 16 /**< (SAMHS_DEV_EPTIMR) Endpoint Interrupts Disable HDMA Request Position */ +#define SAMHS_DEV_EPTIMR_EPDISHDMA (_U_(0x1) << SAMHS_DEV_EPTIMR_EPDISHDMA_Pos) /**< (SAMHS_DEV_EPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ +#define SAMHS_DEV_EPTIMR_RSTDT_Pos 18 /**< (SAMHS_DEV_EPTIMR) Reset Data Toggle Position */ +#define SAMHS_DEV_EPTIMR_RSTDT (_U_(0x1) << SAMHS_DEV_EPTIMR_RSTDT_Pos) /**< (SAMHS_DEV_EPTIMR) Reset Data Toggle Mask */ +#define SAMHS_DEV_EPTIMR_Msk _U_(0x570A3) /**< (SAMHS_DEV_EPTIMR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_DEV_EPTIMR_CTRL_RXSTPE_Pos 2 /**< (SAMHS_DEV_EPTIMR) Received SETUP Interrupt Position */ +#define SAMHS_DEV_EPTIMR_CTRL_RXSTPE (_U_(0x1) << SAMHS_DEV_EPTIMR_CTRL_RXSTPE_Pos) /**< (SAMHS_DEV_EPTIMR) Received SETUP Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_CTRL_NAKOUTE_Pos 3 /**< (SAMHS_DEV_EPTIMR) NAKed OUT Interrupt Position */ +#define SAMHS_DEV_EPTIMR_CTRL_NAKOUTE (_U_(0x1) << SAMHS_DEV_EPTIMR_CTRL_NAKOUTE_Pos) /**< (SAMHS_DEV_EPTIMR) NAKed OUT Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_CTRL_NAKINE_Pos 4 /**< (SAMHS_DEV_EPTIMR) NAKed IN Interrupt Position */ +#define SAMHS_DEV_EPTIMR_CTRL_NAKINE (_U_(0x1) << SAMHS_DEV_EPTIMR_CTRL_NAKINE_Pos) /**< (SAMHS_DEV_EPTIMR) NAKed IN Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_CTRL_STALLEDE_Pos 6 /**< (SAMHS_DEV_EPTIMR) STALLed Interrupt Position */ +#define SAMHS_DEV_EPTIMR_CTRL_STALLEDE (_U_(0x1) << SAMHS_DEV_EPTIMR_CTRL_STALLEDE_Pos) /**< (SAMHS_DEV_EPTIMR) STALLed Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_CTRL_NYETDIS_Pos 17 /**< (SAMHS_DEV_EPTIMR) NYET Token Disable Position */ +#define SAMHS_DEV_EPTIMR_CTRL_NYETDIS (_U_(0x1) << SAMHS_DEV_EPTIMR_CTRL_NYETDIS_Pos) /**< (SAMHS_DEV_EPTIMR) NYET Token Disable Mask */ +#define SAMHS_DEV_EPTIMR_CTRL_STALLRQ_Pos 19 /**< (SAMHS_DEV_EPTIMR) STALL Request Position */ +#define SAMHS_DEV_EPTIMR_CTRL_STALLRQ (_U_(0x1) << SAMHS_DEV_EPTIMR_CTRL_STALLRQ_Pos) /**< (SAMHS_DEV_EPTIMR) STALL Request Mask */ +#define SAMHS_DEV_EPTIMR_CTRL_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIMR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_DEV_EPTIMR_ISO_UNDERFE_Pos 2 /**< (SAMHS_DEV_EPTIMR) Underflow Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_UNDERFE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_UNDERFE_Pos) /**< (SAMHS_DEV_EPTIMR) Underflow Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_HBISOINERRE_Pos 3 /**< (SAMHS_DEV_EPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_HBISOINERRE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_HBISOINERRE_Pos) /**< (SAMHS_DEV_EPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_HBISOFLUSHE_Pos 4 /**< (SAMHS_DEV_EPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_HBISOFLUSHE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_HBISOFLUSHE_Pos) /**< (SAMHS_DEV_EPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_CRCERRE_Pos 6 /**< (SAMHS_DEV_EPTIMR) CRC Error Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_CRCERRE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_CRCERRE_Pos) /**< (SAMHS_DEV_EPTIMR) CRC Error Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_MDATAE_Pos 8 /**< (SAMHS_DEV_EPTIMR) MData Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_MDATAE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_MDATAE_Pos) /**< (SAMHS_DEV_EPTIMR) MData Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_DATAXE_Pos 9 /**< (SAMHS_DEV_EPTIMR) DataX Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_DATAXE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_DATAXE_Pos) /**< (SAMHS_DEV_EPTIMR) DataX Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_ERRORTRANSE_Pos 10 /**< (SAMHS_DEV_EPTIMR) Transaction Error Interrupt Position */ +#define SAMHS_DEV_EPTIMR_ISO_ERRORTRANSE (_U_(0x1) << SAMHS_DEV_EPTIMR_ISO_ERRORTRANSE_Pos) /**< (SAMHS_DEV_EPTIMR) Transaction Error Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_ISO_Msk _U_(0x75C) /**< (SAMHS_DEV_EPTIMR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_DEV_EPTIMR_BLK_RXSTPE_Pos 2 /**< (SAMHS_DEV_EPTIMR) Received SETUP Interrupt Position */ +#define SAMHS_DEV_EPTIMR_BLK_RXSTPE (_U_(0x1) << SAMHS_DEV_EPTIMR_BLK_RXSTPE_Pos) /**< (SAMHS_DEV_EPTIMR) Received SETUP Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_BLK_NAKOUTE_Pos 3 /**< (SAMHS_DEV_EPTIMR) NAKed OUT Interrupt Position */ +#define SAMHS_DEV_EPTIMR_BLK_NAKOUTE (_U_(0x1) << SAMHS_DEV_EPTIMR_BLK_NAKOUTE_Pos) /**< (SAMHS_DEV_EPTIMR) NAKed OUT Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_BLK_NAKINE_Pos 4 /**< (SAMHS_DEV_EPTIMR) NAKed IN Interrupt Position */ +#define SAMHS_DEV_EPTIMR_BLK_NAKINE (_U_(0x1) << SAMHS_DEV_EPTIMR_BLK_NAKINE_Pos) /**< (SAMHS_DEV_EPTIMR) NAKed IN Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_BLK_STALLEDE_Pos 6 /**< (SAMHS_DEV_EPTIMR) STALLed Interrupt Position */ +#define SAMHS_DEV_EPTIMR_BLK_STALLEDE (_U_(0x1) << SAMHS_DEV_EPTIMR_BLK_STALLEDE_Pos) /**< (SAMHS_DEV_EPTIMR) STALLed Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_BLK_NYETDIS_Pos 17 /**< (SAMHS_DEV_EPTIMR) NYET Token Disable Position */ +#define SAMHS_DEV_EPTIMR_BLK_NYETDIS (_U_(0x1) << SAMHS_DEV_EPTIMR_BLK_NYETDIS_Pos) /**< (SAMHS_DEV_EPTIMR) NYET Token Disable Mask */ +#define SAMHS_DEV_EPTIMR_BLK_STALLRQ_Pos 19 /**< (SAMHS_DEV_EPTIMR) STALL Request Position */ +#define SAMHS_DEV_EPTIMR_BLK_STALLRQ (_U_(0x1) << SAMHS_DEV_EPTIMR_BLK_STALLRQ_Pos) /**< (SAMHS_DEV_EPTIMR) STALL Request Mask */ +#define SAMHS_DEV_EPTIMR_BLK_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIMR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_DEV_EPTIMR_INTRPT_RXSTPE_Pos 2 /**< (SAMHS_DEV_EPTIMR) Received SETUP Interrupt Position */ +#define SAMHS_DEV_EPTIMR_INTRPT_RXSTPE (_U_(0x1) << SAMHS_DEV_EPTIMR_INTRPT_RXSTPE_Pos) /**< (SAMHS_DEV_EPTIMR) Received SETUP Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_INTRPT_NAKOUTE_Pos 3 /**< (SAMHS_DEV_EPTIMR) NAKed OUT Interrupt Position */ +#define SAMHS_DEV_EPTIMR_INTRPT_NAKOUTE (_U_(0x1) << SAMHS_DEV_EPTIMR_INTRPT_NAKOUTE_Pos) /**< (SAMHS_DEV_EPTIMR) NAKed OUT Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_INTRPT_NAKINE_Pos 4 /**< (SAMHS_DEV_EPTIMR) NAKed IN Interrupt Position */ +#define SAMHS_DEV_EPTIMR_INTRPT_NAKINE (_U_(0x1) << SAMHS_DEV_EPTIMR_INTRPT_NAKINE_Pos) /**< (SAMHS_DEV_EPTIMR) NAKed IN Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_INTRPT_STALLEDE_Pos 6 /**< (SAMHS_DEV_EPTIMR) STALLed Interrupt Position */ +#define SAMHS_DEV_EPTIMR_INTRPT_STALLEDE (_U_(0x1) << SAMHS_DEV_EPTIMR_INTRPT_STALLEDE_Pos) /**< (SAMHS_DEV_EPTIMR) STALLed Interrupt Mask */ +#define SAMHS_DEV_EPTIMR_INTRPT_NYETDIS_Pos 17 /**< (SAMHS_DEV_EPTIMR) NYET Token Disable Position */ +#define SAMHS_DEV_EPTIMR_INTRPT_NYETDIS (_U_(0x1) << SAMHS_DEV_EPTIMR_INTRPT_NYETDIS_Pos) /**< (SAMHS_DEV_EPTIMR) NYET Token Disable Mask */ +#define SAMHS_DEV_EPTIMR_INTRPT_STALLRQ_Pos 19 /**< (SAMHS_DEV_EPTIMR) STALL Request Position */ +#define SAMHS_DEV_EPTIMR_INTRPT_STALLRQ (_U_(0x1) << SAMHS_DEV_EPTIMR_INTRPT_STALLRQ_Pos) /**< (SAMHS_DEV_EPTIMR) STALL Request Mask */ +#define SAMHS_DEV_EPTIMR_INTRPT_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIMR_INTRPT) Register Mask */ + + +/* -------- SAMHS_DEV_EPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */ + +#define SAMHS_DEV_EPTIER_OFFSET (0x1F0) /**< (SAMHS_DEV_EPTIER) Device Endpoint Interrupt Enable Register Offset */ + +#define SAMHS_DEV_EPTIER_TXINES_Pos 0 /**< (SAMHS_DEV_EPTIER) Transmitted IN Data Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_TXINES (_U_(0x1) << SAMHS_DEV_EPTIER_TXINES_Pos) /**< (SAMHS_DEV_EPTIER) Transmitted IN Data Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_RXOUTES_Pos 1 /**< (SAMHS_DEV_EPTIER) Received OUT Data Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_RXOUTES (_U_(0x1) << SAMHS_DEV_EPTIER_RXOUTES_Pos) /**< (SAMHS_DEV_EPTIER) Received OUT Data Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_OVERFES_Pos 5 /**< (SAMHS_DEV_EPTIER) Overflow Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_OVERFES (_U_(0x1) << SAMHS_DEV_EPTIER_OVERFES_Pos) /**< (SAMHS_DEV_EPTIER) Overflow Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_SHORTPACKETES_Pos 7 /**< (SAMHS_DEV_EPTIER) Short Packet Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_SHORTPACKETES (_U_(0x1) << SAMHS_DEV_EPTIER_SHORTPACKETES_Pos) /**< (SAMHS_DEV_EPTIER) Short Packet Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_NBUSYBKES_Pos 12 /**< (SAMHS_DEV_EPTIER) Number of Busy Banks Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_NBUSYBKES (_U_(0x1) << SAMHS_DEV_EPTIER_NBUSYBKES_Pos) /**< (SAMHS_DEV_EPTIER) Number of Busy Banks Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_KILLBKS_Pos 13 /**< (SAMHS_DEV_EPTIER) Kill IN Bank Position */ +#define SAMHS_DEV_EPTIER_KILLBKS (_U_(0x1) << SAMHS_DEV_EPTIER_KILLBKS_Pos) /**< (SAMHS_DEV_EPTIER) Kill IN Bank Mask */ +#define SAMHS_DEV_EPTIER_FIFOCONS_Pos 14 /**< (SAMHS_DEV_EPTIER) FIFO Control Position */ +#define SAMHS_DEV_EPTIER_FIFOCONS (_U_(0x1) << SAMHS_DEV_EPTIER_FIFOCONS_Pos) /**< (SAMHS_DEV_EPTIER) FIFO Control Mask */ +#define SAMHS_DEV_EPTIER_EPDISHDMAS_Pos 16 /**< (SAMHS_DEV_EPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ +#define SAMHS_DEV_EPTIER_EPDISHDMAS (_U_(0x1) << SAMHS_DEV_EPTIER_EPDISHDMAS_Pos) /**< (SAMHS_DEV_EPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ +#define SAMHS_DEV_EPTIER_RSTDTS_Pos 18 /**< (SAMHS_DEV_EPTIER) Reset Data Toggle Enable Position */ +#define SAMHS_DEV_EPTIER_RSTDTS (_U_(0x1) << SAMHS_DEV_EPTIER_RSTDTS_Pos) /**< (SAMHS_DEV_EPTIER) Reset Data Toggle Enable Mask */ +#define SAMHS_DEV_EPTIER_Msk _U_(0x570A3) /**< (SAMHS_DEV_EPTIER) Register Mask */ + +/* CTRL mode */ +#define SAMHS_DEV_EPTIER_CTRL_RXSTPES_Pos 2 /**< (SAMHS_DEV_EPTIER) Received SETUP Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_CTRL_RXSTPES (_U_(0x1) << SAMHS_DEV_EPTIER_CTRL_RXSTPES_Pos) /**< (SAMHS_DEV_EPTIER) Received SETUP Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_CTRL_NAKOUTES_Pos 3 /**< (SAMHS_DEV_EPTIER) NAKed OUT Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_CTRL_NAKOUTES (_U_(0x1) << SAMHS_DEV_EPTIER_CTRL_NAKOUTES_Pos) /**< (SAMHS_DEV_EPTIER) NAKed OUT Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_CTRL_NAKINES_Pos 4 /**< (SAMHS_DEV_EPTIER) NAKed IN Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_CTRL_NAKINES (_U_(0x1) << SAMHS_DEV_EPTIER_CTRL_NAKINES_Pos) /**< (SAMHS_DEV_EPTIER) NAKed IN Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_CTRL_STALLEDES_Pos 6 /**< (SAMHS_DEV_EPTIER) STALLed Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_CTRL_STALLEDES (_U_(0x1) << SAMHS_DEV_EPTIER_CTRL_STALLEDES_Pos) /**< (SAMHS_DEV_EPTIER) STALLed Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_CTRL_NYETDISS_Pos 17 /**< (SAMHS_DEV_EPTIER) NYET Token Disable Enable Position */ +#define SAMHS_DEV_EPTIER_CTRL_NYETDISS (_U_(0x1) << SAMHS_DEV_EPTIER_CTRL_NYETDISS_Pos) /**< (SAMHS_DEV_EPTIER) NYET Token Disable Enable Mask */ +#define SAMHS_DEV_EPTIER_CTRL_STALLRQS_Pos 19 /**< (SAMHS_DEV_EPTIER) STALL Request Enable Position */ +#define SAMHS_DEV_EPTIER_CTRL_STALLRQS (_U_(0x1) << SAMHS_DEV_EPTIER_CTRL_STALLRQS_Pos) /**< (SAMHS_DEV_EPTIER) STALL Request Enable Mask */ +#define SAMHS_DEV_EPTIER_CTRL_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIER_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_DEV_EPTIER_ISO_UNDERFES_Pos 2 /**< (SAMHS_DEV_EPTIER) Underflow Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_UNDERFES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_UNDERFES_Pos) /**< (SAMHS_DEV_EPTIER) Underflow Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_HBISOINERRES_Pos 3 /**< (SAMHS_DEV_EPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_HBISOINERRES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_HBISOINERRES_Pos) /**< (SAMHS_DEV_EPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_HBISOFLUSHES_Pos 4 /**< (SAMHS_DEV_EPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_HBISOFLUSHES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_HBISOFLUSHES_Pos) /**< (SAMHS_DEV_EPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_CRCERRES_Pos 6 /**< (SAMHS_DEV_EPTIER) CRC Error Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_CRCERRES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_CRCERRES_Pos) /**< (SAMHS_DEV_EPTIER) CRC Error Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_MDATAES_Pos 8 /**< (SAMHS_DEV_EPTIER) MData Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_MDATAES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_MDATAES_Pos) /**< (SAMHS_DEV_EPTIER) MData Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_DATAXES_Pos 9 /**< (SAMHS_DEV_EPTIER) DataX Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_DATAXES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_DATAXES_Pos) /**< (SAMHS_DEV_EPTIER) DataX Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_ERRORTRANSES_Pos 10 /**< (SAMHS_DEV_EPTIER) Transaction Error Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_ISO_ERRORTRANSES (_U_(0x1) << SAMHS_DEV_EPTIER_ISO_ERRORTRANSES_Pos) /**< (SAMHS_DEV_EPTIER) Transaction Error Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_ISO_Msk _U_(0x75C) /**< (SAMHS_DEV_EPTIER_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_DEV_EPTIER_BLK_RXSTPES_Pos 2 /**< (SAMHS_DEV_EPTIER) Received SETUP Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_BLK_RXSTPES (_U_(0x1) << SAMHS_DEV_EPTIER_BLK_RXSTPES_Pos) /**< (SAMHS_DEV_EPTIER) Received SETUP Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_BLK_NAKOUTES_Pos 3 /**< (SAMHS_DEV_EPTIER) NAKed OUT Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_BLK_NAKOUTES (_U_(0x1) << SAMHS_DEV_EPTIER_BLK_NAKOUTES_Pos) /**< (SAMHS_DEV_EPTIER) NAKed OUT Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_BLK_NAKINES_Pos 4 /**< (SAMHS_DEV_EPTIER) NAKed IN Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_BLK_NAKINES (_U_(0x1) << SAMHS_DEV_EPTIER_BLK_NAKINES_Pos) /**< (SAMHS_DEV_EPTIER) NAKed IN Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_BLK_STALLEDES_Pos 6 /**< (SAMHS_DEV_EPTIER) STALLed Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_BLK_STALLEDES (_U_(0x1) << SAMHS_DEV_EPTIER_BLK_STALLEDES_Pos) /**< (SAMHS_DEV_EPTIER) STALLed Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_BLK_NYETDISS_Pos 17 /**< (SAMHS_DEV_EPTIER) NYET Token Disable Enable Position */ +#define SAMHS_DEV_EPTIER_BLK_NYETDISS (_U_(0x1) << SAMHS_DEV_EPTIER_BLK_NYETDISS_Pos) /**< (SAMHS_DEV_EPTIER) NYET Token Disable Enable Mask */ +#define SAMHS_DEV_EPTIER_BLK_STALLRQS_Pos 19 /**< (SAMHS_DEV_EPTIER) STALL Request Enable Position */ +#define SAMHS_DEV_EPTIER_BLK_STALLRQS (_U_(0x1) << SAMHS_DEV_EPTIER_BLK_STALLRQS_Pos) /**< (SAMHS_DEV_EPTIER) STALL Request Enable Mask */ +#define SAMHS_DEV_EPTIER_BLK_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIER_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_DEV_EPTIER_INTRPT_RXSTPES_Pos 2 /**< (SAMHS_DEV_EPTIER) Received SETUP Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_INTRPT_RXSTPES (_U_(0x1) << SAMHS_DEV_EPTIER_INTRPT_RXSTPES_Pos) /**< (SAMHS_DEV_EPTIER) Received SETUP Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_INTRPT_NAKOUTES_Pos 3 /**< (SAMHS_DEV_EPTIER) NAKed OUT Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_INTRPT_NAKOUTES (_U_(0x1) << SAMHS_DEV_EPTIER_INTRPT_NAKOUTES_Pos) /**< (SAMHS_DEV_EPTIER) NAKed OUT Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_INTRPT_NAKINES_Pos 4 /**< (SAMHS_DEV_EPTIER) NAKed IN Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_INTRPT_NAKINES (_U_(0x1) << SAMHS_DEV_EPTIER_INTRPT_NAKINES_Pos) /**< (SAMHS_DEV_EPTIER) NAKed IN Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_INTRPT_STALLEDES_Pos 6 /**< (SAMHS_DEV_EPTIER) STALLed Interrupt Enable Position */ +#define SAMHS_DEV_EPTIER_INTRPT_STALLEDES (_U_(0x1) << SAMHS_DEV_EPTIER_INTRPT_STALLEDES_Pos) /**< (SAMHS_DEV_EPTIER) STALLed Interrupt Enable Mask */ +#define SAMHS_DEV_EPTIER_INTRPT_NYETDISS_Pos 17 /**< (SAMHS_DEV_EPTIER) NYET Token Disable Enable Position */ +#define SAMHS_DEV_EPTIER_INTRPT_NYETDISS (_U_(0x1) << SAMHS_DEV_EPTIER_INTRPT_NYETDISS_Pos) /**< (SAMHS_DEV_EPTIER) NYET Token Disable Enable Mask */ +#define SAMHS_DEV_EPTIER_INTRPT_STALLRQS_Pos 19 /**< (SAMHS_DEV_EPTIER) STALL Request Enable Position */ +#define SAMHS_DEV_EPTIER_INTRPT_STALLRQS (_U_(0x1) << SAMHS_DEV_EPTIER_INTRPT_STALLRQS_Pos) /**< (SAMHS_DEV_EPTIER) STALL Request Enable Mask */ +#define SAMHS_DEV_EPTIER_INTRPT_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIER_INTRPT) Register Mask */ + + +/* -------- SAMHS_DEV_EPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */ + +#define SAMHS_DEV_EPTIDR_OFFSET (0x220) /**< (SAMHS_DEV_EPTIDR) Device Endpoint Interrupt Disable Register Offset */ + +#define SAMHS_DEV_EPTIDR_TXINEC_Pos 0 /**< (SAMHS_DEV_EPTIDR) Transmitted IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_TXINEC (_U_(0x1) << SAMHS_DEV_EPTIDR_TXINEC_Pos) /**< (SAMHS_DEV_EPTIDR) Transmitted IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_RXOUTEC_Pos 1 /**< (SAMHS_DEV_EPTIDR) Received OUT Data Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_RXOUTEC (_U_(0x1) << SAMHS_DEV_EPTIDR_RXOUTEC_Pos) /**< (SAMHS_DEV_EPTIDR) Received OUT Data Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_OVERFEC_Pos 5 /**< (SAMHS_DEV_EPTIDR) Overflow Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_OVERFEC (_U_(0x1) << SAMHS_DEV_EPTIDR_OVERFEC_Pos) /**< (SAMHS_DEV_EPTIDR) Overflow Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_SHORTPACKETEC_Pos 7 /**< (SAMHS_DEV_EPTIDR) Shortpacket Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_SHORTPACKETEC (_U_(0x1) << SAMHS_DEV_EPTIDR_SHORTPACKETEC_Pos) /**< (SAMHS_DEV_EPTIDR) Shortpacket Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_NBUSYBKEC_Pos 12 /**< (SAMHS_DEV_EPTIDR) Number of Busy Banks Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_NBUSYBKEC (_U_(0x1) << SAMHS_DEV_EPTIDR_NBUSYBKEC_Pos) /**< (SAMHS_DEV_EPTIDR) Number of Busy Banks Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_FIFOCONC_Pos 14 /**< (SAMHS_DEV_EPTIDR) FIFO Control Clear Position */ +#define SAMHS_DEV_EPTIDR_FIFOCONC (_U_(0x1) << SAMHS_DEV_EPTIDR_FIFOCONC_Pos) /**< (SAMHS_DEV_EPTIDR) FIFO Control Clear Mask */ +#define SAMHS_DEV_EPTIDR_EPDISHDMAC_Pos 16 /**< (SAMHS_DEV_EPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ +#define SAMHS_DEV_EPTIDR_EPDISHDMAC (_U_(0x1) << SAMHS_DEV_EPTIDR_EPDISHDMAC_Pos) /**< (SAMHS_DEV_EPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ +#define SAMHS_DEV_EPTIDR_Msk _U_(0x150A3) /**< (SAMHS_DEV_EPTIDR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_DEV_EPTIDR_CTRL_RXSTPEC_Pos 2 /**< (SAMHS_DEV_EPTIDR) Received SETUP Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_CTRL_RXSTPEC (_U_(0x1) << SAMHS_DEV_EPTIDR_CTRL_RXSTPEC_Pos) /**< (SAMHS_DEV_EPTIDR) Received SETUP Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_CTRL_NAKOUTEC_Pos 3 /**< (SAMHS_DEV_EPTIDR) NAKed OUT Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_CTRL_NAKOUTEC (_U_(0x1) << SAMHS_DEV_EPTIDR_CTRL_NAKOUTEC_Pos) /**< (SAMHS_DEV_EPTIDR) NAKed OUT Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_CTRL_NAKINEC_Pos 4 /**< (SAMHS_DEV_EPTIDR) NAKed IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_CTRL_NAKINEC (_U_(0x1) << SAMHS_DEV_EPTIDR_CTRL_NAKINEC_Pos) /**< (SAMHS_DEV_EPTIDR) NAKed IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_CTRL_STALLEDEC_Pos 6 /**< (SAMHS_DEV_EPTIDR) STALLed Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_CTRL_STALLEDEC (_U_(0x1) << SAMHS_DEV_EPTIDR_CTRL_STALLEDEC_Pos) /**< (SAMHS_DEV_EPTIDR) STALLed Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_CTRL_NYETDISC_Pos 17 /**< (SAMHS_DEV_EPTIDR) NYET Token Disable Clear Position */ +#define SAMHS_DEV_EPTIDR_CTRL_NYETDISC (_U_(0x1) << SAMHS_DEV_EPTIDR_CTRL_NYETDISC_Pos) /**< (SAMHS_DEV_EPTIDR) NYET Token Disable Clear Mask */ +#define SAMHS_DEV_EPTIDR_CTRL_STALLRQC_Pos 19 /**< (SAMHS_DEV_EPTIDR) STALL Request Clear Position */ +#define SAMHS_DEV_EPTIDR_CTRL_STALLRQC (_U_(0x1) << SAMHS_DEV_EPTIDR_CTRL_STALLRQC_Pos) /**< (SAMHS_DEV_EPTIDR) STALL Request Clear Mask */ +#define SAMHS_DEV_EPTIDR_CTRL_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIDR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_DEV_EPTIDR_ISO_UNDERFEC_Pos 2 /**< (SAMHS_DEV_EPTIDR) Underflow Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_ISO_UNDERFEC (_U_(0x1) << SAMHS_DEV_EPTIDR_ISO_UNDERFEC_Pos) /**< (SAMHS_DEV_EPTIDR) Underflow Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_ISO_HBISOINERREC_Pos 3 /**< (SAMHS_DEV_EPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_ISO_HBISOINERREC (_U_(0x1) << SAMHS_DEV_EPTIDR_ISO_HBISOINERREC_Pos) /**< (SAMHS_DEV_EPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_ISO_HBISOFLUSHEC_Pos 4 /**< (SAMHS_DEV_EPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_ISO_HBISOFLUSHEC (_U_(0x1) << SAMHS_DEV_EPTIDR_ISO_HBISOFLUSHEC_Pos) /**< (SAMHS_DEV_EPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_ISO_MDATAEC_Pos 8 /**< (SAMHS_DEV_EPTIDR) MData Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_ISO_MDATAEC (_U_(0x1) << SAMHS_DEV_EPTIDR_ISO_MDATAEC_Pos) /**< (SAMHS_DEV_EPTIDR) MData Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_ISO_DATAXEC_Pos 9 /**< (SAMHS_DEV_EPTIDR) DataX Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_ISO_DATAXEC (_U_(0x1) << SAMHS_DEV_EPTIDR_ISO_DATAXEC_Pos) /**< (SAMHS_DEV_EPTIDR) DataX Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_ISO_ERRORTRANSEC_Pos 10 /**< (SAMHS_DEV_EPTIDR) Transaction Error Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_ISO_ERRORTRANSEC (_U_(0x1) << SAMHS_DEV_EPTIDR_ISO_ERRORTRANSEC_Pos) /**< (SAMHS_DEV_EPTIDR) Transaction Error Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_ISO_Msk _U_(0x71C) /**< (SAMHS_DEV_EPTIDR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_DEV_EPTIDR_BLK_RXSTPEC_Pos 2 /**< (SAMHS_DEV_EPTIDR) Received SETUP Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_BLK_RXSTPEC (_U_(0x1) << SAMHS_DEV_EPTIDR_BLK_RXSTPEC_Pos) /**< (SAMHS_DEV_EPTIDR) Received SETUP Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_BLK_NAKOUTEC_Pos 3 /**< (SAMHS_DEV_EPTIDR) NAKed OUT Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_BLK_NAKOUTEC (_U_(0x1) << SAMHS_DEV_EPTIDR_BLK_NAKOUTEC_Pos) /**< (SAMHS_DEV_EPTIDR) NAKed OUT Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_BLK_NAKINEC_Pos 4 /**< (SAMHS_DEV_EPTIDR) NAKed IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_BLK_NAKINEC (_U_(0x1) << SAMHS_DEV_EPTIDR_BLK_NAKINEC_Pos) /**< (SAMHS_DEV_EPTIDR) NAKed IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_BLK_STALLEDEC_Pos 6 /**< (SAMHS_DEV_EPTIDR) STALLed Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_BLK_STALLEDEC (_U_(0x1) << SAMHS_DEV_EPTIDR_BLK_STALLEDEC_Pos) /**< (SAMHS_DEV_EPTIDR) STALLed Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_BLK_NYETDISC_Pos 17 /**< (SAMHS_DEV_EPTIDR) NYET Token Disable Clear Position */ +#define SAMHS_DEV_EPTIDR_BLK_NYETDISC (_U_(0x1) << SAMHS_DEV_EPTIDR_BLK_NYETDISC_Pos) /**< (SAMHS_DEV_EPTIDR) NYET Token Disable Clear Mask */ +#define SAMHS_DEV_EPTIDR_BLK_STALLRQC_Pos 19 /**< (SAMHS_DEV_EPTIDR) STALL Request Clear Position */ +#define SAMHS_DEV_EPTIDR_BLK_STALLRQC (_U_(0x1) << SAMHS_DEV_EPTIDR_BLK_STALLRQC_Pos) /**< (SAMHS_DEV_EPTIDR) STALL Request Clear Mask */ +#define SAMHS_DEV_EPTIDR_BLK_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIDR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_DEV_EPTIDR_INTRPT_RXSTPEC_Pos 2 /**< (SAMHS_DEV_EPTIDR) Received SETUP Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_INTRPT_RXSTPEC (_U_(0x1) << SAMHS_DEV_EPTIDR_INTRPT_RXSTPEC_Pos) /**< (SAMHS_DEV_EPTIDR) Received SETUP Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_INTRPT_NAKOUTEC_Pos 3 /**< (SAMHS_DEV_EPTIDR) NAKed OUT Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_INTRPT_NAKOUTEC (_U_(0x1) << SAMHS_DEV_EPTIDR_INTRPT_NAKOUTEC_Pos) /**< (SAMHS_DEV_EPTIDR) NAKed OUT Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_INTRPT_NAKINEC_Pos 4 /**< (SAMHS_DEV_EPTIDR) NAKed IN Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_INTRPT_NAKINEC (_U_(0x1) << SAMHS_DEV_EPTIDR_INTRPT_NAKINEC_Pos) /**< (SAMHS_DEV_EPTIDR) NAKed IN Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_INTRPT_STALLEDEC_Pos 6 /**< (SAMHS_DEV_EPTIDR) STALLed Interrupt Clear Position */ +#define SAMHS_DEV_EPTIDR_INTRPT_STALLEDEC (_U_(0x1) << SAMHS_DEV_EPTIDR_INTRPT_STALLEDEC_Pos) /**< (SAMHS_DEV_EPTIDR) STALLed Interrupt Clear Mask */ +#define SAMHS_DEV_EPTIDR_INTRPT_NYETDISC_Pos 17 /**< (SAMHS_DEV_EPTIDR) NYET Token Disable Clear Position */ +#define SAMHS_DEV_EPTIDR_INTRPT_NYETDISC (_U_(0x1) << SAMHS_DEV_EPTIDR_INTRPT_NYETDISC_Pos) /**< (SAMHS_DEV_EPTIDR) NYET Token Disable Clear Mask */ +#define SAMHS_DEV_EPTIDR_INTRPT_STALLRQC_Pos 19 /**< (SAMHS_DEV_EPTIDR) STALL Request Clear Position */ +#define SAMHS_DEV_EPTIDR_INTRPT_STALLRQC (_U_(0x1) << SAMHS_DEV_EPTIDR_INTRPT_STALLRQC_Pos) /**< (SAMHS_DEV_EPTIDR) STALL Request Clear Mask */ +#define SAMHS_DEV_EPTIDR_INTRPT_Msk _U_(0xA005C) /**< (SAMHS_DEV_EPTIDR_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_CTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ + +#define SAMHS_HST_CTRL_OFFSET (0x400) /**< (SAMHS_HST_CTRL) Host General Control Register Offset */ + +#define SAMHS_HST_CTRL_SOFE_Pos 8 /**< (SAMHS_HST_CTRL) Start of Frame Generation Enable Position */ +#define SAMHS_HST_CTRL_SOFE (_U_(0x1) << SAMHS_HST_CTRL_SOFE_Pos) /**< (SAMHS_HST_CTRL) Start of Frame Generation Enable Mask */ +#define SAMHS_HST_CTRL_RESET_Pos 9 /**< (SAMHS_HST_CTRL) Send USB Reset Position */ +#define SAMHS_HST_CTRL_RESET (_U_(0x1) << SAMHS_HST_CTRL_RESET_Pos) /**< (SAMHS_HST_CTRL) Send USB Reset Mask */ +#define SAMHS_HST_CTRL_RESUME_Pos 10 /**< (SAMHS_HST_CTRL) Send USB Resume Position */ +#define SAMHS_HST_CTRL_RESUME (_U_(0x1) << SAMHS_HST_CTRL_RESUME_Pos) /**< (SAMHS_HST_CTRL) Send USB Resume Mask */ +#define SAMHS_HST_CTRL_SPDCONF_Pos 12 /**< (SAMHS_HST_CTRL) Mode Configuration Position */ +#define SAMHS_HST_CTRL_SPDCONF (_U_(0x3) << SAMHS_HST_CTRL_SPDCONF_Pos) /**< (SAMHS_HST_CTRL) Mode Configuration Mask */ +#define SAMHS_HST_CTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (SAMHS_HST_CTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define SAMHS_HST_CTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (SAMHS_HST_CTRL) For a better consumption, if high speed is not needed. */ +#define SAMHS_HST_CTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (SAMHS_HST_CTRL) Forced high speed. */ +#define SAMHS_HST_CTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (SAMHS_HST_CTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +#define SAMHS_HST_CTRL_SPDCONF_NORMAL (SAMHS_HST_CTRL_SPDCONF_NORMAL_Val << SAMHS_HST_CTRL_SPDCONF_Pos) /**< (SAMHS_HST_CTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ +#define SAMHS_HST_CTRL_SPDCONF_LOW_POWER (SAMHS_HST_CTRL_SPDCONF_LOW_POWER_Val << SAMHS_HST_CTRL_SPDCONF_Pos) /**< (SAMHS_HST_CTRL) For a better consumption, if high speed is not needed. Position */ +#define SAMHS_HST_CTRL_SPDCONF_HIGH_SPEED (SAMHS_HST_CTRL_SPDCONF_HIGH_SPEED_Val << SAMHS_HST_CTRL_SPDCONF_Pos) /**< (SAMHS_HST_CTRL) Forced high speed. Position */ +#define SAMHS_HST_CTRL_SPDCONF_FORCED_FS (SAMHS_HST_CTRL_SPDCONF_FORCED_FS_Val << SAMHS_HST_CTRL_SPDCONF_Pos) /**< (SAMHS_HST_CTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position */ +#define SAMHS_HST_CTRL_Msk _U_(0x3700) /**< (SAMHS_HST_CTRL) Register Mask */ + + +/* -------- SAMHS_HST_ISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */ + +#define SAMHS_HST_ISR_OFFSET (0x404) /**< (SAMHS_HST_ISR) Host Global Interrupt Status Register Offset */ + +#define SAMHS_HST_ISR_DCONNI_Pos 0 /**< (SAMHS_HST_ISR) Device Connection Interrupt Position */ +#define SAMHS_HST_ISR_DCONNI (_U_(0x1) << SAMHS_HST_ISR_DCONNI_Pos) /**< (SAMHS_HST_ISR) Device Connection Interrupt Mask */ +#define SAMHS_HST_ISR_DDISCI_Pos 1 /**< (SAMHS_HST_ISR) Device Disconnection Interrupt Position */ +#define SAMHS_HST_ISR_DDISCI (_U_(0x1) << SAMHS_HST_ISR_DDISCI_Pos) /**< (SAMHS_HST_ISR) Device Disconnection Interrupt Mask */ +#define SAMHS_HST_ISR_RSTI_Pos 2 /**< (SAMHS_HST_ISR) USB Reset Sent Interrupt Position */ +#define SAMHS_HST_ISR_RSTI (_U_(0x1) << SAMHS_HST_ISR_RSTI_Pos) /**< (SAMHS_HST_ISR) USB Reset Sent Interrupt Mask */ +#define SAMHS_HST_ISR_RSMEDI_Pos 3 /**< (SAMHS_HST_ISR) Downstream Resume Sent Interrupt Position */ +#define SAMHS_HST_ISR_RSMEDI (_U_(0x1) << SAMHS_HST_ISR_RSMEDI_Pos) /**< (SAMHS_HST_ISR) Downstream Resume Sent Interrupt Mask */ +#define SAMHS_HST_ISR_RXRSMI_Pos 4 /**< (SAMHS_HST_ISR) Upstream Resume Received Interrupt Position */ +#define SAMHS_HST_ISR_RXRSMI (_U_(0x1) << SAMHS_HST_ISR_RXRSMI_Pos) /**< (SAMHS_HST_ISR) Upstream Resume Received Interrupt Mask */ +#define SAMHS_HST_ISR_HSOFI_Pos 5 /**< (SAMHS_HST_ISR) Host Start of Frame Interrupt Position */ +#define SAMHS_HST_ISR_HSOFI (_U_(0x1) << SAMHS_HST_ISR_HSOFI_Pos) /**< (SAMHS_HST_ISR) Host Start of Frame Interrupt Mask */ +#define SAMHS_HST_ISR_HWUPI_Pos 6 /**< (SAMHS_HST_ISR) Host Wake-Up Interrupt Position */ +#define SAMHS_HST_ISR_HWUPI (_U_(0x1) << SAMHS_HST_ISR_HWUPI_Pos) /**< (SAMHS_HST_ISR) Host Wake-Up Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_0_Pos 8 /**< (SAMHS_HST_ISR) Pipe 0 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_0 (_U_(0x1) << SAMHS_HST_ISR_PEP_0_Pos) /**< (SAMHS_HST_ISR) Pipe 0 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_1_Pos 9 /**< (SAMHS_HST_ISR) Pipe 1 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_1 (_U_(0x1) << SAMHS_HST_ISR_PEP_1_Pos) /**< (SAMHS_HST_ISR) Pipe 1 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_2_Pos 10 /**< (SAMHS_HST_ISR) Pipe 2 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_2 (_U_(0x1) << SAMHS_HST_ISR_PEP_2_Pos) /**< (SAMHS_HST_ISR) Pipe 2 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_3_Pos 11 /**< (SAMHS_HST_ISR) Pipe 3 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_3 (_U_(0x1) << SAMHS_HST_ISR_PEP_3_Pos) /**< (SAMHS_HST_ISR) Pipe 3 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_4_Pos 12 /**< (SAMHS_HST_ISR) Pipe 4 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_4 (_U_(0x1) << SAMHS_HST_ISR_PEP_4_Pos) /**< (SAMHS_HST_ISR) Pipe 4 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_5_Pos 13 /**< (SAMHS_HST_ISR) Pipe 5 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_5 (_U_(0x1) << SAMHS_HST_ISR_PEP_5_Pos) /**< (SAMHS_HST_ISR) Pipe 5 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_6_Pos 14 /**< (SAMHS_HST_ISR) Pipe 6 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_6 (_U_(0x1) << SAMHS_HST_ISR_PEP_6_Pos) /**< (SAMHS_HST_ISR) Pipe 6 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_7_Pos 15 /**< (SAMHS_HST_ISR) Pipe 7 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_7 (_U_(0x1) << SAMHS_HST_ISR_PEP_7_Pos) /**< (SAMHS_HST_ISR) Pipe 7 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_8_Pos 16 /**< (SAMHS_HST_ISR) Pipe 8 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_8 (_U_(0x1) << SAMHS_HST_ISR_PEP_8_Pos) /**< (SAMHS_HST_ISR) Pipe 8 Interrupt Mask */ +#define SAMHS_HST_ISR_PEP_9_Pos 17 /**< (SAMHS_HST_ISR) Pipe 9 Interrupt Position */ +#define SAMHS_HST_ISR_PEP_9 (_U_(0x1) << SAMHS_HST_ISR_PEP_9_Pos) /**< (SAMHS_HST_ISR) Pipe 9 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_0_Pos 25 /**< (SAMHS_HST_ISR) DMA Channel 0 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_0 (_U_(0x1) << SAMHS_HST_ISR_DMA_0_Pos) /**< (SAMHS_HST_ISR) DMA Channel 0 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_1_Pos 26 /**< (SAMHS_HST_ISR) DMA Channel 1 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_1 (_U_(0x1) << SAMHS_HST_ISR_DMA_1_Pos) /**< (SAMHS_HST_ISR) DMA Channel 1 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_2_Pos 27 /**< (SAMHS_HST_ISR) DMA Channel 2 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_2 (_U_(0x1) << SAMHS_HST_ISR_DMA_2_Pos) /**< (SAMHS_HST_ISR) DMA Channel 2 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_3_Pos 28 /**< (SAMHS_HST_ISR) DMA Channel 3 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_3 (_U_(0x1) << SAMHS_HST_ISR_DMA_3_Pos) /**< (SAMHS_HST_ISR) DMA Channel 3 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_4_Pos 29 /**< (SAMHS_HST_ISR) DMA Channel 4 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_4 (_U_(0x1) << SAMHS_HST_ISR_DMA_4_Pos) /**< (SAMHS_HST_ISR) DMA Channel 4 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_5_Pos 30 /**< (SAMHS_HST_ISR) DMA Channel 5 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_5 (_U_(0x1) << SAMHS_HST_ISR_DMA_5_Pos) /**< (SAMHS_HST_ISR) DMA Channel 5 Interrupt Mask */ +#define SAMHS_HST_ISR_DMA_6_Pos 31 /**< (SAMHS_HST_ISR) DMA Channel 6 Interrupt Position */ +#define SAMHS_HST_ISR_DMA_6 (_U_(0x1) << SAMHS_HST_ISR_DMA_6_Pos) /**< (SAMHS_HST_ISR) DMA Channel 6 Interrupt Mask */ +#define SAMHS_HST_ISR_Msk _U_(0xFE03FF7F) /**< (SAMHS_HST_ISR) Register Mask */ + +#define SAMHS_HST_ISR_PEP__Pos 8 /**< (SAMHS_HST_ISR Position) Pipe x Interrupt */ +#define SAMHS_HST_ISR_PEP_ (_U_(0x3FF) << SAMHS_HST_ISR_PEP__Pos) /**< (SAMHS_HST_ISR Mask) PEP_ */ +#define SAMHS_HST_ISR_DMA__Pos 25 /**< (SAMHS_HST_ISR Position) DMA Channel 6 Interrupt */ +#define SAMHS_HST_ISR_DMA_ (_U_(0x7F) << SAMHS_HST_ISR_DMA__Pos) /**< (SAMHS_HST_ISR Mask) DMA_ */ + +/* -------- SAMHS_HST_ICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */ + +#define SAMHS_HST_ICR_OFFSET (0x408) /**< (SAMHS_HST_ICR) Host Global Interrupt Clear Register Offset */ + +#define SAMHS_HST_ICR_DCONNIC_Pos 0 /**< (SAMHS_HST_ICR) Device Connection Interrupt Clear Position */ +#define SAMHS_HST_ICR_DCONNIC (_U_(0x1) << SAMHS_HST_ICR_DCONNIC_Pos) /**< (SAMHS_HST_ICR) Device Connection Interrupt Clear Mask */ +#define SAMHS_HST_ICR_DDISCIC_Pos 1 /**< (SAMHS_HST_ICR) Device Disconnection Interrupt Clear Position */ +#define SAMHS_HST_ICR_DDISCIC (_U_(0x1) << SAMHS_HST_ICR_DDISCIC_Pos) /**< (SAMHS_HST_ICR) Device Disconnection Interrupt Clear Mask */ +#define SAMHS_HST_ICR_RSTIC_Pos 2 /**< (SAMHS_HST_ICR) USB Reset Sent Interrupt Clear Position */ +#define SAMHS_HST_ICR_RSTIC (_U_(0x1) << SAMHS_HST_ICR_RSTIC_Pos) /**< (SAMHS_HST_ICR) USB Reset Sent Interrupt Clear Mask */ +#define SAMHS_HST_ICR_RSMEDIC_Pos 3 /**< (SAMHS_HST_ICR) Downstream Resume Sent Interrupt Clear Position */ +#define SAMHS_HST_ICR_RSMEDIC (_U_(0x1) << SAMHS_HST_ICR_RSMEDIC_Pos) /**< (SAMHS_HST_ICR) Downstream Resume Sent Interrupt Clear Mask */ +#define SAMHS_HST_ICR_RXRSMIC_Pos 4 /**< (SAMHS_HST_ICR) Upstream Resume Received Interrupt Clear Position */ +#define SAMHS_HST_ICR_RXRSMIC (_U_(0x1) << SAMHS_HST_ICR_RXRSMIC_Pos) /**< (SAMHS_HST_ICR) Upstream Resume Received Interrupt Clear Mask */ +#define SAMHS_HST_ICR_HSOFIC_Pos 5 /**< (SAMHS_HST_ICR) Host Start of Frame Interrupt Clear Position */ +#define SAMHS_HST_ICR_HSOFIC (_U_(0x1) << SAMHS_HST_ICR_HSOFIC_Pos) /**< (SAMHS_HST_ICR) Host Start of Frame Interrupt Clear Mask */ +#define SAMHS_HST_ICR_HWUPIC_Pos 6 /**< (SAMHS_HST_ICR) Host Wake-Up Interrupt Clear Position */ +#define SAMHS_HST_ICR_HWUPIC (_U_(0x1) << SAMHS_HST_ICR_HWUPIC_Pos) /**< (SAMHS_HST_ICR) Host Wake-Up Interrupt Clear Mask */ +#define SAMHS_HST_ICR_Msk _U_(0x7F) /**< (SAMHS_HST_ICR) Register Mask */ + + +/* -------- SAMHS_HST_IFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */ + +#define SAMHS_HST_IFR_OFFSET (0x40C) /**< (SAMHS_HST_IFR) Host Global Interrupt Set Register Offset */ + +#define SAMHS_HST_IFR_DCONNIS_Pos 0 /**< (SAMHS_HST_IFR) Device Connection Interrupt Set Position */ +#define SAMHS_HST_IFR_DCONNIS (_U_(0x1) << SAMHS_HST_IFR_DCONNIS_Pos) /**< (SAMHS_HST_IFR) Device Connection Interrupt Set Mask */ +#define SAMHS_HST_IFR_DDISCIS_Pos 1 /**< (SAMHS_HST_IFR) Device Disconnection Interrupt Set Position */ +#define SAMHS_HST_IFR_DDISCIS (_U_(0x1) << SAMHS_HST_IFR_DDISCIS_Pos) /**< (SAMHS_HST_IFR) Device Disconnection Interrupt Set Mask */ +#define SAMHS_HST_IFR_RSTIS_Pos 2 /**< (SAMHS_HST_IFR) USB Reset Sent Interrupt Set Position */ +#define SAMHS_HST_IFR_RSTIS (_U_(0x1) << SAMHS_HST_IFR_RSTIS_Pos) /**< (SAMHS_HST_IFR) USB Reset Sent Interrupt Set Mask */ +#define SAMHS_HST_IFR_RSMEDIS_Pos 3 /**< (SAMHS_HST_IFR) Downstream Resume Sent Interrupt Set Position */ +#define SAMHS_HST_IFR_RSMEDIS (_U_(0x1) << SAMHS_HST_IFR_RSMEDIS_Pos) /**< (SAMHS_HST_IFR) Downstream Resume Sent Interrupt Set Mask */ +#define SAMHS_HST_IFR_RXRSMIS_Pos 4 /**< (SAMHS_HST_IFR) Upstream Resume Received Interrupt Set Position */ +#define SAMHS_HST_IFR_RXRSMIS (_U_(0x1) << SAMHS_HST_IFR_RXRSMIS_Pos) /**< (SAMHS_HST_IFR) Upstream Resume Received Interrupt Set Mask */ +#define SAMHS_HST_IFR_HSOFIS_Pos 5 /**< (SAMHS_HST_IFR) Host Start of Frame Interrupt Set Position */ +#define SAMHS_HST_IFR_HSOFIS (_U_(0x1) << SAMHS_HST_IFR_HSOFIS_Pos) /**< (SAMHS_HST_IFR) Host Start of Frame Interrupt Set Mask */ +#define SAMHS_HST_IFR_HWUPIS_Pos 6 /**< (SAMHS_HST_IFR) Host Wake-Up Interrupt Set Position */ +#define SAMHS_HST_IFR_HWUPIS (_U_(0x1) << SAMHS_HST_IFR_HWUPIS_Pos) /**< (SAMHS_HST_IFR) Host Wake-Up Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_0_Pos 25 /**< (SAMHS_HST_IFR) DMA Channel 0 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_0 (_U_(0x1) << SAMHS_HST_IFR_DMA_0_Pos) /**< (SAMHS_HST_IFR) DMA Channel 0 Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_1_Pos 26 /**< (SAMHS_HST_IFR) DMA Channel 1 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_1 (_U_(0x1) << SAMHS_HST_IFR_DMA_1_Pos) /**< (SAMHS_HST_IFR) DMA Channel 1 Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_2_Pos 27 /**< (SAMHS_HST_IFR) DMA Channel 2 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_2 (_U_(0x1) << SAMHS_HST_IFR_DMA_2_Pos) /**< (SAMHS_HST_IFR) DMA Channel 2 Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_3_Pos 28 /**< (SAMHS_HST_IFR) DMA Channel 3 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_3 (_U_(0x1) << SAMHS_HST_IFR_DMA_3_Pos) /**< (SAMHS_HST_IFR) DMA Channel 3 Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_4_Pos 29 /**< (SAMHS_HST_IFR) DMA Channel 4 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_4 (_U_(0x1) << SAMHS_HST_IFR_DMA_4_Pos) /**< (SAMHS_HST_IFR) DMA Channel 4 Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_5_Pos 30 /**< (SAMHS_HST_IFR) DMA Channel 5 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_5 (_U_(0x1) << SAMHS_HST_IFR_DMA_5_Pos) /**< (SAMHS_HST_IFR) DMA Channel 5 Interrupt Set Mask */ +#define SAMHS_HST_IFR_DMA_6_Pos 31 /**< (SAMHS_HST_IFR) DMA Channel 6 Interrupt Set Position */ +#define SAMHS_HST_IFR_DMA_6 (_U_(0x1) << SAMHS_HST_IFR_DMA_6_Pos) /**< (SAMHS_HST_IFR) DMA Channel 6 Interrupt Set Mask */ +#define SAMHS_HST_IFR_Msk _U_(0xFE00007F) /**< (SAMHS_HST_IFR) Register Mask */ + +#define SAMHS_HST_IFR_DMA__Pos 25 /**< (SAMHS_HST_IFR Position) DMA Channel 6 Interrupt Set */ +#define SAMHS_HST_IFR_DMA_ (_U_(0x7F) << SAMHS_HST_IFR_DMA__Pos) /**< (SAMHS_HST_IFR Mask) DMA_ */ + +/* -------- SAMHS_HST_IMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */ + +#define SAMHS_HST_IMR_OFFSET (0x410) /**< (SAMHS_HST_IMR) Host Global Interrupt Mask Register Offset */ + +#define SAMHS_HST_IMR_DCONNIE_Pos 0 /**< (SAMHS_HST_IMR) Device Connection Interrupt Enable Position */ +#define SAMHS_HST_IMR_DCONNIE (_U_(0x1) << SAMHS_HST_IMR_DCONNIE_Pos) /**< (SAMHS_HST_IMR) Device Connection Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DDISCIE_Pos 1 /**< (SAMHS_HST_IMR) Device Disconnection Interrupt Enable Position */ +#define SAMHS_HST_IMR_DDISCIE (_U_(0x1) << SAMHS_HST_IMR_DDISCIE_Pos) /**< (SAMHS_HST_IMR) Device Disconnection Interrupt Enable Mask */ +#define SAMHS_HST_IMR_RSTIE_Pos 2 /**< (SAMHS_HST_IMR) USB Reset Sent Interrupt Enable Position */ +#define SAMHS_HST_IMR_RSTIE (_U_(0x1) << SAMHS_HST_IMR_RSTIE_Pos) /**< (SAMHS_HST_IMR) USB Reset Sent Interrupt Enable Mask */ +#define SAMHS_HST_IMR_RSMEDIE_Pos 3 /**< (SAMHS_HST_IMR) Downstream Resume Sent Interrupt Enable Position */ +#define SAMHS_HST_IMR_RSMEDIE (_U_(0x1) << SAMHS_HST_IMR_RSMEDIE_Pos) /**< (SAMHS_HST_IMR) Downstream Resume Sent Interrupt Enable Mask */ +#define SAMHS_HST_IMR_RXRSMIE_Pos 4 /**< (SAMHS_HST_IMR) Upstream Resume Received Interrupt Enable Position */ +#define SAMHS_HST_IMR_RXRSMIE (_U_(0x1) << SAMHS_HST_IMR_RXRSMIE_Pos) /**< (SAMHS_HST_IMR) Upstream Resume Received Interrupt Enable Mask */ +#define SAMHS_HST_IMR_HSOFIE_Pos 5 /**< (SAMHS_HST_IMR) Host Start of Frame Interrupt Enable Position */ +#define SAMHS_HST_IMR_HSOFIE (_U_(0x1) << SAMHS_HST_IMR_HSOFIE_Pos) /**< (SAMHS_HST_IMR) Host Start of Frame Interrupt Enable Mask */ +#define SAMHS_HST_IMR_HWUPIE_Pos 6 /**< (SAMHS_HST_IMR) Host Wake-Up Interrupt Enable Position */ +#define SAMHS_HST_IMR_HWUPIE (_U_(0x1) << SAMHS_HST_IMR_HWUPIE_Pos) /**< (SAMHS_HST_IMR) Host Wake-Up Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_0_Pos 8 /**< (SAMHS_HST_IMR) Pipe 0 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_0 (_U_(0x1) << SAMHS_HST_IMR_PEP_0_Pos) /**< (SAMHS_HST_IMR) Pipe 0 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_1_Pos 9 /**< (SAMHS_HST_IMR) Pipe 1 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_1 (_U_(0x1) << SAMHS_HST_IMR_PEP_1_Pos) /**< (SAMHS_HST_IMR) Pipe 1 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_2_Pos 10 /**< (SAMHS_HST_IMR) Pipe 2 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_2 (_U_(0x1) << SAMHS_HST_IMR_PEP_2_Pos) /**< (SAMHS_HST_IMR) Pipe 2 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_3_Pos 11 /**< (SAMHS_HST_IMR) Pipe 3 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_3 (_U_(0x1) << SAMHS_HST_IMR_PEP_3_Pos) /**< (SAMHS_HST_IMR) Pipe 3 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_4_Pos 12 /**< (SAMHS_HST_IMR) Pipe 4 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_4 (_U_(0x1) << SAMHS_HST_IMR_PEP_4_Pos) /**< (SAMHS_HST_IMR) Pipe 4 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_5_Pos 13 /**< (SAMHS_HST_IMR) Pipe 5 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_5 (_U_(0x1) << SAMHS_HST_IMR_PEP_5_Pos) /**< (SAMHS_HST_IMR) Pipe 5 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_6_Pos 14 /**< (SAMHS_HST_IMR) Pipe 6 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_6 (_U_(0x1) << SAMHS_HST_IMR_PEP_6_Pos) /**< (SAMHS_HST_IMR) Pipe 6 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_7_Pos 15 /**< (SAMHS_HST_IMR) Pipe 7 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_7 (_U_(0x1) << SAMHS_HST_IMR_PEP_7_Pos) /**< (SAMHS_HST_IMR) Pipe 7 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_8_Pos 16 /**< (SAMHS_HST_IMR) Pipe 8 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_8 (_U_(0x1) << SAMHS_HST_IMR_PEP_8_Pos) /**< (SAMHS_HST_IMR) Pipe 8 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_PEP_9_Pos 17 /**< (SAMHS_HST_IMR) Pipe 9 Interrupt Enable Position */ +#define SAMHS_HST_IMR_PEP_9 (_U_(0x1) << SAMHS_HST_IMR_PEP_9_Pos) /**< (SAMHS_HST_IMR) Pipe 9 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_0_Pos 25 /**< (SAMHS_HST_IMR) DMA Channel 0 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_0 (_U_(0x1) << SAMHS_HST_IMR_DMA_0_Pos) /**< (SAMHS_HST_IMR) DMA Channel 0 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_1_Pos 26 /**< (SAMHS_HST_IMR) DMA Channel 1 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_1 (_U_(0x1) << SAMHS_HST_IMR_DMA_1_Pos) /**< (SAMHS_HST_IMR) DMA Channel 1 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_2_Pos 27 /**< (SAMHS_HST_IMR) DMA Channel 2 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_2 (_U_(0x1) << SAMHS_HST_IMR_DMA_2_Pos) /**< (SAMHS_HST_IMR) DMA Channel 2 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_3_Pos 28 /**< (SAMHS_HST_IMR) DMA Channel 3 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_3 (_U_(0x1) << SAMHS_HST_IMR_DMA_3_Pos) /**< (SAMHS_HST_IMR) DMA Channel 3 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_4_Pos 29 /**< (SAMHS_HST_IMR) DMA Channel 4 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_4 (_U_(0x1) << SAMHS_HST_IMR_DMA_4_Pos) /**< (SAMHS_HST_IMR) DMA Channel 4 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_5_Pos 30 /**< (SAMHS_HST_IMR) DMA Channel 5 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_5 (_U_(0x1) << SAMHS_HST_IMR_DMA_5_Pos) /**< (SAMHS_HST_IMR) DMA Channel 5 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_DMA_6_Pos 31 /**< (SAMHS_HST_IMR) DMA Channel 6 Interrupt Enable Position */ +#define SAMHS_HST_IMR_DMA_6 (_U_(0x1) << SAMHS_HST_IMR_DMA_6_Pos) /**< (SAMHS_HST_IMR) DMA Channel 6 Interrupt Enable Mask */ +#define SAMHS_HST_IMR_Msk _U_(0xFE03FF7F) /**< (SAMHS_HST_IMR) Register Mask */ + +#define SAMHS_HST_IMR_PEP__Pos 8 /**< (SAMHS_HST_IMR Position) Pipe x Interrupt Enable */ +#define SAMHS_HST_IMR_PEP_ (_U_(0x3FF) << SAMHS_HST_IMR_PEP__Pos) /**< (SAMHS_HST_IMR Mask) PEP_ */ +#define SAMHS_HST_IMR_DMA__Pos 25 /**< (SAMHS_HST_IMR Position) DMA Channel 6 Interrupt Enable */ +#define SAMHS_HST_IMR_DMA_ (_U_(0x7F) << SAMHS_HST_IMR_DMA__Pos) /**< (SAMHS_HST_IMR Mask) DMA_ */ + +/* -------- SAMHS_HST_IDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */ + +#define SAMHS_HST_IDR_OFFSET (0x414) /**< (SAMHS_HST_IDR) Host Global Interrupt Disable Register Offset */ + +#define SAMHS_HST_IDR_DCONNIEC_Pos 0 /**< (SAMHS_HST_IDR) Device Connection Interrupt Disable Position */ +#define SAMHS_HST_IDR_DCONNIEC (_U_(0x1) << SAMHS_HST_IDR_DCONNIEC_Pos) /**< (SAMHS_HST_IDR) Device Connection Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DDISCIEC_Pos 1 /**< (SAMHS_HST_IDR) Device Disconnection Interrupt Disable Position */ +#define SAMHS_HST_IDR_DDISCIEC (_U_(0x1) << SAMHS_HST_IDR_DDISCIEC_Pos) /**< (SAMHS_HST_IDR) Device Disconnection Interrupt Disable Mask */ +#define SAMHS_HST_IDR_RSTIEC_Pos 2 /**< (SAMHS_HST_IDR) USB Reset Sent Interrupt Disable Position */ +#define SAMHS_HST_IDR_RSTIEC (_U_(0x1) << SAMHS_HST_IDR_RSTIEC_Pos) /**< (SAMHS_HST_IDR) USB Reset Sent Interrupt Disable Mask */ +#define SAMHS_HST_IDR_RSMEDIEC_Pos 3 /**< (SAMHS_HST_IDR) Downstream Resume Sent Interrupt Disable Position */ +#define SAMHS_HST_IDR_RSMEDIEC (_U_(0x1) << SAMHS_HST_IDR_RSMEDIEC_Pos) /**< (SAMHS_HST_IDR) Downstream Resume Sent Interrupt Disable Mask */ +#define SAMHS_HST_IDR_RXRSMIEC_Pos 4 /**< (SAMHS_HST_IDR) Upstream Resume Received Interrupt Disable Position */ +#define SAMHS_HST_IDR_RXRSMIEC (_U_(0x1) << SAMHS_HST_IDR_RXRSMIEC_Pos) /**< (SAMHS_HST_IDR) Upstream Resume Received Interrupt Disable Mask */ +#define SAMHS_HST_IDR_HSOFIEC_Pos 5 /**< (SAMHS_HST_IDR) Host Start of Frame Interrupt Disable Position */ +#define SAMHS_HST_IDR_HSOFIEC (_U_(0x1) << SAMHS_HST_IDR_HSOFIEC_Pos) /**< (SAMHS_HST_IDR) Host Start of Frame Interrupt Disable Mask */ +#define SAMHS_HST_IDR_HWUPIEC_Pos 6 /**< (SAMHS_HST_IDR) Host Wake-Up Interrupt Disable Position */ +#define SAMHS_HST_IDR_HWUPIEC (_U_(0x1) << SAMHS_HST_IDR_HWUPIEC_Pos) /**< (SAMHS_HST_IDR) Host Wake-Up Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_0_Pos 8 /**< (SAMHS_HST_IDR) Pipe 0 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_0 (_U_(0x1) << SAMHS_HST_IDR_PEP_0_Pos) /**< (SAMHS_HST_IDR) Pipe 0 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_1_Pos 9 /**< (SAMHS_HST_IDR) Pipe 1 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_1 (_U_(0x1) << SAMHS_HST_IDR_PEP_1_Pos) /**< (SAMHS_HST_IDR) Pipe 1 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_2_Pos 10 /**< (SAMHS_HST_IDR) Pipe 2 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_2 (_U_(0x1) << SAMHS_HST_IDR_PEP_2_Pos) /**< (SAMHS_HST_IDR) Pipe 2 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_3_Pos 11 /**< (SAMHS_HST_IDR) Pipe 3 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_3 (_U_(0x1) << SAMHS_HST_IDR_PEP_3_Pos) /**< (SAMHS_HST_IDR) Pipe 3 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_4_Pos 12 /**< (SAMHS_HST_IDR) Pipe 4 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_4 (_U_(0x1) << SAMHS_HST_IDR_PEP_4_Pos) /**< (SAMHS_HST_IDR) Pipe 4 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_5_Pos 13 /**< (SAMHS_HST_IDR) Pipe 5 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_5 (_U_(0x1) << SAMHS_HST_IDR_PEP_5_Pos) /**< (SAMHS_HST_IDR) Pipe 5 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_6_Pos 14 /**< (SAMHS_HST_IDR) Pipe 6 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_6 (_U_(0x1) << SAMHS_HST_IDR_PEP_6_Pos) /**< (SAMHS_HST_IDR) Pipe 6 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_7_Pos 15 /**< (SAMHS_HST_IDR) Pipe 7 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_7 (_U_(0x1) << SAMHS_HST_IDR_PEP_7_Pos) /**< (SAMHS_HST_IDR) Pipe 7 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_8_Pos 16 /**< (SAMHS_HST_IDR) Pipe 8 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_8 (_U_(0x1) << SAMHS_HST_IDR_PEP_8_Pos) /**< (SAMHS_HST_IDR) Pipe 8 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_PEP_9_Pos 17 /**< (SAMHS_HST_IDR) Pipe 9 Interrupt Disable Position */ +#define SAMHS_HST_IDR_PEP_9 (_U_(0x1) << SAMHS_HST_IDR_PEP_9_Pos) /**< (SAMHS_HST_IDR) Pipe 9 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_0_Pos 25 /**< (SAMHS_HST_IDR) DMA Channel 0 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_0 (_U_(0x1) << SAMHS_HST_IDR_DMA_0_Pos) /**< (SAMHS_HST_IDR) DMA Channel 0 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_1_Pos 26 /**< (SAMHS_HST_IDR) DMA Channel 1 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_1 (_U_(0x1) << SAMHS_HST_IDR_DMA_1_Pos) /**< (SAMHS_HST_IDR) DMA Channel 1 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_2_Pos 27 /**< (SAMHS_HST_IDR) DMA Channel 2 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_2 (_U_(0x1) << SAMHS_HST_IDR_DMA_2_Pos) /**< (SAMHS_HST_IDR) DMA Channel 2 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_3_Pos 28 /**< (SAMHS_HST_IDR) DMA Channel 3 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_3 (_U_(0x1) << SAMHS_HST_IDR_DMA_3_Pos) /**< (SAMHS_HST_IDR) DMA Channel 3 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_4_Pos 29 /**< (SAMHS_HST_IDR) DMA Channel 4 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_4 (_U_(0x1) << SAMHS_HST_IDR_DMA_4_Pos) /**< (SAMHS_HST_IDR) DMA Channel 4 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_5_Pos 30 /**< (SAMHS_HST_IDR) DMA Channel 5 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_5 (_U_(0x1) << SAMHS_HST_IDR_DMA_5_Pos) /**< (SAMHS_HST_IDR) DMA Channel 5 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_DMA_6_Pos 31 /**< (SAMHS_HST_IDR) DMA Channel 6 Interrupt Disable Position */ +#define SAMHS_HST_IDR_DMA_6 (_U_(0x1) << SAMHS_HST_IDR_DMA_6_Pos) /**< (SAMHS_HST_IDR) DMA Channel 6 Interrupt Disable Mask */ +#define SAMHS_HST_IDR_Msk _U_(0xFE03FF7F) /**< (SAMHS_HST_IDR) Register Mask */ + +#define SAMHS_HST_IDR_PEP__Pos 8 /**< (SAMHS_HST_IDR Position) Pipe x Interrupt Disable */ +#define SAMHS_HST_IDR_PEP_ (_U_(0x3FF) << SAMHS_HST_IDR_PEP__Pos) /**< (SAMHS_HST_IDR Mask) PEP_ */ +#define SAMHS_HST_IDR_DMA__Pos 25 /**< (SAMHS_HST_IDR Position) DMA Channel 6 Interrupt Disable */ +#define SAMHS_HST_IDR_DMA_ (_U_(0x7F) << SAMHS_HST_IDR_DMA__Pos) /**< (SAMHS_HST_IDR Mask) DMA_ */ + +/* -------- SAMHS_HST_IER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */ + +#define SAMHS_HST_IER_OFFSET (0x418) /**< (SAMHS_HST_IER) Host Global Interrupt Enable Register Offset */ + +#define SAMHS_HST_IER_DCONNIES_Pos 0 /**< (SAMHS_HST_IER) Device Connection Interrupt Enable Position */ +#define SAMHS_HST_IER_DCONNIES (_U_(0x1) << SAMHS_HST_IER_DCONNIES_Pos) /**< (SAMHS_HST_IER) Device Connection Interrupt Enable Mask */ +#define SAMHS_HST_IER_DDISCIES_Pos 1 /**< (SAMHS_HST_IER) Device Disconnection Interrupt Enable Position */ +#define SAMHS_HST_IER_DDISCIES (_U_(0x1) << SAMHS_HST_IER_DDISCIES_Pos) /**< (SAMHS_HST_IER) Device Disconnection Interrupt Enable Mask */ +#define SAMHS_HST_IER_RSTIES_Pos 2 /**< (SAMHS_HST_IER) USB Reset Sent Interrupt Enable Position */ +#define SAMHS_HST_IER_RSTIES (_U_(0x1) << SAMHS_HST_IER_RSTIES_Pos) /**< (SAMHS_HST_IER) USB Reset Sent Interrupt Enable Mask */ +#define SAMHS_HST_IER_RSMEDIES_Pos 3 /**< (SAMHS_HST_IER) Downstream Resume Sent Interrupt Enable Position */ +#define SAMHS_HST_IER_RSMEDIES (_U_(0x1) << SAMHS_HST_IER_RSMEDIES_Pos) /**< (SAMHS_HST_IER) Downstream Resume Sent Interrupt Enable Mask */ +#define SAMHS_HST_IER_RXRSMIES_Pos 4 /**< (SAMHS_HST_IER) Upstream Resume Received Interrupt Enable Position */ +#define SAMHS_HST_IER_RXRSMIES (_U_(0x1) << SAMHS_HST_IER_RXRSMIES_Pos) /**< (SAMHS_HST_IER) Upstream Resume Received Interrupt Enable Mask */ +#define SAMHS_HST_IER_HSOFIES_Pos 5 /**< (SAMHS_HST_IER) Host Start of Frame Interrupt Enable Position */ +#define SAMHS_HST_IER_HSOFIES (_U_(0x1) << SAMHS_HST_IER_HSOFIES_Pos) /**< (SAMHS_HST_IER) Host Start of Frame Interrupt Enable Mask */ +#define SAMHS_HST_IER_HWUPIES_Pos 6 /**< (SAMHS_HST_IER) Host Wake-Up Interrupt Enable Position */ +#define SAMHS_HST_IER_HWUPIES (_U_(0x1) << SAMHS_HST_IER_HWUPIES_Pos) /**< (SAMHS_HST_IER) Host Wake-Up Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_0_Pos 8 /**< (SAMHS_HST_IER) Pipe 0 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_0 (_U_(0x1) << SAMHS_HST_IER_PEP_0_Pos) /**< (SAMHS_HST_IER) Pipe 0 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_1_Pos 9 /**< (SAMHS_HST_IER) Pipe 1 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_1 (_U_(0x1) << SAMHS_HST_IER_PEP_1_Pos) /**< (SAMHS_HST_IER) Pipe 1 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_2_Pos 10 /**< (SAMHS_HST_IER) Pipe 2 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_2 (_U_(0x1) << SAMHS_HST_IER_PEP_2_Pos) /**< (SAMHS_HST_IER) Pipe 2 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_3_Pos 11 /**< (SAMHS_HST_IER) Pipe 3 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_3 (_U_(0x1) << SAMHS_HST_IER_PEP_3_Pos) /**< (SAMHS_HST_IER) Pipe 3 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_4_Pos 12 /**< (SAMHS_HST_IER) Pipe 4 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_4 (_U_(0x1) << SAMHS_HST_IER_PEP_4_Pos) /**< (SAMHS_HST_IER) Pipe 4 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_5_Pos 13 /**< (SAMHS_HST_IER) Pipe 5 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_5 (_U_(0x1) << SAMHS_HST_IER_PEP_5_Pos) /**< (SAMHS_HST_IER) Pipe 5 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_6_Pos 14 /**< (SAMHS_HST_IER) Pipe 6 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_6 (_U_(0x1) << SAMHS_HST_IER_PEP_6_Pos) /**< (SAMHS_HST_IER) Pipe 6 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_7_Pos 15 /**< (SAMHS_HST_IER) Pipe 7 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_7 (_U_(0x1) << SAMHS_HST_IER_PEP_7_Pos) /**< (SAMHS_HST_IER) Pipe 7 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_8_Pos 16 /**< (SAMHS_HST_IER) Pipe 8 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_8 (_U_(0x1) << SAMHS_HST_IER_PEP_8_Pos) /**< (SAMHS_HST_IER) Pipe 8 Interrupt Enable Mask */ +#define SAMHS_HST_IER_PEP_9_Pos 17 /**< (SAMHS_HST_IER) Pipe 9 Interrupt Enable Position */ +#define SAMHS_HST_IER_PEP_9 (_U_(0x1) << SAMHS_HST_IER_PEP_9_Pos) /**< (SAMHS_HST_IER) Pipe 9 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_0_Pos 25 /**< (SAMHS_HST_IER) DMA Channel 0 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_0 (_U_(0x1) << SAMHS_HST_IER_DMA_0_Pos) /**< (SAMHS_HST_IER) DMA Channel 0 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_1_Pos 26 /**< (SAMHS_HST_IER) DMA Channel 1 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_1 (_U_(0x1) << SAMHS_HST_IER_DMA_1_Pos) /**< (SAMHS_HST_IER) DMA Channel 1 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_2_Pos 27 /**< (SAMHS_HST_IER) DMA Channel 2 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_2 (_U_(0x1) << SAMHS_HST_IER_DMA_2_Pos) /**< (SAMHS_HST_IER) DMA Channel 2 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_3_Pos 28 /**< (SAMHS_HST_IER) DMA Channel 3 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_3 (_U_(0x1) << SAMHS_HST_IER_DMA_3_Pos) /**< (SAMHS_HST_IER) DMA Channel 3 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_4_Pos 29 /**< (SAMHS_HST_IER) DMA Channel 4 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_4 (_U_(0x1) << SAMHS_HST_IER_DMA_4_Pos) /**< (SAMHS_HST_IER) DMA Channel 4 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_5_Pos 30 /**< (SAMHS_HST_IER) DMA Channel 5 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_5 (_U_(0x1) << SAMHS_HST_IER_DMA_5_Pos) /**< (SAMHS_HST_IER) DMA Channel 5 Interrupt Enable Mask */ +#define SAMHS_HST_IER_DMA_6_Pos 31 /**< (SAMHS_HST_IER) DMA Channel 6 Interrupt Enable Position */ +#define SAMHS_HST_IER_DMA_6 (_U_(0x1) << SAMHS_HST_IER_DMA_6_Pos) /**< (SAMHS_HST_IER) DMA Channel 6 Interrupt Enable Mask */ +#define SAMHS_HST_IER_Msk _U_(0xFE03FF7F) /**< (SAMHS_HST_IER) Register Mask */ + +#define SAMHS_HST_IER_PEP__Pos 8 /**< (SAMHS_HST_IER Position) Pipe x Interrupt Enable */ +#define SAMHS_HST_IER_PEP_ (_U_(0x3FF) << SAMHS_HST_IER_PEP__Pos) /**< (SAMHS_HST_IER Mask) PEP_ */ +#define SAMHS_HST_IER_DMA__Pos 25 /**< (SAMHS_HST_IER Position) DMA Channel 6 Interrupt Enable */ +#define SAMHS_HST_IER_DMA_ (_U_(0x7F) << SAMHS_HST_IER_DMA__Pos) /**< (SAMHS_HST_IER Mask) DMA_ */ + +/* -------- SAMHS_HST_PIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */ + +#define SAMHS_HST_PIP_OFFSET (0x41C) /**< (SAMHS_HST_PIP) Host Pipe Register Offset */ + +#define SAMHS_HST_PIP_PEN0_Pos 0 /**< (SAMHS_HST_PIP) Pipe 0 Enable Position */ +#define SAMHS_HST_PIP_PEN0 (_U_(0x1) << SAMHS_HST_PIP_PEN0_Pos) /**< (SAMHS_HST_PIP) Pipe 0 Enable Mask */ +#define SAMHS_HST_PIP_PEN1_Pos 1 /**< (SAMHS_HST_PIP) Pipe 1 Enable Position */ +#define SAMHS_HST_PIP_PEN1 (_U_(0x1) << SAMHS_HST_PIP_PEN1_Pos) /**< (SAMHS_HST_PIP) Pipe 1 Enable Mask */ +#define SAMHS_HST_PIP_PEN2_Pos 2 /**< (SAMHS_HST_PIP) Pipe 2 Enable Position */ +#define SAMHS_HST_PIP_PEN2 (_U_(0x1) << SAMHS_HST_PIP_PEN2_Pos) /**< (SAMHS_HST_PIP) Pipe 2 Enable Mask */ +#define SAMHS_HST_PIP_PEN3_Pos 3 /**< (SAMHS_HST_PIP) Pipe 3 Enable Position */ +#define SAMHS_HST_PIP_PEN3 (_U_(0x1) << SAMHS_HST_PIP_PEN3_Pos) /**< (SAMHS_HST_PIP) Pipe 3 Enable Mask */ +#define SAMHS_HST_PIP_PEN4_Pos 4 /**< (SAMHS_HST_PIP) Pipe 4 Enable Position */ +#define SAMHS_HST_PIP_PEN4 (_U_(0x1) << SAMHS_HST_PIP_PEN4_Pos) /**< (SAMHS_HST_PIP) Pipe 4 Enable Mask */ +#define SAMHS_HST_PIP_PEN5_Pos 5 /**< (SAMHS_HST_PIP) Pipe 5 Enable Position */ +#define SAMHS_HST_PIP_PEN5 (_U_(0x1) << SAMHS_HST_PIP_PEN5_Pos) /**< (SAMHS_HST_PIP) Pipe 5 Enable Mask */ +#define SAMHS_HST_PIP_PEN6_Pos 6 /**< (SAMHS_HST_PIP) Pipe 6 Enable Position */ +#define SAMHS_HST_PIP_PEN6 (_U_(0x1) << SAMHS_HST_PIP_PEN6_Pos) /**< (SAMHS_HST_PIP) Pipe 6 Enable Mask */ +#define SAMHS_HST_PIP_PEN7_Pos 7 /**< (SAMHS_HST_PIP) Pipe 7 Enable Position */ +#define SAMHS_HST_PIP_PEN7 (_U_(0x1) << SAMHS_HST_PIP_PEN7_Pos) /**< (SAMHS_HST_PIP) Pipe 7 Enable Mask */ +#define SAMHS_HST_PIP_PEN8_Pos 8 /**< (SAMHS_HST_PIP) Pipe 8 Enable Position */ +#define SAMHS_HST_PIP_PEN8 (_U_(0x1) << SAMHS_HST_PIP_PEN8_Pos) /**< (SAMHS_HST_PIP) Pipe 8 Enable Mask */ +#define SAMHS_HST_PIP_PRST0_Pos 16 /**< (SAMHS_HST_PIP) Pipe 0 Reset Position */ +#define SAMHS_HST_PIP_PRST0 (_U_(0x1) << SAMHS_HST_PIP_PRST0_Pos) /**< (SAMHS_HST_PIP) Pipe 0 Reset Mask */ +#define SAMHS_HST_PIP_PRST1_Pos 17 /**< (SAMHS_HST_PIP) Pipe 1 Reset Position */ +#define SAMHS_HST_PIP_PRST1 (_U_(0x1) << SAMHS_HST_PIP_PRST1_Pos) /**< (SAMHS_HST_PIP) Pipe 1 Reset Mask */ +#define SAMHS_HST_PIP_PRST2_Pos 18 /**< (SAMHS_HST_PIP) Pipe 2 Reset Position */ +#define SAMHS_HST_PIP_PRST2 (_U_(0x1) << SAMHS_HST_PIP_PRST2_Pos) /**< (SAMHS_HST_PIP) Pipe 2 Reset Mask */ +#define SAMHS_HST_PIP_PRST3_Pos 19 /**< (SAMHS_HST_PIP) Pipe 3 Reset Position */ +#define SAMHS_HST_PIP_PRST3 (_U_(0x1) << SAMHS_HST_PIP_PRST3_Pos) /**< (SAMHS_HST_PIP) Pipe 3 Reset Mask */ +#define SAMHS_HST_PIP_PRST4_Pos 20 /**< (SAMHS_HST_PIP) Pipe 4 Reset Position */ +#define SAMHS_HST_PIP_PRST4 (_U_(0x1) << SAMHS_HST_PIP_PRST4_Pos) /**< (SAMHS_HST_PIP) Pipe 4 Reset Mask */ +#define SAMHS_HST_PIP_PRST5_Pos 21 /**< (SAMHS_HST_PIP) Pipe 5 Reset Position */ +#define SAMHS_HST_PIP_PRST5 (_U_(0x1) << SAMHS_HST_PIP_PRST5_Pos) /**< (SAMHS_HST_PIP) Pipe 5 Reset Mask */ +#define SAMHS_HST_PIP_PRST6_Pos 22 /**< (SAMHS_HST_PIP) Pipe 6 Reset Position */ +#define SAMHS_HST_PIP_PRST6 (_U_(0x1) << SAMHS_HST_PIP_PRST6_Pos) /**< (SAMHS_HST_PIP) Pipe 6 Reset Mask */ +#define SAMHS_HST_PIP_PRST7_Pos 23 /**< (SAMHS_HST_PIP) Pipe 7 Reset Position */ +#define SAMHS_HST_PIP_PRST7 (_U_(0x1) << SAMHS_HST_PIP_PRST7_Pos) /**< (SAMHS_HST_PIP) Pipe 7 Reset Mask */ +#define SAMHS_HST_PIP_PRST8_Pos 24 /**< (SAMHS_HST_PIP) Pipe 8 Reset Position */ +#define SAMHS_HST_PIP_PRST8 (_U_(0x1) << SAMHS_HST_PIP_PRST8_Pos) /**< (SAMHS_HST_PIP) Pipe 8 Reset Mask */ +#define SAMHS_HST_PIP_Msk _U_(0x1FF01FF) /**< (SAMHS_HST_PIP) Register Mask */ + +#define SAMHS_HST_PIP_PEN_Pos 0 /**< (SAMHS_HST_PIP Position) Pipe x Enable */ +#define SAMHS_HST_PIP_PEN (_U_(0x1FF) << SAMHS_HST_PIP_PEN_Pos) /**< (SAMHS_HST_PIP Mask) PEN */ +#define SAMHS_HST_PIP_PRST_Pos 16 /**< (SAMHS_HST_PIP Position) Pipe 8 Reset */ +#define SAMHS_HST_PIP_PRST (_U_(0x1FF) << SAMHS_HST_PIP_PRST_Pos) /**< (SAMHS_HST_PIP Mask) PRST */ + +/* -------- SAMHS_HST_FNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ + +#define SAMHS_HST_FNUM_OFFSET (0x420) /**< (SAMHS_HST_FNUM) Host Frame Number Register Offset */ + +#define SAMHS_HST_FNUM_MFNUM_Pos 0 /**< (SAMHS_HST_FNUM) Micro Frame Number Position */ +#define SAMHS_HST_FNUM_MFNUM (_U_(0x7) << SAMHS_HST_FNUM_MFNUM_Pos) /**< (SAMHS_HST_FNUM) Micro Frame Number Mask */ +#define SAMHS_HST_FNUM_FNUM_Pos 3 /**< (SAMHS_HST_FNUM) Frame Number Position */ +#define SAMHS_HST_FNUM_FNUM (_U_(0x7FF) << SAMHS_HST_FNUM_FNUM_Pos) /**< (SAMHS_HST_FNUM) Frame Number Mask */ +#define SAMHS_HST_FNUM_FLENHIGH_Pos 16 /**< (SAMHS_HST_FNUM) Frame Length Position */ +#define SAMHS_HST_FNUM_FLENHIGH (_U_(0xFF) << SAMHS_HST_FNUM_FLENHIGH_Pos) /**< (SAMHS_HST_FNUM) Frame Length Mask */ +#define SAMHS_HST_FNUM_Msk _U_(0xFF3FFF) /**< (SAMHS_HST_FNUM) Register Mask */ + + +/* -------- SAMHS_HST_ADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ + +#define SAMHS_HST_ADDR1_OFFSET (0x424) /**< (SAMHS_HST_ADDR1) Host Address 1 Register Offset */ + +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP0_Pos 0 /**< (SAMHS_HST_ADDR1) USB Host Address Position */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP0 (_U_(0x7F) << SAMHS_HST_ADDR1_SAMHS_HST_ADDRP0_Pos) /**< (SAMHS_HST_ADDR1) USB Host Address Mask */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP1_Pos 8 /**< (SAMHS_HST_ADDR1) USB Host Address Position */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP1 (_U_(0x7F) << SAMHS_HST_ADDR1_SAMHS_HST_ADDRP1_Pos) /**< (SAMHS_HST_ADDR1) USB Host Address Mask */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP2_Pos 16 /**< (SAMHS_HST_ADDR1) USB Host Address Position */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP2 (_U_(0x7F) << SAMHS_HST_ADDR1_SAMHS_HST_ADDRP2_Pos) /**< (SAMHS_HST_ADDR1) USB Host Address Mask */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP3_Pos 24 /**< (SAMHS_HST_ADDR1) USB Host Address Position */ +#define SAMHS_HST_ADDR1_SAMHS_HST_ADDRP3 (_U_(0x7F) << SAMHS_HST_ADDR1_SAMHS_HST_ADDRP3_Pos) /**< (SAMHS_HST_ADDR1) USB Host Address Mask */ +#define SAMHS_HST_ADDR1_Msk _U_(0x7F7F7F7F) /**< (SAMHS_HST_ADDR1) Register Mask */ + + +/* -------- SAMHS_HST_ADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ + +#define SAMHS_HST_ADDR2_OFFSET (0x428) /**< (SAMHS_HST_ADDR2) Host Address 2 Register Offset */ + +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP4_Pos 0 /**< (SAMHS_HST_ADDR2) USB Host Address Position */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP4 (_U_(0x7F) << SAMHS_HST_ADDR2_SAMHS_HST_ADDRP4_Pos) /**< (SAMHS_HST_ADDR2) USB Host Address Mask */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP5_Pos 8 /**< (SAMHS_HST_ADDR2) USB Host Address Position */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP5 (_U_(0x7F) << SAMHS_HST_ADDR2_SAMHS_HST_ADDRP5_Pos) /**< (SAMHS_HST_ADDR2) USB Host Address Mask */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP6_Pos 16 /**< (SAMHS_HST_ADDR2) USB Host Address Position */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP6 (_U_(0x7F) << SAMHS_HST_ADDR2_SAMHS_HST_ADDRP6_Pos) /**< (SAMHS_HST_ADDR2) USB Host Address Mask */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP7_Pos 24 /**< (SAMHS_HST_ADDR2) USB Host Address Position */ +#define SAMHS_HST_ADDR2_SAMHS_HST_ADDRP7 (_U_(0x7F) << SAMHS_HST_ADDR2_SAMHS_HST_ADDRP7_Pos) /**< (SAMHS_HST_ADDR2) USB Host Address Mask */ +#define SAMHS_HST_ADDR2_Msk _U_(0x7F7F7F7F) /**< (SAMHS_HST_ADDR2) Register Mask */ + + +/* -------- SAMHS_HST_ADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */ + +#define SAMHS_HST_ADDR3_OFFSET (0x42C) /**< (SAMHS_HST_ADDR3) Host Address 3 Register Offset */ + +#define SAMHS_HST_ADDR3_SAMHS_HST_ADDRP8_Pos 0 /**< (SAMHS_HST_ADDR3) USB Host Address Position */ +#define SAMHS_HST_ADDR3_SAMHS_HST_ADDRP8 (_U_(0x7F) << SAMHS_HST_ADDR3_SAMHS_HST_ADDRP8_Pos) /**< (SAMHS_HST_ADDR3) USB Host Address Mask */ +#define SAMHS_HST_ADDR3_SAMHS_HST_ADDRP9_Pos 8 /**< (SAMHS_HST_ADDR3) USB Host Address Position */ +#define SAMHS_HST_ADDR3_SAMHS_HST_ADDRP9 (_U_(0x7F) << SAMHS_HST_ADDR3_SAMHS_HST_ADDRP9_Pos) /**< (SAMHS_HST_ADDR3) USB Host Address Mask */ +#define SAMHS_HST_ADDR3_Msk _U_(0x7F7F) /**< (SAMHS_HST_ADDR3) Register Mask */ + + +/* -------- SAMHS_HST_PIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */ + +#define SAMHS_HST_PIPCFG_OFFSET (0x500) /**< (SAMHS_HST_PIPCFG) Host Pipe Configuration Register Offset */ + +#define SAMHS_HST_PIPCFG_ALLOC_Pos 1 /**< (SAMHS_HST_PIPCFG) Pipe Memory Allocate Position */ +#define SAMHS_HST_PIPCFG_ALLOC (_U_(0x1) << SAMHS_HST_PIPCFG_ALLOC_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Memory Allocate Mask */ +#define SAMHS_HST_PIPCFG_PBK_Pos 2 /**< (SAMHS_HST_PIPCFG) Pipe Banks Position */ +#define SAMHS_HST_PIPCFG_PBK (_U_(0x3) << SAMHS_HST_PIPCFG_PBK_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Banks Mask */ +#define SAMHS_HST_PIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (SAMHS_HST_PIPCFG) Single-bank pipe */ +#define SAMHS_HST_PIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (SAMHS_HST_PIPCFG) Double-bank pipe */ +#define SAMHS_HST_PIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (SAMHS_HST_PIPCFG) Triple-bank pipe */ +#define SAMHS_HST_PIPCFG_PBK_1_BANK (SAMHS_HST_PIPCFG_PBK_1_BANK_Val << SAMHS_HST_PIPCFG_PBK_Pos) /**< (SAMHS_HST_PIPCFG) Single-bank pipe Position */ +#define SAMHS_HST_PIPCFG_PBK_2_BANK (SAMHS_HST_PIPCFG_PBK_2_BANK_Val << SAMHS_HST_PIPCFG_PBK_Pos) /**< (SAMHS_HST_PIPCFG) Double-bank pipe Position */ +#define SAMHS_HST_PIPCFG_PBK_3_BANK (SAMHS_HST_PIPCFG_PBK_3_BANK_Val << SAMHS_HST_PIPCFG_PBK_Pos) /**< (SAMHS_HST_PIPCFG) Triple-bank pipe Position */ +#define SAMHS_HST_PIPCFG_PSIZE_Pos 4 /**< (SAMHS_HST_PIPCFG) Pipe Size Position */ +#define SAMHS_HST_PIPCFG_PSIZE (_U_(0x7) << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Size Mask */ +#define SAMHS_HST_PIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (SAMHS_HST_PIPCFG) 8 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (SAMHS_HST_PIPCFG) 16 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (SAMHS_HST_PIPCFG) 32 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (SAMHS_HST_PIPCFG) 64 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (SAMHS_HST_PIPCFG) 128 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (SAMHS_HST_PIPCFG) 256 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (SAMHS_HST_PIPCFG) 512 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (SAMHS_HST_PIPCFG) 1024 bytes */ +#define SAMHS_HST_PIPCFG_PSIZE_8_BYTE (SAMHS_HST_PIPCFG_PSIZE_8_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 8 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_16_BYTE (SAMHS_HST_PIPCFG_PSIZE_16_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 16 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_32_BYTE (SAMHS_HST_PIPCFG_PSIZE_32_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 32 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_64_BYTE (SAMHS_HST_PIPCFG_PSIZE_64_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 64 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_128_BYTE (SAMHS_HST_PIPCFG_PSIZE_128_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 128 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_256_BYTE (SAMHS_HST_PIPCFG_PSIZE_256_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 256 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_512_BYTE (SAMHS_HST_PIPCFG_PSIZE_512_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 512 bytes Position */ +#define SAMHS_HST_PIPCFG_PSIZE_1024_BYTE (SAMHS_HST_PIPCFG_PSIZE_1024_BYTE_Val << SAMHS_HST_PIPCFG_PSIZE_Pos) /**< (SAMHS_HST_PIPCFG) 1024 bytes Position */ +#define SAMHS_HST_PIPCFG_PTOKEN_Pos 8 /**< (SAMHS_HST_PIPCFG) Pipe Token Position */ +#define SAMHS_HST_PIPCFG_PTOKEN (_U_(0x3) << SAMHS_HST_PIPCFG_PTOKEN_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Token Mask */ +#define SAMHS_HST_PIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (SAMHS_HST_PIPCFG) SETUP */ +#define SAMHS_HST_PIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (SAMHS_HST_PIPCFG) IN */ +#define SAMHS_HST_PIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (SAMHS_HST_PIPCFG) OUT */ +#define SAMHS_HST_PIPCFG_PTOKEN_SETUP (SAMHS_HST_PIPCFG_PTOKEN_SETUP_Val << SAMHS_HST_PIPCFG_PTOKEN_Pos) /**< (SAMHS_HST_PIPCFG) SETUP Position */ +#define SAMHS_HST_PIPCFG_PTOKEN_IN (SAMHS_HST_PIPCFG_PTOKEN_IN_Val << SAMHS_HST_PIPCFG_PTOKEN_Pos) /**< (SAMHS_HST_PIPCFG) IN Position */ +#define SAMHS_HST_PIPCFG_PTOKEN_OUT (SAMHS_HST_PIPCFG_PTOKEN_OUT_Val << SAMHS_HST_PIPCFG_PTOKEN_Pos) /**< (SAMHS_HST_PIPCFG) OUT Position */ +#define SAMHS_HST_PIPCFG_AUTOSW_Pos 10 /**< (SAMHS_HST_PIPCFG) Automatic Switch Position */ +#define SAMHS_HST_PIPCFG_AUTOSW (_U_(0x1) << SAMHS_HST_PIPCFG_AUTOSW_Pos) /**< (SAMHS_HST_PIPCFG) Automatic Switch Mask */ +#define SAMHS_HST_PIPCFG_PTYPE_Pos 12 /**< (SAMHS_HST_PIPCFG) Pipe Type Position */ +#define SAMHS_HST_PIPCFG_PTYPE (_U_(0x3) << SAMHS_HST_PIPCFG_PTYPE_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Type Mask */ +#define SAMHS_HST_PIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (SAMHS_HST_PIPCFG) Control */ +#define SAMHS_HST_PIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (SAMHS_HST_PIPCFG) Isochronous */ +#define SAMHS_HST_PIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (SAMHS_HST_PIPCFG) Bulk */ +#define SAMHS_HST_PIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (SAMHS_HST_PIPCFG) Interrupt */ +#define SAMHS_HST_PIPCFG_PTYPE_CTRL (SAMHS_HST_PIPCFG_PTYPE_CTRL_Val << SAMHS_HST_PIPCFG_PTYPE_Pos) /**< (SAMHS_HST_PIPCFG) Control Position */ +#define SAMHS_HST_PIPCFG_PTYPE_ISO (SAMHS_HST_PIPCFG_PTYPE_ISO_Val << SAMHS_HST_PIPCFG_PTYPE_Pos) /**< (SAMHS_HST_PIPCFG) Isochronous Position */ +#define SAMHS_HST_PIPCFG_PTYPE_BLK (SAMHS_HST_PIPCFG_PTYPE_BLK_Val << SAMHS_HST_PIPCFG_PTYPE_Pos) /**< (SAMHS_HST_PIPCFG) Bulk Position */ +#define SAMHS_HST_PIPCFG_PTYPE_INTRPT (SAMHS_HST_PIPCFG_PTYPE_INTRPT_Val << SAMHS_HST_PIPCFG_PTYPE_Pos) /**< (SAMHS_HST_PIPCFG) Interrupt Position */ +#define SAMHS_HST_PIPCFG_PEPNUM_Pos 16 /**< (SAMHS_HST_PIPCFG) Pipe Endpoint Number Position */ +#define SAMHS_HST_PIPCFG_PEPNUM (_U_(0xF) << SAMHS_HST_PIPCFG_PEPNUM_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Endpoint Number Mask */ +#define SAMHS_HST_PIPCFG_INTFRQ_Pos 24 /**< (SAMHS_HST_PIPCFG) Pipe Interrupt Request Frequency Position */ +#define SAMHS_HST_PIPCFG_INTFRQ (_U_(0xFF) << SAMHS_HST_PIPCFG_INTFRQ_Pos) /**< (SAMHS_HST_PIPCFG) Pipe Interrupt Request Frequency Mask */ +#define SAMHS_HST_PIPCFG_Msk _U_(0xFF0F377E) /**< (SAMHS_HST_PIPCFG) Register Mask */ + +/* CTRL_BULK mode */ +#define SAMHS_HST_PIPCFG_CTRL_BULK_PINGEN_Pos 20 /**< (SAMHS_HST_PIPCFG) Ping Enable Position */ +#define SAMHS_HST_PIPCFG_CTRL_BULK_PINGEN (_U_(0x1) << SAMHS_HST_PIPCFG_CTRL_BULK_PINGEN_Pos) /**< (SAMHS_HST_PIPCFG) Ping Enable Mask */ +#define SAMHS_HST_PIPCFG_CTRL_BULK_BINTERVAL_Pos 24 /**< (SAMHS_HST_PIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */ +#define SAMHS_HST_PIPCFG_CTRL_BULK_BINTERVAL (_U_(0xFF) << SAMHS_HST_PIPCFG_CTRL_BULK_BINTERVAL_Pos) /**< (SAMHS_HST_PIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */ +#define SAMHS_HST_PIPCFG_CTRL_BULK_Msk _U_(0xFF100000) /**< (SAMHS_HST_PIPCFG_CTRL_BULK) Register Mask */ + + +/* -------- SAMHS_HST_PIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */ + +#define SAMHS_HST_PIPISR_OFFSET (0x530) /**< (SAMHS_HST_PIPISR) Host Pipe Status Register Offset */ + +#define SAMHS_HST_PIPISR_RXINI_Pos 0 /**< (SAMHS_HST_PIPISR) Received IN Data Interrupt Position */ +#define SAMHS_HST_PIPISR_RXINI (_U_(0x1) << SAMHS_HST_PIPISR_RXINI_Pos) /**< (SAMHS_HST_PIPISR) Received IN Data Interrupt Mask */ +#define SAMHS_HST_PIPISR_TXOUTI_Pos 1 /**< (SAMHS_HST_PIPISR) Transmitted OUT Data Interrupt Position */ +#define SAMHS_HST_PIPISR_TXOUTI (_U_(0x1) << SAMHS_HST_PIPISR_TXOUTI_Pos) /**< (SAMHS_HST_PIPISR) Transmitted OUT Data Interrupt Mask */ +#define SAMHS_HST_PIPISR_PERRI_Pos 3 /**< (SAMHS_HST_PIPISR) Pipe Error Interrupt Position */ +#define SAMHS_HST_PIPISR_PERRI (_U_(0x1) << SAMHS_HST_PIPISR_PERRI_Pos) /**< (SAMHS_HST_PIPISR) Pipe Error Interrupt Mask */ +#define SAMHS_HST_PIPISR_NAKEDI_Pos 4 /**< (SAMHS_HST_PIPISR) NAKed Interrupt Position */ +#define SAMHS_HST_PIPISR_NAKEDI (_U_(0x1) << SAMHS_HST_PIPISR_NAKEDI_Pos) /**< (SAMHS_HST_PIPISR) NAKed Interrupt Mask */ +#define SAMHS_HST_PIPISR_OVERFI_Pos 5 /**< (SAMHS_HST_PIPISR) Overflow Interrupt Position */ +#define SAMHS_HST_PIPISR_OVERFI (_U_(0x1) << SAMHS_HST_PIPISR_OVERFI_Pos) /**< (SAMHS_HST_PIPISR) Overflow Interrupt Mask */ +#define SAMHS_HST_PIPISR_SHORTPACKETI_Pos 7 /**< (SAMHS_HST_PIPISR) Short Packet Interrupt Position */ +#define SAMHS_HST_PIPISR_SHORTPACKETI (_U_(0x1) << SAMHS_HST_PIPISR_SHORTPACKETI_Pos) /**< (SAMHS_HST_PIPISR) Short Packet Interrupt Mask */ +#define SAMHS_HST_PIPISR_DTSEQ_Pos 8 /**< (SAMHS_HST_PIPISR) Data Toggle Sequence Position */ +#define SAMHS_HST_PIPISR_DTSEQ (_U_(0x3) << SAMHS_HST_PIPISR_DTSEQ_Pos) /**< (SAMHS_HST_PIPISR) Data Toggle Sequence Mask */ +#define SAMHS_HST_PIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (SAMHS_HST_PIPISR) Data0 toggle sequence */ +#define SAMHS_HST_PIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (SAMHS_HST_PIPISR) Data1 toggle sequence */ +#define SAMHS_HST_PIPISR_DTSEQ_DATA0 (SAMHS_HST_PIPISR_DTSEQ_DATA0_Val << SAMHS_HST_PIPISR_DTSEQ_Pos) /**< (SAMHS_HST_PIPISR) Data0 toggle sequence Position */ +#define SAMHS_HST_PIPISR_DTSEQ_DATA1 (SAMHS_HST_PIPISR_DTSEQ_DATA1_Val << SAMHS_HST_PIPISR_DTSEQ_Pos) /**< (SAMHS_HST_PIPISR) Data1 toggle sequence Position */ +#define SAMHS_HST_PIPISR_NBUSYBK_Pos 12 /**< (SAMHS_HST_PIPISR) Number of Busy Banks Position */ +#define SAMHS_HST_PIPISR_NBUSYBK (_U_(0x3) << SAMHS_HST_PIPISR_NBUSYBK_Pos) /**< (SAMHS_HST_PIPISR) Number of Busy Banks Mask */ +#define SAMHS_HST_PIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (SAMHS_HST_PIPISR) 0 busy bank (all banks free) */ +#define SAMHS_HST_PIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (SAMHS_HST_PIPISR) 1 busy bank */ +#define SAMHS_HST_PIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (SAMHS_HST_PIPISR) 2 busy banks */ +#define SAMHS_HST_PIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (SAMHS_HST_PIPISR) 3 busy banks */ +#define SAMHS_HST_PIPISR_NBUSYBK_0_BUSY (SAMHS_HST_PIPISR_NBUSYBK_0_BUSY_Val << SAMHS_HST_PIPISR_NBUSYBK_Pos) /**< (SAMHS_HST_PIPISR) 0 busy bank (all banks free) Position */ +#define SAMHS_HST_PIPISR_NBUSYBK_1_BUSY (SAMHS_HST_PIPISR_NBUSYBK_1_BUSY_Val << SAMHS_HST_PIPISR_NBUSYBK_Pos) /**< (SAMHS_HST_PIPISR) 1 busy bank Position */ +#define SAMHS_HST_PIPISR_NBUSYBK_2_BUSY (SAMHS_HST_PIPISR_NBUSYBK_2_BUSY_Val << SAMHS_HST_PIPISR_NBUSYBK_Pos) /**< (SAMHS_HST_PIPISR) 2 busy banks Position */ +#define SAMHS_HST_PIPISR_NBUSYBK_3_BUSY (SAMHS_HST_PIPISR_NBUSYBK_3_BUSY_Val << SAMHS_HST_PIPISR_NBUSYBK_Pos) /**< (SAMHS_HST_PIPISR) 3 busy banks Position */ +#define SAMHS_HST_PIPISR_CURRBK_Pos 14 /**< (SAMHS_HST_PIPISR) Current Bank Position */ +#define SAMHS_HST_PIPISR_CURRBK (_U_(0x3) << SAMHS_HST_PIPISR_CURRBK_Pos) /**< (SAMHS_HST_PIPISR) Current Bank Mask */ +#define SAMHS_HST_PIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (SAMHS_HST_PIPISR) Current bank is bank0 */ +#define SAMHS_HST_PIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (SAMHS_HST_PIPISR) Current bank is bank1 */ +#define SAMHS_HST_PIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (SAMHS_HST_PIPISR) Current bank is bank2 */ +#define SAMHS_HST_PIPISR_CURRBK_BANK0 (SAMHS_HST_PIPISR_CURRBK_BANK0_Val << SAMHS_HST_PIPISR_CURRBK_Pos) /**< (SAMHS_HST_PIPISR) Current bank is bank0 Position */ +#define SAMHS_HST_PIPISR_CURRBK_BANK1 (SAMHS_HST_PIPISR_CURRBK_BANK1_Val << SAMHS_HST_PIPISR_CURRBK_Pos) /**< (SAMHS_HST_PIPISR) Current bank is bank1 Position */ +#define SAMHS_HST_PIPISR_CURRBK_BANK2 (SAMHS_HST_PIPISR_CURRBK_BANK2_Val << SAMHS_HST_PIPISR_CURRBK_Pos) /**< (SAMHS_HST_PIPISR) Current bank is bank2 Position */ +#define SAMHS_HST_PIPISR_RWALL_Pos 16 /**< (SAMHS_HST_PIPISR) Read/Write Allowed Position */ +#define SAMHS_HST_PIPISR_RWALL (_U_(0x1) << SAMHS_HST_PIPISR_RWALL_Pos) /**< (SAMHS_HST_PIPISR) Read/Write Allowed Mask */ +#define SAMHS_HST_PIPISR_CFGOK_Pos 18 /**< (SAMHS_HST_PIPISR) Configuration OK Status Position */ +#define SAMHS_HST_PIPISR_CFGOK (_U_(0x1) << SAMHS_HST_PIPISR_CFGOK_Pos) /**< (SAMHS_HST_PIPISR) Configuration OK Status Mask */ +#define SAMHS_HST_PIPISR_PBYCT_Pos 20 /**< (SAMHS_HST_PIPISR) Pipe Byte Count Position */ +#define SAMHS_HST_PIPISR_PBYCT (_U_(0x7FF) << SAMHS_HST_PIPISR_PBYCT_Pos) /**< (SAMHS_HST_PIPISR) Pipe Byte Count Mask */ +#define SAMHS_HST_PIPISR_Msk _U_(0x7FF5F3BB) /**< (SAMHS_HST_PIPISR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_HST_PIPISR_CTRL_TXSTPI_Pos 2 /**< (SAMHS_HST_PIPISR) Transmitted SETUP Interrupt Position */ +#define SAMHS_HST_PIPISR_CTRL_TXSTPI (_U_(0x1) << SAMHS_HST_PIPISR_CTRL_TXSTPI_Pos) /**< (SAMHS_HST_PIPISR) Transmitted SETUP Interrupt Mask */ +#define SAMHS_HST_PIPISR_CTRL_RXSTALLDI_Pos 6 /**< (SAMHS_HST_PIPISR) Received STALLed Interrupt Position */ +#define SAMHS_HST_PIPISR_CTRL_RXSTALLDI (_U_(0x1) << SAMHS_HST_PIPISR_CTRL_RXSTALLDI_Pos) /**< (SAMHS_HST_PIPISR) Received STALLed Interrupt Mask */ +#define SAMHS_HST_PIPISR_CTRL_Msk _U_(0x44) /**< (SAMHS_HST_PIPISR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_HST_PIPISR_ISO_UNDERFI_Pos 2 /**< (SAMHS_HST_PIPISR) Underflow Interrupt Position */ +#define SAMHS_HST_PIPISR_ISO_UNDERFI (_U_(0x1) << SAMHS_HST_PIPISR_ISO_UNDERFI_Pos) /**< (SAMHS_HST_PIPISR) Underflow Interrupt Mask */ +#define SAMHS_HST_PIPISR_ISO_CRCERRI_Pos 6 /**< (SAMHS_HST_PIPISR) CRC Error Interrupt Position */ +#define SAMHS_HST_PIPISR_ISO_CRCERRI (_U_(0x1) << SAMHS_HST_PIPISR_ISO_CRCERRI_Pos) /**< (SAMHS_HST_PIPISR) CRC Error Interrupt Mask */ +#define SAMHS_HST_PIPISR_ISO_Msk _U_(0x44) /**< (SAMHS_HST_PIPISR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_HST_PIPISR_BLK_TXSTPI_Pos 2 /**< (SAMHS_HST_PIPISR) Transmitted SETUP Interrupt Position */ +#define SAMHS_HST_PIPISR_BLK_TXSTPI (_U_(0x1) << SAMHS_HST_PIPISR_BLK_TXSTPI_Pos) /**< (SAMHS_HST_PIPISR) Transmitted SETUP Interrupt Mask */ +#define SAMHS_HST_PIPISR_BLK_RXSTALLDI_Pos 6 /**< (SAMHS_HST_PIPISR) Received STALLed Interrupt Position */ +#define SAMHS_HST_PIPISR_BLK_RXSTALLDI (_U_(0x1) << SAMHS_HST_PIPISR_BLK_RXSTALLDI_Pos) /**< (SAMHS_HST_PIPISR) Received STALLed Interrupt Mask */ +#define SAMHS_HST_PIPISR_BLK_Msk _U_(0x44) /**< (SAMHS_HST_PIPISR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_HST_PIPISR_INTRPT_UNDERFI_Pos 2 /**< (SAMHS_HST_PIPISR) Underflow Interrupt Position */ +#define SAMHS_HST_PIPISR_INTRPT_UNDERFI (_U_(0x1) << SAMHS_HST_PIPISR_INTRPT_UNDERFI_Pos) /**< (SAMHS_HST_PIPISR) Underflow Interrupt Mask */ +#define SAMHS_HST_PIPISR_INTRPT_RXSTALLDI_Pos 6 /**< (SAMHS_HST_PIPISR) Received STALLed Interrupt Position */ +#define SAMHS_HST_PIPISR_INTRPT_RXSTALLDI (_U_(0x1) << SAMHS_HST_PIPISR_INTRPT_RXSTALLDI_Pos) /**< (SAMHS_HST_PIPISR) Received STALLed Interrupt Mask */ +#define SAMHS_HST_PIPISR_INTRPT_Msk _U_(0x44) /**< (SAMHS_HST_PIPISR_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_PIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */ + +#define SAMHS_HST_PIPICR_OFFSET (0x560) /**< (SAMHS_HST_PIPICR) Host Pipe Clear Register Offset */ + +#define SAMHS_HST_PIPICR_RXINIC_Pos 0 /**< (SAMHS_HST_PIPICR) Received IN Data Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_RXINIC (_U_(0x1) << SAMHS_HST_PIPICR_RXINIC_Pos) /**< (SAMHS_HST_PIPICR) Received IN Data Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_TXOUTIC_Pos 1 /**< (SAMHS_HST_PIPICR) Transmitted OUT Data Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_TXOUTIC (_U_(0x1) << SAMHS_HST_PIPICR_TXOUTIC_Pos) /**< (SAMHS_HST_PIPICR) Transmitted OUT Data Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_NAKEDIC_Pos 4 /**< (SAMHS_HST_PIPICR) NAKed Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_NAKEDIC (_U_(0x1) << SAMHS_HST_PIPICR_NAKEDIC_Pos) /**< (SAMHS_HST_PIPICR) NAKed Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_OVERFIC_Pos 5 /**< (SAMHS_HST_PIPICR) Overflow Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_OVERFIC (_U_(0x1) << SAMHS_HST_PIPICR_OVERFIC_Pos) /**< (SAMHS_HST_PIPICR) Overflow Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_SHORTPACKETIC_Pos 7 /**< (SAMHS_HST_PIPICR) Short Packet Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_SHORTPACKETIC (_U_(0x1) << SAMHS_HST_PIPICR_SHORTPACKETIC_Pos) /**< (SAMHS_HST_PIPICR) Short Packet Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_Msk _U_(0xB3) /**< (SAMHS_HST_PIPICR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_HST_PIPICR_CTRL_TXSTPIC_Pos 2 /**< (SAMHS_HST_PIPICR) Transmitted SETUP Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_CTRL_TXSTPIC (_U_(0x1) << SAMHS_HST_PIPICR_CTRL_TXSTPIC_Pos) /**< (SAMHS_HST_PIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_CTRL_RXSTALLDIC_Pos 6 /**< (SAMHS_HST_PIPICR) Received STALLed Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_CTRL_RXSTALLDIC (_U_(0x1) << SAMHS_HST_PIPICR_CTRL_RXSTALLDIC_Pos) /**< (SAMHS_HST_PIPICR) Received STALLed Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_CTRL_Msk _U_(0x44) /**< (SAMHS_HST_PIPICR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_HST_PIPICR_ISO_UNDERFIC_Pos 2 /**< (SAMHS_HST_PIPICR) Underflow Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_ISO_UNDERFIC (_U_(0x1) << SAMHS_HST_PIPICR_ISO_UNDERFIC_Pos) /**< (SAMHS_HST_PIPICR) Underflow Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_ISO_CRCERRIC_Pos 6 /**< (SAMHS_HST_PIPICR) CRC Error Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_ISO_CRCERRIC (_U_(0x1) << SAMHS_HST_PIPICR_ISO_CRCERRIC_Pos) /**< (SAMHS_HST_PIPICR) CRC Error Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_ISO_Msk _U_(0x44) /**< (SAMHS_HST_PIPICR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_HST_PIPICR_BLK_TXSTPIC_Pos 2 /**< (SAMHS_HST_PIPICR) Transmitted SETUP Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_BLK_TXSTPIC (_U_(0x1) << SAMHS_HST_PIPICR_BLK_TXSTPIC_Pos) /**< (SAMHS_HST_PIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_BLK_RXSTALLDIC_Pos 6 /**< (SAMHS_HST_PIPICR) Received STALLed Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_BLK_RXSTALLDIC (_U_(0x1) << SAMHS_HST_PIPICR_BLK_RXSTALLDIC_Pos) /**< (SAMHS_HST_PIPICR) Received STALLed Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_BLK_Msk _U_(0x44) /**< (SAMHS_HST_PIPICR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_HST_PIPICR_INTRPT_UNDERFIC_Pos 2 /**< (SAMHS_HST_PIPICR) Underflow Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_INTRPT_UNDERFIC (_U_(0x1) << SAMHS_HST_PIPICR_INTRPT_UNDERFIC_Pos) /**< (SAMHS_HST_PIPICR) Underflow Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_INTRPT_RXSTALLDIC_Pos 6 /**< (SAMHS_HST_PIPICR) Received STALLed Interrupt Clear Position */ +#define SAMHS_HST_PIPICR_INTRPT_RXSTALLDIC (_U_(0x1) << SAMHS_HST_PIPICR_INTRPT_RXSTALLDIC_Pos) /**< (SAMHS_HST_PIPICR) Received STALLed Interrupt Clear Mask */ +#define SAMHS_HST_PIPICR_INTRPT_Msk _U_(0x44) /**< (SAMHS_HST_PIPICR_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_PIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */ + +#define SAMHS_HST_PIPIFR_OFFSET (0x590) /**< (SAMHS_HST_PIPIFR) Host Pipe Set Register Offset */ + +#define SAMHS_HST_PIPIFR_RXINIS_Pos 0 /**< (SAMHS_HST_PIPIFR) Received IN Data Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_RXINIS (_U_(0x1) << SAMHS_HST_PIPIFR_RXINIS_Pos) /**< (SAMHS_HST_PIPIFR) Received IN Data Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_TXOUTIS_Pos 1 /**< (SAMHS_HST_PIPIFR) Transmitted OUT Data Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_TXOUTIS (_U_(0x1) << SAMHS_HST_PIPIFR_TXOUTIS_Pos) /**< (SAMHS_HST_PIPIFR) Transmitted OUT Data Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_PERRIS_Pos 3 /**< (SAMHS_HST_PIPIFR) Pipe Error Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_PERRIS (_U_(0x1) << SAMHS_HST_PIPIFR_PERRIS_Pos) /**< (SAMHS_HST_PIPIFR) Pipe Error Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_NAKEDIS_Pos 4 /**< (SAMHS_HST_PIPIFR) NAKed Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_NAKEDIS (_U_(0x1) << SAMHS_HST_PIPIFR_NAKEDIS_Pos) /**< (SAMHS_HST_PIPIFR) NAKed Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_OVERFIS_Pos 5 /**< (SAMHS_HST_PIPIFR) Overflow Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_OVERFIS (_U_(0x1) << SAMHS_HST_PIPIFR_OVERFIS_Pos) /**< (SAMHS_HST_PIPIFR) Overflow Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_SHORTPACKETIS_Pos 7 /**< (SAMHS_HST_PIPIFR) Short Packet Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_SHORTPACKETIS (_U_(0x1) << SAMHS_HST_PIPIFR_SHORTPACKETIS_Pos) /**< (SAMHS_HST_PIPIFR) Short Packet Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_NBUSYBKS_Pos 12 /**< (SAMHS_HST_PIPIFR) Number of Busy Banks Set Position */ +#define SAMHS_HST_PIPIFR_NBUSYBKS (_U_(0x1) << SAMHS_HST_PIPIFR_NBUSYBKS_Pos) /**< (SAMHS_HST_PIPIFR) Number of Busy Banks Set Mask */ +#define SAMHS_HST_PIPIFR_Msk _U_(0x10BB) /**< (SAMHS_HST_PIPIFR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_HST_PIPIFR_CTRL_TXSTPIS_Pos 2 /**< (SAMHS_HST_PIPIFR) Transmitted SETUP Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_CTRL_TXSTPIS (_U_(0x1) << SAMHS_HST_PIPIFR_CTRL_TXSTPIS_Pos) /**< (SAMHS_HST_PIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_CTRL_RXSTALLDIS_Pos 6 /**< (SAMHS_HST_PIPIFR) Received STALLed Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_CTRL_RXSTALLDIS (_U_(0x1) << SAMHS_HST_PIPIFR_CTRL_RXSTALLDIS_Pos) /**< (SAMHS_HST_PIPIFR) Received STALLed Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_CTRL_Msk _U_(0x44) /**< (SAMHS_HST_PIPIFR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_HST_PIPIFR_ISO_UNDERFIS_Pos 2 /**< (SAMHS_HST_PIPIFR) Underflow Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_ISO_UNDERFIS (_U_(0x1) << SAMHS_HST_PIPIFR_ISO_UNDERFIS_Pos) /**< (SAMHS_HST_PIPIFR) Underflow Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_ISO_CRCERRIS_Pos 6 /**< (SAMHS_HST_PIPIFR) CRC Error Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_ISO_CRCERRIS (_U_(0x1) << SAMHS_HST_PIPIFR_ISO_CRCERRIS_Pos) /**< (SAMHS_HST_PIPIFR) CRC Error Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_ISO_Msk _U_(0x44) /**< (SAMHS_HST_PIPIFR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_HST_PIPIFR_BLK_TXSTPIS_Pos 2 /**< (SAMHS_HST_PIPIFR) Transmitted SETUP Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_BLK_TXSTPIS (_U_(0x1) << SAMHS_HST_PIPIFR_BLK_TXSTPIS_Pos) /**< (SAMHS_HST_PIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_BLK_RXSTALLDIS_Pos 6 /**< (SAMHS_HST_PIPIFR) Received STALLed Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_BLK_RXSTALLDIS (_U_(0x1) << SAMHS_HST_PIPIFR_BLK_RXSTALLDIS_Pos) /**< (SAMHS_HST_PIPIFR) Received STALLed Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_BLK_Msk _U_(0x44) /**< (SAMHS_HST_PIPIFR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_HST_PIPIFR_INTRPT_UNDERFIS_Pos 2 /**< (SAMHS_HST_PIPIFR) Underflow Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_INTRPT_UNDERFIS (_U_(0x1) << SAMHS_HST_PIPIFR_INTRPT_UNDERFIS_Pos) /**< (SAMHS_HST_PIPIFR) Underflow Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_INTRPT_RXSTALLDIS_Pos 6 /**< (SAMHS_HST_PIPIFR) Received STALLed Interrupt Set Position */ +#define SAMHS_HST_PIPIFR_INTRPT_RXSTALLDIS (_U_(0x1) << SAMHS_HST_PIPIFR_INTRPT_RXSTALLDIS_Pos) /**< (SAMHS_HST_PIPIFR) Received STALLed Interrupt Set Mask */ +#define SAMHS_HST_PIPIFR_INTRPT_Msk _U_(0x44) /**< (SAMHS_HST_PIPIFR_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_PIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */ + +#define SAMHS_HST_PIPIMR_OFFSET (0x5C0) /**< (SAMHS_HST_PIPIMR) Host Pipe Mask Register Offset */ + +#define SAMHS_HST_PIPIMR_RXINE_Pos 0 /**< (SAMHS_HST_PIPIMR) Received IN Data Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_RXINE (_U_(0x1) << SAMHS_HST_PIPIMR_RXINE_Pos) /**< (SAMHS_HST_PIPIMR) Received IN Data Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_TXOUTE_Pos 1 /**< (SAMHS_HST_PIPIMR) Transmitted OUT Data Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_TXOUTE (_U_(0x1) << SAMHS_HST_PIPIMR_TXOUTE_Pos) /**< (SAMHS_HST_PIPIMR) Transmitted OUT Data Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_PERRE_Pos 3 /**< (SAMHS_HST_PIPIMR) Pipe Error Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_PERRE (_U_(0x1) << SAMHS_HST_PIPIMR_PERRE_Pos) /**< (SAMHS_HST_PIPIMR) Pipe Error Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_NAKEDE_Pos 4 /**< (SAMHS_HST_PIPIMR) NAKed Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_NAKEDE (_U_(0x1) << SAMHS_HST_PIPIMR_NAKEDE_Pos) /**< (SAMHS_HST_PIPIMR) NAKed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_OVERFIE_Pos 5 /**< (SAMHS_HST_PIPIMR) Overflow Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_OVERFIE (_U_(0x1) << SAMHS_HST_PIPIMR_OVERFIE_Pos) /**< (SAMHS_HST_PIPIMR) Overflow Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_SHORTPACKETIE_Pos 7 /**< (SAMHS_HST_PIPIMR) Short Packet Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_SHORTPACKETIE (_U_(0x1) << SAMHS_HST_PIPIMR_SHORTPACKETIE_Pos) /**< (SAMHS_HST_PIPIMR) Short Packet Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_NBUSYBKE_Pos 12 /**< (SAMHS_HST_PIPIMR) Number of Busy Banks Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_NBUSYBKE (_U_(0x1) << SAMHS_HST_PIPIMR_NBUSYBKE_Pos) /**< (SAMHS_HST_PIPIMR) Number of Busy Banks Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_FIFOCON_Pos 14 /**< (SAMHS_HST_PIPIMR) FIFO Control Position */ +#define SAMHS_HST_PIPIMR_FIFOCON (_U_(0x1) << SAMHS_HST_PIPIMR_FIFOCON_Pos) /**< (SAMHS_HST_PIPIMR) FIFO Control Mask */ +#define SAMHS_HST_PIPIMR_PDISHDMA_Pos 16 /**< (SAMHS_HST_PIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ +#define SAMHS_HST_PIPIMR_PDISHDMA (_U_(0x1) << SAMHS_HST_PIPIMR_PDISHDMA_Pos) /**< (SAMHS_HST_PIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define SAMHS_HST_PIPIMR_PFREEZE_Pos 17 /**< (SAMHS_HST_PIPIMR) Pipe Freeze Position */ +#define SAMHS_HST_PIPIMR_PFREEZE (_U_(0x1) << SAMHS_HST_PIPIMR_PFREEZE_Pos) /**< (SAMHS_HST_PIPIMR) Pipe Freeze Mask */ +#define SAMHS_HST_PIPIMR_RSTDT_Pos 18 /**< (SAMHS_HST_PIPIMR) Reset Data Toggle Position */ +#define SAMHS_HST_PIPIMR_RSTDT (_U_(0x1) << SAMHS_HST_PIPIMR_RSTDT_Pos) /**< (SAMHS_HST_PIPIMR) Reset Data Toggle Mask */ +#define SAMHS_HST_PIPIMR_Msk _U_(0x750BB) /**< (SAMHS_HST_PIPIMR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_HST_PIPIMR_CTRL_TXSTPE_Pos 2 /**< (SAMHS_HST_PIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_CTRL_TXSTPE (_U_(0x1) << SAMHS_HST_PIPIMR_CTRL_TXSTPE_Pos) /**< (SAMHS_HST_PIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_CTRL_RXSTALLDE_Pos 6 /**< (SAMHS_HST_PIPIMR) Received STALLed Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_CTRL_RXSTALLDE (_U_(0x1) << SAMHS_HST_PIPIMR_CTRL_RXSTALLDE_Pos) /**< (SAMHS_HST_PIPIMR) Received STALLed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_CTRL_Msk _U_(0x44) /**< (SAMHS_HST_PIPIMR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_HST_PIPIMR_ISO_UNDERFIE_Pos 2 /**< (SAMHS_HST_PIPIMR) Underflow Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_ISO_UNDERFIE (_U_(0x1) << SAMHS_HST_PIPIMR_ISO_UNDERFIE_Pos) /**< (SAMHS_HST_PIPIMR) Underflow Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_ISO_CRCERRE_Pos 6 /**< (SAMHS_HST_PIPIMR) CRC Error Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_ISO_CRCERRE (_U_(0x1) << SAMHS_HST_PIPIMR_ISO_CRCERRE_Pos) /**< (SAMHS_HST_PIPIMR) CRC Error Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_ISO_Msk _U_(0x44) /**< (SAMHS_HST_PIPIMR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_HST_PIPIMR_BLK_TXSTPE_Pos 2 /**< (SAMHS_HST_PIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_BLK_TXSTPE (_U_(0x1) << SAMHS_HST_PIPIMR_BLK_TXSTPE_Pos) /**< (SAMHS_HST_PIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_BLK_RXSTALLDE_Pos 6 /**< (SAMHS_HST_PIPIMR) Received STALLed Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_BLK_RXSTALLDE (_U_(0x1) << SAMHS_HST_PIPIMR_BLK_RXSTALLDE_Pos) /**< (SAMHS_HST_PIPIMR) Received STALLed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_BLK_Msk _U_(0x44) /**< (SAMHS_HST_PIPIMR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_HST_PIPIMR_INTRPT_UNDERFIE_Pos 2 /**< (SAMHS_HST_PIPIMR) Underflow Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_INTRPT_UNDERFIE (_U_(0x1) << SAMHS_HST_PIPIMR_INTRPT_UNDERFIE_Pos) /**< (SAMHS_HST_PIPIMR) Underflow Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_INTRPT_RXSTALLDE_Pos 6 /**< (SAMHS_HST_PIPIMR) Received STALLed Interrupt Enable Position */ +#define SAMHS_HST_PIPIMR_INTRPT_RXSTALLDE (_U_(0x1) << SAMHS_HST_PIPIMR_INTRPT_RXSTALLDE_Pos) /**< (SAMHS_HST_PIPIMR) Received STALLed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIMR_INTRPT_Msk _U_(0x44) /**< (SAMHS_HST_PIPIMR_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_PIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */ + +#define SAMHS_HST_PIPIER_OFFSET (0x5F0) /**< (SAMHS_HST_PIPIER) Host Pipe Enable Register Offset */ + +#define SAMHS_HST_PIPIER_RXINES_Pos 0 /**< (SAMHS_HST_PIPIER) Received IN Data Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_RXINES (_U_(0x1) << SAMHS_HST_PIPIER_RXINES_Pos) /**< (SAMHS_HST_PIPIER) Received IN Data Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_TXOUTES_Pos 1 /**< (SAMHS_HST_PIPIER) Transmitted OUT Data Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_TXOUTES (_U_(0x1) << SAMHS_HST_PIPIER_TXOUTES_Pos) /**< (SAMHS_HST_PIPIER) Transmitted OUT Data Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_PERRES_Pos 3 /**< (SAMHS_HST_PIPIER) Pipe Error Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_PERRES (_U_(0x1) << SAMHS_HST_PIPIER_PERRES_Pos) /**< (SAMHS_HST_PIPIER) Pipe Error Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_NAKEDES_Pos 4 /**< (SAMHS_HST_PIPIER) NAKed Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_NAKEDES (_U_(0x1) << SAMHS_HST_PIPIER_NAKEDES_Pos) /**< (SAMHS_HST_PIPIER) NAKed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_OVERFIES_Pos 5 /**< (SAMHS_HST_PIPIER) Overflow Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_OVERFIES (_U_(0x1) << SAMHS_HST_PIPIER_OVERFIES_Pos) /**< (SAMHS_HST_PIPIER) Overflow Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_SHORTPACKETIES_Pos 7 /**< (SAMHS_HST_PIPIER) Short Packet Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_SHORTPACKETIES (_U_(0x1) << SAMHS_HST_PIPIER_SHORTPACKETIES_Pos) /**< (SAMHS_HST_PIPIER) Short Packet Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_NBUSYBKES_Pos 12 /**< (SAMHS_HST_PIPIER) Number of Busy Banks Enable Position */ +#define SAMHS_HST_PIPIER_NBUSYBKES (_U_(0x1) << SAMHS_HST_PIPIER_NBUSYBKES_Pos) /**< (SAMHS_HST_PIPIER) Number of Busy Banks Enable Mask */ +#define SAMHS_HST_PIPIER_PDISHDMAS_Pos 16 /**< (SAMHS_HST_PIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ +#define SAMHS_HST_PIPIER_PDISHDMAS (_U_(0x1) << SAMHS_HST_PIPIER_PDISHDMAS_Pos) /**< (SAMHS_HST_PIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define SAMHS_HST_PIPIER_PFREEZES_Pos 17 /**< (SAMHS_HST_PIPIER) Pipe Freeze Enable Position */ +#define SAMHS_HST_PIPIER_PFREEZES (_U_(0x1) << SAMHS_HST_PIPIER_PFREEZES_Pos) /**< (SAMHS_HST_PIPIER) Pipe Freeze Enable Mask */ +#define SAMHS_HST_PIPIER_RSTDTS_Pos 18 /**< (SAMHS_HST_PIPIER) Reset Data Toggle Enable Position */ +#define SAMHS_HST_PIPIER_RSTDTS (_U_(0x1) << SAMHS_HST_PIPIER_RSTDTS_Pos) /**< (SAMHS_HST_PIPIER) Reset Data Toggle Enable Mask */ +#define SAMHS_HST_PIPIER_Msk _U_(0x710BB) /**< (SAMHS_HST_PIPIER) Register Mask */ + +/* CTRL mode */ +#define SAMHS_HST_PIPIER_CTRL_TXSTPES_Pos 2 /**< (SAMHS_HST_PIPIER) Transmitted SETUP Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_CTRL_TXSTPES (_U_(0x1) << SAMHS_HST_PIPIER_CTRL_TXSTPES_Pos) /**< (SAMHS_HST_PIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_CTRL_RXSTALLDES_Pos 6 /**< (SAMHS_HST_PIPIER) Received STALLed Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_CTRL_RXSTALLDES (_U_(0x1) << SAMHS_HST_PIPIER_CTRL_RXSTALLDES_Pos) /**< (SAMHS_HST_PIPIER) Received STALLed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_CTRL_Msk _U_(0x44) /**< (SAMHS_HST_PIPIER_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_HST_PIPIER_ISO_UNDERFIES_Pos 2 /**< (SAMHS_HST_PIPIER) Underflow Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_ISO_UNDERFIES (_U_(0x1) << SAMHS_HST_PIPIER_ISO_UNDERFIES_Pos) /**< (SAMHS_HST_PIPIER) Underflow Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_ISO_CRCERRES_Pos 6 /**< (SAMHS_HST_PIPIER) CRC Error Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_ISO_CRCERRES (_U_(0x1) << SAMHS_HST_PIPIER_ISO_CRCERRES_Pos) /**< (SAMHS_HST_PIPIER) CRC Error Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_ISO_Msk _U_(0x44) /**< (SAMHS_HST_PIPIER_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_HST_PIPIER_BLK_TXSTPES_Pos 2 /**< (SAMHS_HST_PIPIER) Transmitted SETUP Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_BLK_TXSTPES (_U_(0x1) << SAMHS_HST_PIPIER_BLK_TXSTPES_Pos) /**< (SAMHS_HST_PIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_BLK_RXSTALLDES_Pos 6 /**< (SAMHS_HST_PIPIER) Received STALLed Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_BLK_RXSTALLDES (_U_(0x1) << SAMHS_HST_PIPIER_BLK_RXSTALLDES_Pos) /**< (SAMHS_HST_PIPIER) Received STALLed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_BLK_Msk _U_(0x44) /**< (SAMHS_HST_PIPIER_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_HST_PIPIER_INTRPT_UNDERFIES_Pos 2 /**< (SAMHS_HST_PIPIER) Underflow Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_INTRPT_UNDERFIES (_U_(0x1) << SAMHS_HST_PIPIER_INTRPT_UNDERFIES_Pos) /**< (SAMHS_HST_PIPIER) Underflow Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_INTRPT_RXSTALLDES_Pos 6 /**< (SAMHS_HST_PIPIER) Received STALLed Interrupt Enable Position */ +#define SAMHS_HST_PIPIER_INTRPT_RXSTALLDES (_U_(0x1) << SAMHS_HST_PIPIER_INTRPT_RXSTALLDES_Pos) /**< (SAMHS_HST_PIPIER) Received STALLed Interrupt Enable Mask */ +#define SAMHS_HST_PIPIER_INTRPT_Msk _U_(0x44) /**< (SAMHS_HST_PIPIER_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_PIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */ + +#define SAMHS_HST_PIPIDR_OFFSET (0x620) /**< (SAMHS_HST_PIPIDR) Host Pipe Disable Register Offset */ + +#define SAMHS_HST_PIPIDR_RXINEC_Pos 0 /**< (SAMHS_HST_PIPIDR) Received IN Data Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_RXINEC (_U_(0x1) << SAMHS_HST_PIPIDR_RXINEC_Pos) /**< (SAMHS_HST_PIPIDR) Received IN Data Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_TXOUTEC_Pos 1 /**< (SAMHS_HST_PIPIDR) Transmitted OUT Data Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_TXOUTEC (_U_(0x1) << SAMHS_HST_PIPIDR_TXOUTEC_Pos) /**< (SAMHS_HST_PIPIDR) Transmitted OUT Data Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_PERREC_Pos 3 /**< (SAMHS_HST_PIPIDR) Pipe Error Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_PERREC (_U_(0x1) << SAMHS_HST_PIPIDR_PERREC_Pos) /**< (SAMHS_HST_PIPIDR) Pipe Error Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_NAKEDEC_Pos 4 /**< (SAMHS_HST_PIPIDR) NAKed Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_NAKEDEC (_U_(0x1) << SAMHS_HST_PIPIDR_NAKEDEC_Pos) /**< (SAMHS_HST_PIPIDR) NAKed Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_OVERFIEC_Pos 5 /**< (SAMHS_HST_PIPIDR) Overflow Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_OVERFIEC (_U_(0x1) << SAMHS_HST_PIPIDR_OVERFIEC_Pos) /**< (SAMHS_HST_PIPIDR) Overflow Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_SHORTPACKETIEC_Pos 7 /**< (SAMHS_HST_PIPIDR) Short Packet Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_SHORTPACKETIEC (_U_(0x1) << SAMHS_HST_PIPIDR_SHORTPACKETIEC_Pos) /**< (SAMHS_HST_PIPIDR) Short Packet Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_NBUSYBKEC_Pos 12 /**< (SAMHS_HST_PIPIDR) Number of Busy Banks Disable Position */ +#define SAMHS_HST_PIPIDR_NBUSYBKEC (_U_(0x1) << SAMHS_HST_PIPIDR_NBUSYBKEC_Pos) /**< (SAMHS_HST_PIPIDR) Number of Busy Banks Disable Mask */ +#define SAMHS_HST_PIPIDR_FIFOCONC_Pos 14 /**< (SAMHS_HST_PIPIDR) FIFO Control Disable Position */ +#define SAMHS_HST_PIPIDR_FIFOCONC (_U_(0x1) << SAMHS_HST_PIPIDR_FIFOCONC_Pos) /**< (SAMHS_HST_PIPIDR) FIFO Control Disable Mask */ +#define SAMHS_HST_PIPIDR_PDISHDMAC_Pos 16 /**< (SAMHS_HST_PIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ +#define SAMHS_HST_PIPIDR_PDISHDMAC (_U_(0x1) << SAMHS_HST_PIPIDR_PDISHDMAC_Pos) /**< (SAMHS_HST_PIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ +#define SAMHS_HST_PIPIDR_PFREEZEC_Pos 17 /**< (SAMHS_HST_PIPIDR) Pipe Freeze Disable Position */ +#define SAMHS_HST_PIPIDR_PFREEZEC (_U_(0x1) << SAMHS_HST_PIPIDR_PFREEZEC_Pos) /**< (SAMHS_HST_PIPIDR) Pipe Freeze Disable Mask */ +#define SAMHS_HST_PIPIDR_Msk _U_(0x350BB) /**< (SAMHS_HST_PIPIDR) Register Mask */ + +/* CTRL mode */ +#define SAMHS_HST_PIPIDR_CTRL_TXSTPEC_Pos 2 /**< (SAMHS_HST_PIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_CTRL_TXSTPEC (_U_(0x1) << SAMHS_HST_PIPIDR_CTRL_TXSTPEC_Pos) /**< (SAMHS_HST_PIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_CTRL_RXSTALLDEC_Pos 6 /**< (SAMHS_HST_PIPIDR) Received STALLed Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_CTRL_RXSTALLDEC (_U_(0x1) << SAMHS_HST_PIPIDR_CTRL_RXSTALLDEC_Pos) /**< (SAMHS_HST_PIPIDR) Received STALLed Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_CTRL_Msk _U_(0x44) /**< (SAMHS_HST_PIPIDR_CTRL) Register Mask */ + +/* ISO mode */ +#define SAMHS_HST_PIPIDR_ISO_UNDERFIEC_Pos 2 /**< (SAMHS_HST_PIPIDR) Underflow Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_ISO_UNDERFIEC (_U_(0x1) << SAMHS_HST_PIPIDR_ISO_UNDERFIEC_Pos) /**< (SAMHS_HST_PIPIDR) Underflow Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_ISO_CRCERREC_Pos 6 /**< (SAMHS_HST_PIPIDR) CRC Error Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_ISO_CRCERREC (_U_(0x1) << SAMHS_HST_PIPIDR_ISO_CRCERREC_Pos) /**< (SAMHS_HST_PIPIDR) CRC Error Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_ISO_Msk _U_(0x44) /**< (SAMHS_HST_PIPIDR_ISO) Register Mask */ + +/* BLK mode */ +#define SAMHS_HST_PIPIDR_BLK_TXSTPEC_Pos 2 /**< (SAMHS_HST_PIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_BLK_TXSTPEC (_U_(0x1) << SAMHS_HST_PIPIDR_BLK_TXSTPEC_Pos) /**< (SAMHS_HST_PIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_BLK_RXSTALLDEC_Pos 6 /**< (SAMHS_HST_PIPIDR) Received STALLed Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_BLK_RXSTALLDEC (_U_(0x1) << SAMHS_HST_PIPIDR_BLK_RXSTALLDEC_Pos) /**< (SAMHS_HST_PIPIDR) Received STALLed Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_BLK_Msk _U_(0x44) /**< (SAMHS_HST_PIPIDR_BLK) Register Mask */ + +/* INTRPT mode */ +#define SAMHS_HST_PIPIDR_INTRPT_UNDERFIEC_Pos 2 /**< (SAMHS_HST_PIPIDR) Underflow Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_INTRPT_UNDERFIEC (_U_(0x1) << SAMHS_HST_PIPIDR_INTRPT_UNDERFIEC_Pos) /**< (SAMHS_HST_PIPIDR) Underflow Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_INTRPT_RXSTALLDEC_Pos 6 /**< (SAMHS_HST_PIPIDR) Received STALLed Interrupt Disable Position */ +#define SAMHS_HST_PIPIDR_INTRPT_RXSTALLDEC (_U_(0x1) << SAMHS_HST_PIPIDR_INTRPT_RXSTALLDEC_Pos) /**< (SAMHS_HST_PIPIDR) Received STALLed Interrupt Disable Mask */ +#define SAMHS_HST_PIPIDR_INTRPT_Msk _U_(0x44) /**< (SAMHS_HST_PIPIDR_INTRPT) Register Mask */ + + +/* -------- SAMHS_HST_PIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */ + +#define SAMHS_HST_PIPINRQ_OFFSET (0x650) /**< (SAMHS_HST_PIPINRQ) Host Pipe IN Request Register Offset */ + +#define SAMHS_HST_PIPINRQ_INRQ_Pos 0 /**< (SAMHS_HST_PIPINRQ) IN Request Number before Freeze Position */ +#define SAMHS_HST_PIPINRQ_INRQ (_U_(0xFF) << SAMHS_HST_PIPINRQ_INRQ_Pos) /**< (SAMHS_HST_PIPINRQ) IN Request Number before Freeze Mask */ +#define SAMHS_HST_PIPINRQ_INMODE_Pos 8 /**< (SAMHS_HST_PIPINRQ) IN Request Mode Position */ +#define SAMHS_HST_PIPINRQ_INMODE (_U_(0x1) << SAMHS_HST_PIPINRQ_INMODE_Pos) /**< (SAMHS_HST_PIPINRQ) IN Request Mode Mask */ +#define SAMHS_HST_PIPINRQ_Msk _U_(0x1FF) /**< (SAMHS_HST_PIPINRQ) Register Mask */ + + +/* -------- SAMHS_HST_PIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */ + +#define SAMHS_HST_PIPERR_OFFSET (0x680) /**< (SAMHS_HST_PIPERR) Host Pipe Error Register Offset */ + +#define SAMHS_HST_PIPERR_DATATGL_Pos 0 /**< (SAMHS_HST_PIPERR) Data Toggle Error Position */ +#define SAMHS_HST_PIPERR_DATATGL (_U_(0x1) << SAMHS_HST_PIPERR_DATATGL_Pos) /**< (SAMHS_HST_PIPERR) Data Toggle Error Mask */ +#define SAMHS_HST_PIPERR_DATAPID_Pos 1 /**< (SAMHS_HST_PIPERR) Data PID Error Position */ +#define SAMHS_HST_PIPERR_DATAPID (_U_(0x1) << SAMHS_HST_PIPERR_DATAPID_Pos) /**< (SAMHS_HST_PIPERR) Data PID Error Mask */ +#define SAMHS_HST_PIPERR_PID_Pos 2 /**< (SAMHS_HST_PIPERR) Data PID Error Position */ +#define SAMHS_HST_PIPERR_PID (_U_(0x1) << SAMHS_HST_PIPERR_PID_Pos) /**< (SAMHS_HST_PIPERR) Data PID Error Mask */ +#define SAMHS_HST_PIPERR_TIMEOUT_Pos 3 /**< (SAMHS_HST_PIPERR) Time-Out Error Position */ +#define SAMHS_HST_PIPERR_TIMEOUT (_U_(0x1) << SAMHS_HST_PIPERR_TIMEOUT_Pos) /**< (SAMHS_HST_PIPERR) Time-Out Error Mask */ +#define SAMHS_HST_PIPERR_CRC16_Pos 4 /**< (SAMHS_HST_PIPERR) CRC16 Error Position */ +#define SAMHS_HST_PIPERR_CRC16 (_U_(0x1) << SAMHS_HST_PIPERR_CRC16_Pos) /**< (SAMHS_HST_PIPERR) CRC16 Error Mask */ +#define SAMHS_HST_PIPERR_COUNTER_Pos 5 /**< (SAMHS_HST_PIPERR) Error Counter Position */ +#define SAMHS_HST_PIPERR_COUNTER (_U_(0x3) << SAMHS_HST_PIPERR_COUNTER_Pos) /**< (SAMHS_HST_PIPERR) Error Counter Mask */ +#define SAMHS_HST_PIPERR_Msk _U_(0x7F) /**< (SAMHS_HST_PIPERR) Register Mask */ + +#define SAMHS_HST_PIPERR_CRC_Pos 4 /**< (SAMHS_HST_PIPERR Position) CRCx6 Error */ +#define SAMHS_HST_PIPERR_CRC (_U_(0x1) << SAMHS_HST_PIPERR_CRC_Pos) /**< (SAMHS_HST_PIPERR Mask) CRC */ + +/* -------- CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ + +#define CTRL_OFFSET (0x800) /**< (CTRL) General Control Register Offset */ + +#define CTRL_RDERRE_Pos 4 /**< (CTRL) Remote Device Connection Error Interrupt Enable Position */ +#define CTRL_RDERRE (_U_(0x1) << CTRL_RDERRE_Pos) /**< (CTRL) Remote Device Connection Error Interrupt Enable Mask */ +#define CTRL_VBUSHWC_Pos 8 /**< (CTRL) VBUS Hardware Control Position */ +#define CTRL_VBUSHWC (_U_(0x1) << CTRL_VBUSHWC_Pos) /**< (CTRL) VBUS Hardware Control Mask */ +#define CTRL_FRZCLK_Pos 14 /**< (CTRL) Freeze USB Clock Position */ +#define CTRL_FRZCLK (_U_(0x1) << CTRL_FRZCLK_Pos) /**< (CTRL) Freeze USB Clock Mask */ +#define CTRL_USBE_Pos 15 /**< (CTRL) USBHS Enable Position */ +#define CTRL_USBE (_U_(0x1) << CTRL_USBE_Pos) /**< (CTRL) USBHS Enable Mask */ +#define CTRL_UID_Pos 24 /**< (CTRL) UID Pin Enable Position */ +#define CTRL_UID (_U_(0x1) << CTRL_UID_Pos) /**< (CTRL) UID Pin Enable Mask */ +#define CTRL_UIMOD_Pos 25 /**< (CTRL) USBHS Mode Position */ +#define CTRL_UIMOD (_U_(0x1) << CTRL_UIMOD_Pos) /**< (CTRL) USBHS Mode Mask */ +#define CTRL_UIMOD_HOST_Val _U_(0x0) /**< (CTRL) The module is in USB Host mode. */ +#define CTRL_UIMOD_SAMHS_DEV_ICE_Val _U_(0x1) /**< (CTRL) The module is in USB Device mode. */ +#define CTRL_UIMOD_HOST (CTRL_UIMOD_HOST_Val << CTRL_UIMOD_Pos) /**< (CTRL) The module is in USB Host mode. Position */ +#define CTRL_UIMOD_SAMHS_DEV_ICE (CTRL_UIMOD_SAMHS_DEV_ICE_Val << CTRL_UIMOD_Pos) /**< (CTRL) The module is in USB Device mode. Position */ +#define CTRL_Msk _U_(0x300C110) /**< (CTRL) Register Mask */ + + +/* -------- SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */ + +#define SR_OFFSET (0x804) /**< (SR) General Status Register Offset */ + +#define SR_RDERRI_Pos 4 /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Position */ +#define SR_RDERRI (_U_(0x1) << SR_RDERRI_Pos) /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ +#define SR_SPEED_Pos 12 /**< (SR) Speed Status (Device mode only) Position */ +#define SR_SPEED (_U_(0x3) << SR_SPEED_Pos) /**< (SR) Speed Status (Device mode only) Mask */ +#define SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (SR) Full-Speed mode */ +#define SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (SR) High-Speed mode */ +#define SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (SR) Low-Speed mode */ +#define SR_SPEED_FULL_SPEED (SR_SPEED_FULL_SPEED_Val << SR_SPEED_Pos) /**< (SR) Full-Speed mode Position */ +#define SR_SPEED_HIGH_SPEED (SR_SPEED_HIGH_SPEED_Val << SR_SPEED_Pos) /**< (SR) High-Speed mode Position */ +#define SR_SPEED_LOW_SPEED (SR_SPEED_LOW_SPEED_Val << SR_SPEED_Pos) /**< (SR) Low-Speed mode Position */ +#define SR_CLKUSABLE_Pos 14 /**< (SR) UTMI Clock Usable Position */ +#define SR_CLKUSABLE (_U_(0x1) << SR_CLKUSABLE_Pos) /**< (SR) UTMI Clock Usable Mask */ +#define SR_Msk _U_(0x7010) /**< (SR) Register Mask */ + + +/* -------- SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */ + +#define SCR_OFFSET (0x808) /**< (SCR) General Status Clear Register Offset */ + +#define SCR_RDERRIC_Pos 4 /**< (SCR) Remote Device Connection Error Interrupt Clear Position */ +#define SCR_RDERRIC (_U_(0x1) << SCR_RDERRIC_Pos) /**< (SCR) Remote Device Connection Error Interrupt Clear Mask */ +#define SCR_Msk _U_(0x10) /**< (SCR) Register Mask */ + + +/* -------- SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */ + +#define SFR_OFFSET (0x80C) /**< (SFR) General Status Set Register Offset */ + +#define SFR_RDERRIS_Pos 4 /**< (SFR) Remote Device Connection Error Interrupt Set Position */ +#define SFR_RDERRIS (_U_(0x1) << SFR_RDERRIS_Pos) /**< (SFR) Remote Device Connection Error Interrupt Set Mask */ +#define SFR_VBUSRQS_Pos 9 /**< (SFR) VBUS Request Set Position */ +#define SFR_VBUSRQS (_U_(0x1) << SFR_VBUSRQS_Pos) /**< (SFR) VBUS Request Set Mask */ +#define SFR_Msk _U_(0x210) /**< (SFR) Register Mask */ + + +/** \brief SAMHS_DEV_DMA hardware registers */ +typedef struct +{ + __IO uint32_t SAMHS_DEV_DMANXTDSC; /**< (SAMHS_DEV_DMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t SAMHS_DEV_DMAADDRESS; /**< (SAMHS_DEV_DMA Offset: 0x04) Device DMA Channel Address Register */ + __IO uint32_t SAMHS_DEV_DMACONTROL; /**< (SAMHS_DEV_DMA Offset: 0x08) Device DMA Channel Control Register */ + __IO uint32_t SAMHS_DEV_DMASTATUS; /**< (SAMHS_DEV_DMA Offset: 0x0C) Device DMA Channel Status Register */ +} samhs_dev_dma_t; + +/** \brief SAMHS_HST_DMA hardware registers */ +typedef struct +{ + __IO uint32_t SAMHS_HST_DMANXTDSC; /**< (SAMHS_HST_DMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t SAMHS_HST_DMAADDRESS; /**< (SAMHS_HST_DMA Offset: 0x04) Host DMA Channel Address Register */ + __IO uint32_t SAMHS_HST_DMACONTROL; /**< (SAMHS_HST_DMA Offset: 0x08) Host DMA Channel Control Register */ + __IO uint32_t SAMHS_HST_DMASTATUS; /**< (SAMHS_HST_DMA Offset: 0x0C) Host DMA Channel Status Register */ +} samhs_hst_dma_t; + +/** \brief USBHS hardware registers */ +typedef struct +{ + __IO uint32_t SAMHS_DEV_CTRL; /**< (USBHS Offset: 0x00) Device General Control Register */ + __I uint32_t SAMHS_DEV_ISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */ + __O uint32_t SAMHS_DEV_ICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */ + __O uint32_t SAMHS_DEV_IFR; /**< (USBHS Offset: 0x0C) Device Global Interrupt Set Register */ + __I uint32_t SAMHS_DEV_IMR; /**< (USBHS Offset: 0x10) Device Global Interrupt Mask Register */ + __O uint32_t SAMHS_DEV_IDR; /**< (USBHS Offset: 0x14) Device Global Interrupt Disable Register */ + __O uint32_t SAMHS_DEV_IER; /**< (USBHS Offset: 0x18) Device Global Interrupt Enable Register */ + __IO uint32_t SAMHS_DEV_EPT; /**< (USBHS Offset: 0x1C) Device Endpoint Register */ + __I uint32_t SAMHS_DEV_FNUM; /**< (USBHS Offset: 0x20) Device Frame Number Register */ + __I uint8_t Reserved1[220]; + __IO uint32_t SAMHS_DEV_EPTCFG[10]; /**< (USBHS Offset: 0x100) Device Endpoint Configuration Register */ + __I uint8_t Reserved2[8]; + __I uint32_t SAMHS_DEV_EPTISR[10]; /**< (USBHS Offset: 0x130) Device Endpoint Interrupt Status Register */ + __I uint8_t Reserved3[8]; + __O uint32_t SAMHS_DEV_EPTICR[10]; /**< (USBHS Offset: 0x160) Device Endpoint Interrupt Clear Register */ + __I uint8_t Reserved4[8]; + __O uint32_t SAMHS_DEV_EPTIFR[10]; /**< (USBHS Offset: 0x190) Device Endpoint Interrupt Set Register */ + __I uint8_t Reserved5[8]; + __I uint32_t SAMHS_DEV_EPTIMR[10]; /**< (USBHS Offset: 0x1C0) Device Endpoint Interrupt Mask Register */ + __I uint8_t Reserved6[8]; + __O uint32_t SAMHS_DEV_EPTIER[10]; /**< (USBHS Offset: 0x1F0) Device Endpoint Interrupt Enable Register */ + __I uint8_t Reserved7[8]; + __O uint32_t SAMHS_DEV_EPTIDR[10]; /**< (USBHS Offset: 0x220) Device Endpoint Interrupt Disable Register */ + __I uint8_t Reserved8[200]; + samhs_dev_dma_t SAMHS_DEV_DMA[7]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved9[128]; + __IO uint32_t SAMHS_HST_CTRL; /**< (USBHS Offset: 0x400) Host General Control Register */ + __I uint32_t SAMHS_HST_ISR; /**< (USBHS Offset: 0x404) Host Global Interrupt Status Register */ + __O uint32_t SAMHS_HST_ICR; /**< (USBHS Offset: 0x408) Host Global Interrupt Clear Register */ + __O uint32_t SAMHS_HST_IFR; /**< (USBHS Offset: 0x40C) Host Global Interrupt Set Register */ + __I uint32_t SAMHS_HST_IMR; /**< (USBHS Offset: 0x410) Host Global Interrupt Mask Register */ + __O uint32_t SAMHS_HST_IDR; /**< (USBHS Offset: 0x414) Host Global Interrupt Disable Register */ + __O uint32_t SAMHS_HST_IER; /**< (USBHS Offset: 0x418) Host Global Interrupt Enable Register */ + __IO uint32_t SAMHS_HST_PIP; /**< (USBHS Offset: 0x41C) Host Pipe Register */ + __IO uint32_t SAMHS_HST_FNUM; /**< (USBHS Offset: 0x420) Host Frame Number Register */ + __IO uint32_t SAMHS_HST_ADDR1; /**< (USBHS Offset: 0x424) Host Address 1 Register */ + __IO uint32_t SAMHS_HST_ADDR2; /**< (USBHS Offset: 0x428) Host Address 2 Register */ + __IO uint32_t SAMHS_HST_ADDR3; /**< (USBHS Offset: 0x42C) Host Address 3 Register */ + __I uint8_t Reserved10[208]; + __IO uint32_t SAMHS_HST_PIPCFG[10]; /**< (USBHS Offset: 0x500) Host Pipe Configuration Register */ + __I uint8_t Reserved11[8]; + __I uint32_t SAMHS_HST_PIPISR[10]; /**< (USBHS Offset: 0x530) Host Pipe Status Register */ + __I uint8_t Reserved12[8]; + __O uint32_t SAMHS_HST_PIPICR[10]; /**< (USBHS Offset: 0x560) Host Pipe Clear Register */ + __I uint8_t Reserved13[8]; + __O uint32_t SAMHS_HST_PIPIFR[10]; /**< (USBHS Offset: 0x590) Host Pipe Set Register */ + __I uint8_t Reserved14[8]; + __I uint32_t SAMHS_HST_PIPIMR[10]; /**< (USBHS Offset: 0x5C0) Host Pipe Mask Register */ + __I uint8_t Reserved15[8]; + __O uint32_t SAMHS_HST_PIPIER[10]; /**< (USBHS Offset: 0x5F0) Host Pipe Enable Register */ + __I uint8_t Reserved16[8]; + __O uint32_t SAMHS_HST_PIPIDR[10]; /**< (USBHS Offset: 0x620) Host Pipe Disable Register */ + __I uint8_t Reserved17[8]; + __IO uint32_t SAMHS_HST_PIPINRQ[10]; /**< (USBHS Offset: 0x650) Host Pipe IN Request Register */ + __I uint8_t Reserved18[8]; + __IO uint32_t SAMHS_HST_PIPERR[10]; /**< (USBHS Offset: 0x680) Host Pipe Error Register */ + __I uint8_t Reserved19[104]; + samhs_hst_dma_t SAMHS_HST_DMA[7]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved20[128]; + __IO uint32_t SAMHS_CTRL; /**< (USBHS Offset: 0x800) General Control Register */ + __I uint32_t SAMHS_SR; /**< (USBHS Offset: 0x804) General Status Register */ + __O uint32_t SAMHS_SCR; /**< (USBHS Offset: 0x808) General Status Clear Register */ + __O uint32_t SAMHS_SFR; /**< (USBHS Offset: 0x80C) General Status Set Register */ +} samhs_reg_t; + +#define SAMHS_BASE_REG (0x40038000U) /**< \brief (USBHS) Base Address */ + +#define EP_MAX 10 + +#define FIFO_RAM_ADDR (0xA0100000U) + +// Errata: The DMA feature is not available for Pipe/Endpoint 7 +#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6) + +#endif /* _SAMHS_SAMX7X_H_ */ diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/common_usb_regs.h deleted file mode 100644 index d232f0bcba..0000000000 --- a/src/portable/microchip/samx7x/common_usb_regs.h +++ /dev/null @@ -1,2108 +0,0 @@ - /* -* The MIT License (MIT) -* -* Copyright (c) 2019 Microchip Technology Inc. -* Copyright (c) 2018, hathach (tinyusb.org) -* Copyright (c) 2021, HiFiPhile -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -* THE SOFTWARE. -* -* This file is part of the TinyUSB stack. -*/ - -#ifndef _COMMON_USB_REGS_H_ -#define _COMMON_USB_REGS_H_ - -#if CFG_TUSB_MCU == OPT_MCU_SAMX7X - -/* -------- DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */ - -#define DEVDMANXTDSC_OFFSET (0x00) /**< (DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register Offset */ - -#define DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (DEVDMANXTDSC) Next Descriptor Address Position */ -#define DEVDMANXTDSC_NXT_DSC_ADD (_U_(0xFFFFFFFF) << DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< (DEVDMANXTDSC) Next Descriptor Address Mask */ -#define DEVDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (DEVDMANXTDSC) Register Mask */ - - -/* -------- DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */ - -#define DEVDMAADDRESS_OFFSET (0x04) /**< (DEVDMAADDRESS) Device DMA Channel Address Register Offset */ - -#define DEVDMAADDRESS_BUFF_ADD_Pos 0 /**< (DEVDMAADDRESS) Buffer Address Position */ -#define DEVDMAADDRESS_BUFF_ADD (_U_(0xFFFFFFFF) << DEVDMAADDRESS_BUFF_ADD_Pos) /**< (DEVDMAADDRESS) Buffer Address Mask */ -#define DEVDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (DEVDMAADDRESS) Register Mask */ - - -/* -------- DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */ - -#define DEVDMACONTROL_OFFSET (0x08) /**< (DEVDMACONTROL) Device DMA Channel Control Register Offset */ - -#define DEVDMACONTROL_CHANN_ENB_Pos 0 /**< (DEVDMACONTROL) Channel Enable Command Position */ -#define DEVDMACONTROL_CHANN_ENB (_U_(0x1) << DEVDMACONTROL_CHANN_ENB_Pos) /**< (DEVDMACONTROL) Channel Enable Command Mask */ -#define DEVDMACONTROL_LDNXT_DSC_Pos 1 /**< (DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ -#define DEVDMACONTROL_LDNXT_DSC (_U_(0x1) << DEVDMACONTROL_LDNXT_DSC_Pos) /**< (DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ -#define DEVDMACONTROL_END_TR_EN_Pos 2 /**< (DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ -#define DEVDMACONTROL_END_TR_EN (_U_(0x1) << DEVDMACONTROL_END_TR_EN_Pos) /**< (DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ -#define DEVDMACONTROL_END_B_EN_Pos 3 /**< (DEVDMACONTROL) End of Buffer Enable Control Position */ -#define DEVDMACONTROL_END_B_EN (_U_(0x1) << DEVDMACONTROL_END_B_EN_Pos) /**< (DEVDMACONTROL) End of Buffer Enable Control Mask */ -#define DEVDMACONTROL_END_TR_IT_Pos 4 /**< (DEVDMACONTROL) End of Transfer Interrupt Enable Position */ -#define DEVDMACONTROL_END_TR_IT (_U_(0x1) << DEVDMACONTROL_END_TR_IT_Pos) /**< (DEVDMACONTROL) End of Transfer Interrupt Enable Mask */ -#define DEVDMACONTROL_END_BUFFIT_Pos 5 /**< (DEVDMACONTROL) End of Buffer Interrupt Enable Position */ -#define DEVDMACONTROL_END_BUFFIT (_U_(0x1) << DEVDMACONTROL_END_BUFFIT_Pos) /**< (DEVDMACONTROL) End of Buffer Interrupt Enable Mask */ -#define DEVDMACONTROL_DESC_LD_IT_Pos 6 /**< (DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */ -#define DEVDMACONTROL_DESC_LD_IT (_U_(0x1) << DEVDMACONTROL_DESC_LD_IT_Pos) /**< (DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ -#define DEVDMACONTROL_BURST_LCK_Pos 7 /**< (DEVDMACONTROL) Burst Lock Enable Position */ -#define DEVDMACONTROL_BURST_LCK (_U_(0x1) << DEVDMACONTROL_BURST_LCK_Pos) /**< (DEVDMACONTROL) Burst Lock Enable Mask */ -#define DEVDMACONTROL_BUFF_LENGTH_Pos 16 /**< (DEVDMACONTROL) Buffer Byte Length (Write-only) Position */ -#define DEVDMACONTROL_BUFF_LENGTH (_U_(0xFFFF) << DEVDMACONTROL_BUFF_LENGTH_Pos) /**< (DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */ -#define DEVDMACONTROL_Msk _U_(0xFFFF00FF) /**< (DEVDMACONTROL) Register Mask */ - - -/* -------- DEVDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */ - -#define DEVDMASTATUS_OFFSET (0x0C) /**< (DEVDMASTATUS) Device DMA Channel Status Register Offset */ - -#define DEVDMASTATUS_CHANN_ENB_Pos 0 /**< (DEVDMASTATUS) Channel Enable Status Position */ -#define DEVDMASTATUS_CHANN_ENB (_U_(0x1) << DEVDMASTATUS_CHANN_ENB_Pos) /**< (DEVDMASTATUS) Channel Enable Status Mask */ -#define DEVDMASTATUS_CHANN_ACT_Pos 1 /**< (DEVDMASTATUS) Channel Active Status Position */ -#define DEVDMASTATUS_CHANN_ACT (_U_(0x1) << DEVDMASTATUS_CHANN_ACT_Pos) /**< (DEVDMASTATUS) Channel Active Status Mask */ -#define DEVDMASTATUS_END_TR_ST_Pos 4 /**< (DEVDMASTATUS) End of Channel Transfer Status Position */ -#define DEVDMASTATUS_END_TR_ST (_U_(0x1) << DEVDMASTATUS_END_TR_ST_Pos) /**< (DEVDMASTATUS) End of Channel Transfer Status Mask */ -#define DEVDMASTATUS_END_BF_ST_Pos 5 /**< (DEVDMASTATUS) End of Channel Buffer Status Position */ -#define DEVDMASTATUS_END_BF_ST (_U_(0x1) << DEVDMASTATUS_END_BF_ST_Pos) /**< (DEVDMASTATUS) End of Channel Buffer Status Mask */ -#define DEVDMASTATUS_DESC_LDST_Pos 6 /**< (DEVDMASTATUS) Descriptor Loaded Status Position */ -#define DEVDMASTATUS_DESC_LDST (_U_(0x1) << DEVDMASTATUS_DESC_LDST_Pos) /**< (DEVDMASTATUS) Descriptor Loaded Status Mask */ -#define DEVDMASTATUS_BUFF_COUNT_Pos 16 /**< (DEVDMASTATUS) Buffer Byte Count Position */ -#define DEVDMASTATUS_BUFF_COUNT (_U_(0xFFFF) << DEVDMASTATUS_BUFF_COUNT_Pos) /**< (DEVDMASTATUS) Buffer Byte Count Mask */ -#define DEVDMASTATUS_Msk _U_(0xFFFF0073) /**< (DEVDMASTATUS) Register Mask */ - - -/* -------- HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */ - -#define HSTDMANXTDSC_OFFSET (0x00) /**< (HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register Offset */ - -#define HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (HSTDMANXTDSC) Next Descriptor Address Position */ -#define HSTDMANXTDSC_NXT_DSC_ADD (_U_(0xFFFFFFFF) << HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< (HSTDMANXTDSC) Next Descriptor Address Mask */ -#define HSTDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (HSTDMANXTDSC) Register Mask */ - - -/* -------- HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */ - -#define HSTDMAADDRESS_OFFSET (0x04) /**< (HSTDMAADDRESS) Host DMA Channel Address Register Offset */ - -#define HSTDMAADDRESS_BUFF_ADD_Pos 0 /**< (HSTDMAADDRESS) Buffer Address Position */ -#define HSTDMAADDRESS_BUFF_ADD (_U_(0xFFFFFFFF) << HSTDMAADDRESS_BUFF_ADD_Pos) /**< (HSTDMAADDRESS) Buffer Address Mask */ -#define HSTDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (HSTDMAADDRESS) Register Mask */ - - -/* -------- HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */ - -#define HSTDMACONTROL_OFFSET (0x08) /**< (HSTDMACONTROL) Host DMA Channel Control Register Offset */ - -#define HSTDMACONTROL_CHANN_ENB_Pos 0 /**< (HSTDMACONTROL) Channel Enable Command Position */ -#define HSTDMACONTROL_CHANN_ENB (_U_(0x1) << HSTDMACONTROL_CHANN_ENB_Pos) /**< (HSTDMACONTROL) Channel Enable Command Mask */ -#define HSTDMACONTROL_LDNXT_DSC_Pos 1 /**< (HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ -#define HSTDMACONTROL_LDNXT_DSC (_U_(0x1) << HSTDMACONTROL_LDNXT_DSC_Pos) /**< (HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ -#define HSTDMACONTROL_END_TR_EN_Pos 2 /**< (HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ -#define HSTDMACONTROL_END_TR_EN (_U_(0x1) << HSTDMACONTROL_END_TR_EN_Pos) /**< (HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ -#define HSTDMACONTROL_END_B_EN_Pos 3 /**< (HSTDMACONTROL) End of Buffer Enable Control Position */ -#define HSTDMACONTROL_END_B_EN (_U_(0x1) << HSTDMACONTROL_END_B_EN_Pos) /**< (HSTDMACONTROL) End of Buffer Enable Control Mask */ -#define HSTDMACONTROL_END_TR_IT_Pos 4 /**< (HSTDMACONTROL) End of Transfer Interrupt Enable Position */ -#define HSTDMACONTROL_END_TR_IT (_U_(0x1) << HSTDMACONTROL_END_TR_IT_Pos) /**< (HSTDMACONTROL) End of Transfer Interrupt Enable Mask */ -#define HSTDMACONTROL_END_BUFFIT_Pos 5 /**< (HSTDMACONTROL) End of Buffer Interrupt Enable Position */ -#define HSTDMACONTROL_END_BUFFIT (_U_(0x1) << HSTDMACONTROL_END_BUFFIT_Pos) /**< (HSTDMACONTROL) End of Buffer Interrupt Enable Mask */ -#define HSTDMACONTROL_DESC_LD_IT_Pos 6 /**< (HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */ -#define HSTDMACONTROL_DESC_LD_IT (_U_(0x1) << HSTDMACONTROL_DESC_LD_IT_Pos) /**< (HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ -#define HSTDMACONTROL_BURST_LCK_Pos 7 /**< (HSTDMACONTROL) Burst Lock Enable Position */ -#define HSTDMACONTROL_BURST_LCK (_U_(0x1) << HSTDMACONTROL_BURST_LCK_Pos) /**< (HSTDMACONTROL) Burst Lock Enable Mask */ -#define HSTDMACONTROL_BUFF_LENGTH_Pos 16 /**< (HSTDMACONTROL) Buffer Byte Length (Write-only) Position */ -#define HSTDMACONTROL_BUFF_LENGTH (_U_(0xFFFF) << HSTDMACONTROL_BUFF_LENGTH_Pos) /**< (HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */ -#define HSTDMACONTROL_Msk _U_(0xFFFF00FF) /**< (HSTDMACONTROL) Register Mask */ - - -/* -------- HSTDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */ - -#define HSTDMASTATUS_OFFSET (0x0C) /**< (HSTDMASTATUS) Host DMA Channel Status Register Offset */ - -#define HSTDMASTATUS_CHANN_ENB_Pos 0 /**< (HSTDMASTATUS) Channel Enable Status Position */ -#define HSTDMASTATUS_CHANN_ENB (_U_(0x1) << HSTDMASTATUS_CHANN_ENB_Pos) /**< (HSTDMASTATUS) Channel Enable Status Mask */ -#define HSTDMASTATUS_CHANN_ACT_Pos 1 /**< (HSTDMASTATUS) Channel Active Status Position */ -#define HSTDMASTATUS_CHANN_ACT (_U_(0x1) << HSTDMASTATUS_CHANN_ACT_Pos) /**< (HSTDMASTATUS) Channel Active Status Mask */ -#define HSTDMASTATUS_END_TR_ST_Pos 4 /**< (HSTDMASTATUS) End of Channel Transfer Status Position */ -#define HSTDMASTATUS_END_TR_ST (_U_(0x1) << HSTDMASTATUS_END_TR_ST_Pos) /**< (HSTDMASTATUS) End of Channel Transfer Status Mask */ -#define HSTDMASTATUS_END_BF_ST_Pos 5 /**< (HSTDMASTATUS) End of Channel Buffer Status Position */ -#define HSTDMASTATUS_END_BF_ST (_U_(0x1) << HSTDMASTATUS_END_BF_ST_Pos) /**< (HSTDMASTATUS) End of Channel Buffer Status Mask */ -#define HSTDMASTATUS_DESC_LDST_Pos 6 /**< (HSTDMASTATUS) Descriptor Loaded Status Position */ -#define HSTDMASTATUS_DESC_LDST (_U_(0x1) << HSTDMASTATUS_DESC_LDST_Pos) /**< (HSTDMASTATUS) Descriptor Loaded Status Mask */ -#define HSTDMASTATUS_BUFF_COUNT_Pos 16 /**< (HSTDMASTATUS) Buffer Byte Count Position */ -#define HSTDMASTATUS_BUFF_COUNT (_U_(0xFFFF) << HSTDMASTATUS_BUFF_COUNT_Pos) /**< (HSTDMASTATUS) Buffer Byte Count Mask */ -#define HSTDMASTATUS_Msk _U_(0xFFFF0073) /**< (HSTDMASTATUS) Register Mask */ - - -/* -------- DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ - -#define DEVCTRL_OFFSET (0x00) /**< (DEVCTRL) Device General Control Register Offset */ - -#define DEVCTRL_UADD_Pos 0 /**< (DEVCTRL) USB Address Position */ -#define DEVCTRL_UADD (_U_(0x7F) << DEVCTRL_UADD_Pos) /**< (DEVCTRL) USB Address Mask */ -#define DEVCTRL_ADDEN_Pos 7 /**< (DEVCTRL) Address Enable Position */ -#define DEVCTRL_ADDEN (_U_(0x1) << DEVCTRL_ADDEN_Pos) /**< (DEVCTRL) Address Enable Mask */ -#define DEVCTRL_DETACH_Pos 8 /**< (DEVCTRL) Detach Position */ -#define DEVCTRL_DETACH (_U_(0x1) << DEVCTRL_DETACH_Pos) /**< (DEVCTRL) Detach Mask */ -#define DEVCTRL_RMWKUP_Pos 9 /**< (DEVCTRL) Remote Wake-Up Position */ -#define DEVCTRL_RMWKUP (_U_(0x1) << DEVCTRL_RMWKUP_Pos) /**< (DEVCTRL) Remote Wake-Up Mask */ -#define DEVCTRL_SPDCONF_Pos 10 /**< (DEVCTRL) Mode Configuration Position */ -#define DEVCTRL_SPDCONF (_U_(0x3) << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) Mode Configuration Mask */ -#define DEVCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ -#define DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (DEVCTRL) For a better consumption, if high speed is not needed. */ -#define DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (DEVCTRL) Forced high speed. */ -#define DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ -#define DEVCTRL_SPDCONF_NORMAL (DEVCTRL_SPDCONF_NORMAL_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ -#define DEVCTRL_SPDCONF_LOW_POWER (DEVCTRL_SPDCONF_LOW_POWER_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) For a better consumption, if high speed is not needed. Position */ -#define DEVCTRL_SPDCONF_HIGH_SPEED (DEVCTRL_SPDCONF_HIGH_SPEED_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) Forced high speed. Position */ -#define DEVCTRL_SPDCONF_FORCED_FS (DEVCTRL_SPDCONF_FORCED_FS_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position */ -#define DEVCTRL_LS_Pos 12 /**< (DEVCTRL) Low-Speed Mode Force Position */ -#define DEVCTRL_LS (_U_(0x1) << DEVCTRL_LS_Pos) /**< (DEVCTRL) Low-Speed Mode Force Mask */ -#define DEVCTRL_TSTJ_Pos 13 /**< (DEVCTRL) Test mode J Position */ -#define DEVCTRL_TSTJ (_U_(0x1) << DEVCTRL_TSTJ_Pos) /**< (DEVCTRL) Test mode J Mask */ -#define DEVCTRL_TSTK_Pos 14 /**< (DEVCTRL) Test mode K Position */ -#define DEVCTRL_TSTK (_U_(0x1) << DEVCTRL_TSTK_Pos) /**< (DEVCTRL) Test mode K Mask */ -#define DEVCTRL_TSTPCKT_Pos 15 /**< (DEVCTRL) Test packet mode Position */ -#define DEVCTRL_TSTPCKT (_U_(0x1) << DEVCTRL_TSTPCKT_Pos) /**< (DEVCTRL) Test packet mode Mask */ -#define DEVCTRL_OPMODE2_Pos 16 /**< (DEVCTRL) Specific Operational mode Position */ -#define DEVCTRL_OPMODE2 (_U_(0x1) << DEVCTRL_OPMODE2_Pos) /**< (DEVCTRL) Specific Operational mode Mask */ -#define DEVCTRL_Msk _U_(0x1FFFF) /**< (DEVCTRL) Register Mask */ - -#define DEVCTRL_OPMODE_Pos 16 /**< (DEVCTRL Position) Specific Operational mode */ -#define DEVCTRL_OPMODE (_U_(0x1) << DEVCTRL_OPMODE_Pos) /**< (DEVCTRL Mask) OPMODE */ - -/* -------- DEVISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */ - -#define DEVISR_OFFSET (0x04) /**< (DEVISR) Device Global Interrupt Status Register Offset */ - -#define DEVISR_SUSP_Pos 0 /**< (DEVISR) Suspend Interrupt Position */ -#define DEVISR_SUSP (_U_(0x1) << DEVISR_SUSP_Pos) /**< (DEVISR) Suspend Interrupt Mask */ -#define DEVISR_MSOF_Pos 1 /**< (DEVISR) Micro Start of Frame Interrupt Position */ -#define DEVISR_MSOF (_U_(0x1) << DEVISR_MSOF_Pos) /**< (DEVISR) Micro Start of Frame Interrupt Mask */ -#define DEVISR_SOF_Pos 2 /**< (DEVISR) Start of Frame Interrupt Position */ -#define DEVISR_SOF (_U_(0x1) << DEVISR_SOF_Pos) /**< (DEVISR) Start of Frame Interrupt Mask */ -#define DEVISR_EORST_Pos 3 /**< (DEVISR) End of Reset Interrupt Position */ -#define DEVISR_EORST (_U_(0x1) << DEVISR_EORST_Pos) /**< (DEVISR) End of Reset Interrupt Mask */ -#define DEVISR_WAKEUP_Pos 4 /**< (DEVISR) Wake-Up Interrupt Position */ -#define DEVISR_WAKEUP (_U_(0x1) << DEVISR_WAKEUP_Pos) /**< (DEVISR) Wake-Up Interrupt Mask */ -#define DEVISR_EORSM_Pos 5 /**< (DEVISR) End of Resume Interrupt Position */ -#define DEVISR_EORSM (_U_(0x1) << DEVISR_EORSM_Pos) /**< (DEVISR) End of Resume Interrupt Mask */ -#define DEVISR_UPRSM_Pos 6 /**< (DEVISR) Upstream Resume Interrupt Position */ -#define DEVISR_UPRSM (_U_(0x1) << DEVISR_UPRSM_Pos) /**< (DEVISR) Upstream Resume Interrupt Mask */ -#define DEVISR_PEP_0_Pos 12 /**< (DEVISR) Endpoint 0 Interrupt Position */ -#define DEVISR_PEP_0 (_U_(0x1) << DEVISR_PEP_0_Pos) /**< (DEVISR) Endpoint 0 Interrupt Mask */ -#define DEVISR_PEP_1_Pos 13 /**< (DEVISR) Endpoint 1 Interrupt Position */ -#define DEVISR_PEP_1 (_U_(0x1) << DEVISR_PEP_1_Pos) /**< (DEVISR) Endpoint 1 Interrupt Mask */ -#define DEVISR_PEP_2_Pos 14 /**< (DEVISR) Endpoint 2 Interrupt Position */ -#define DEVISR_PEP_2 (_U_(0x1) << DEVISR_PEP_2_Pos) /**< (DEVISR) Endpoint 2 Interrupt Mask */ -#define DEVISR_PEP_3_Pos 15 /**< (DEVISR) Endpoint 3 Interrupt Position */ -#define DEVISR_PEP_3 (_U_(0x1) << DEVISR_PEP_3_Pos) /**< (DEVISR) Endpoint 3 Interrupt Mask */ -#define DEVISR_PEP_4_Pos 16 /**< (DEVISR) Endpoint 4 Interrupt Position */ -#define DEVISR_PEP_4 (_U_(0x1) << DEVISR_PEP_4_Pos) /**< (DEVISR) Endpoint 4 Interrupt Mask */ -#define DEVISR_PEP_5_Pos 17 /**< (DEVISR) Endpoint 5 Interrupt Position */ -#define DEVISR_PEP_5 (_U_(0x1) << DEVISR_PEP_5_Pos) /**< (DEVISR) Endpoint 5 Interrupt Mask */ -#define DEVISR_PEP_6_Pos 18 /**< (DEVISR) Endpoint 6 Interrupt Position */ -#define DEVISR_PEP_6 (_U_(0x1) << DEVISR_PEP_6_Pos) /**< (DEVISR) Endpoint 6 Interrupt Mask */ -#define DEVISR_PEP_7_Pos 19 /**< (DEVISR) Endpoint 7 Interrupt Position */ -#define DEVISR_PEP_7 (_U_(0x1) << DEVISR_PEP_7_Pos) /**< (DEVISR) Endpoint 7 Interrupt Mask */ -#define DEVISR_PEP_8_Pos 20 /**< (DEVISR) Endpoint 8 Interrupt Position */ -#define DEVISR_PEP_8 (_U_(0x1) << DEVISR_PEP_8_Pos) /**< (DEVISR) Endpoint 8 Interrupt Mask */ -#define DEVISR_PEP_9_Pos 21 /**< (DEVISR) Endpoint 9 Interrupt Position */ -#define DEVISR_PEP_9 (_U_(0x1) << DEVISR_PEP_9_Pos) /**< (DEVISR) Endpoint 9 Interrupt Mask */ -#define DEVISR_DMA_1_Pos 25 /**< (DEVISR) DMA Channel 1 Interrupt Position */ -#define DEVISR_DMA_1 (_U_(0x1) << DEVISR_DMA_1_Pos) /**< (DEVISR) DMA Channel 1 Interrupt Mask */ -#define DEVISR_DMA_2_Pos 26 /**< (DEVISR) DMA Channel 2 Interrupt Position */ -#define DEVISR_DMA_2 (_U_(0x1) << DEVISR_DMA_2_Pos) /**< (DEVISR) DMA Channel 2 Interrupt Mask */ -#define DEVISR_DMA_3_Pos 27 /**< (DEVISR) DMA Channel 3 Interrupt Position */ -#define DEVISR_DMA_3 (_U_(0x1) << DEVISR_DMA_3_Pos) /**< (DEVISR) DMA Channel 3 Interrupt Mask */ -#define DEVISR_DMA_4_Pos 28 /**< (DEVISR) DMA Channel 4 Interrupt Position */ -#define DEVISR_DMA_4 (_U_(0x1) << DEVISR_DMA_4_Pos) /**< (DEVISR) DMA Channel 4 Interrupt Mask */ -#define DEVISR_DMA_5_Pos 29 /**< (DEVISR) DMA Channel 5 Interrupt Position */ -#define DEVISR_DMA_5 (_U_(0x1) << DEVISR_DMA_5_Pos) /**< (DEVISR) DMA Channel 5 Interrupt Mask */ -#define DEVISR_DMA_6_Pos 30 /**< (DEVISR) DMA Channel 6 Interrupt Position */ -#define DEVISR_DMA_6 (_U_(0x1) << DEVISR_DMA_6_Pos) /**< (DEVISR) DMA Channel 6 Interrupt Mask */ -#define DEVISR_DMA_7_Pos 31 /**< (DEVISR) DMA Channel 7 Interrupt Position */ -#define DEVISR_DMA_7 (_U_(0x1) << DEVISR_DMA_7_Pos) /**< (DEVISR) DMA Channel 7 Interrupt Mask */ -#define DEVISR_Msk _U_(0xFE3FF07F) /**< (DEVISR) Register Mask */ - -#define DEVISR_PEP__Pos 12 /**< (DEVISR Position) Endpoint x Interrupt */ -#define DEVISR_PEP_ (_U_(0x3FF) << DEVISR_PEP__Pos) /**< (DEVISR Mask) PEP_ */ -#define DEVISR_DMA__Pos 25 /**< (DEVISR Position) DMA Channel 7 Interrupt */ -#define DEVISR_DMA_ (_U_(0x7F) << DEVISR_DMA__Pos) /**< (DEVISR Mask) DMA_ */ - -/* -------- DEVICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */ - -#define DEVICR_OFFSET (0x08) /**< (DEVICR) Device Global Interrupt Clear Register Offset */ - -#define DEVICR_SUSPC_Pos 0 /**< (DEVICR) Suspend Interrupt Clear Position */ -#define DEVICR_SUSPC (_U_(0x1) << DEVICR_SUSPC_Pos) /**< (DEVICR) Suspend Interrupt Clear Mask */ -#define DEVICR_MSOFC_Pos 1 /**< (DEVICR) Micro Start of Frame Interrupt Clear Position */ -#define DEVICR_MSOFC (_U_(0x1) << DEVICR_MSOFC_Pos) /**< (DEVICR) Micro Start of Frame Interrupt Clear Mask */ -#define DEVICR_SOFC_Pos 2 /**< (DEVICR) Start of Frame Interrupt Clear Position */ -#define DEVICR_SOFC (_U_(0x1) << DEVICR_SOFC_Pos) /**< (DEVICR) Start of Frame Interrupt Clear Mask */ -#define DEVICR_EORSTC_Pos 3 /**< (DEVICR) End of Reset Interrupt Clear Position */ -#define DEVICR_EORSTC (_U_(0x1) << DEVICR_EORSTC_Pos) /**< (DEVICR) End of Reset Interrupt Clear Mask */ -#define DEVICR_WAKEUPC_Pos 4 /**< (DEVICR) Wake-Up Interrupt Clear Position */ -#define DEVICR_WAKEUPC (_U_(0x1) << DEVICR_WAKEUPC_Pos) /**< (DEVICR) Wake-Up Interrupt Clear Mask */ -#define DEVICR_EORSMC_Pos 5 /**< (DEVICR) End of Resume Interrupt Clear Position */ -#define DEVICR_EORSMC (_U_(0x1) << DEVICR_EORSMC_Pos) /**< (DEVICR) End of Resume Interrupt Clear Mask */ -#define DEVICR_UPRSMC_Pos 6 /**< (DEVICR) Upstream Resume Interrupt Clear Position */ -#define DEVICR_UPRSMC (_U_(0x1) << DEVICR_UPRSMC_Pos) /**< (DEVICR) Upstream Resume Interrupt Clear Mask */ -#define DEVICR_Msk _U_(0x7F) /**< (DEVICR) Register Mask */ - - -/* -------- DEVIFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */ - -#define DEVIFR_OFFSET (0x0C) /**< (DEVIFR) Device Global Interrupt Set Register Offset */ - -#define DEVIFR_SUSPS_Pos 0 /**< (DEVIFR) Suspend Interrupt Set Position */ -#define DEVIFR_SUSPS (_U_(0x1) << DEVIFR_SUSPS_Pos) /**< (DEVIFR) Suspend Interrupt Set Mask */ -#define DEVIFR_MSOFS_Pos 1 /**< (DEVIFR) Micro Start of Frame Interrupt Set Position */ -#define DEVIFR_MSOFS (_U_(0x1) << DEVIFR_MSOFS_Pos) /**< (DEVIFR) Micro Start of Frame Interrupt Set Mask */ -#define DEVIFR_SOFS_Pos 2 /**< (DEVIFR) Start of Frame Interrupt Set Position */ -#define DEVIFR_SOFS (_U_(0x1) << DEVIFR_SOFS_Pos) /**< (DEVIFR) Start of Frame Interrupt Set Mask */ -#define DEVIFR_EORSTS_Pos 3 /**< (DEVIFR) End of Reset Interrupt Set Position */ -#define DEVIFR_EORSTS (_U_(0x1) << DEVIFR_EORSTS_Pos) /**< (DEVIFR) End of Reset Interrupt Set Mask */ -#define DEVIFR_WAKEUPS_Pos 4 /**< (DEVIFR) Wake-Up Interrupt Set Position */ -#define DEVIFR_WAKEUPS (_U_(0x1) << DEVIFR_WAKEUPS_Pos) /**< (DEVIFR) Wake-Up Interrupt Set Mask */ -#define DEVIFR_EORSMS_Pos 5 /**< (DEVIFR) End of Resume Interrupt Set Position */ -#define DEVIFR_EORSMS (_U_(0x1) << DEVIFR_EORSMS_Pos) /**< (DEVIFR) End of Resume Interrupt Set Mask */ -#define DEVIFR_UPRSMS_Pos 6 /**< (DEVIFR) Upstream Resume Interrupt Set Position */ -#define DEVIFR_UPRSMS (_U_(0x1) << DEVIFR_UPRSMS_Pos) /**< (DEVIFR) Upstream Resume Interrupt Set Mask */ -#define DEVIFR_DMA_1_Pos 25 /**< (DEVIFR) DMA Channel 1 Interrupt Set Position */ -#define DEVIFR_DMA_1 (_U_(0x1) << DEVIFR_DMA_1_Pos) /**< (DEVIFR) DMA Channel 1 Interrupt Set Mask */ -#define DEVIFR_DMA_2_Pos 26 /**< (DEVIFR) DMA Channel 2 Interrupt Set Position */ -#define DEVIFR_DMA_2 (_U_(0x1) << DEVIFR_DMA_2_Pos) /**< (DEVIFR) DMA Channel 2 Interrupt Set Mask */ -#define DEVIFR_DMA_3_Pos 27 /**< (DEVIFR) DMA Channel 3 Interrupt Set Position */ -#define DEVIFR_DMA_3 (_U_(0x1) << DEVIFR_DMA_3_Pos) /**< (DEVIFR) DMA Channel 3 Interrupt Set Mask */ -#define DEVIFR_DMA_4_Pos 28 /**< (DEVIFR) DMA Channel 4 Interrupt Set Position */ -#define DEVIFR_DMA_4 (_U_(0x1) << DEVIFR_DMA_4_Pos) /**< (DEVIFR) DMA Channel 4 Interrupt Set Mask */ -#define DEVIFR_DMA_5_Pos 29 /**< (DEVIFR) DMA Channel 5 Interrupt Set Position */ -#define DEVIFR_DMA_5 (_U_(0x1) << DEVIFR_DMA_5_Pos) /**< (DEVIFR) DMA Channel 5 Interrupt Set Mask */ -#define DEVIFR_DMA_6_Pos 30 /**< (DEVIFR) DMA Channel 6 Interrupt Set Position */ -#define DEVIFR_DMA_6 (_U_(0x1) << DEVIFR_DMA_6_Pos) /**< (DEVIFR) DMA Channel 6 Interrupt Set Mask */ -#define DEVIFR_DMA_7_Pos 31 /**< (DEVIFR) DMA Channel 7 Interrupt Set Position */ -#define DEVIFR_DMA_7 (_U_(0x1) << DEVIFR_DMA_7_Pos) /**< (DEVIFR) DMA Channel 7 Interrupt Set Mask */ -#define DEVIFR_Msk _U_(0xFE00007F) /**< (DEVIFR) Register Mask */ - -#define DEVIFR_DMA__Pos 25 /**< (DEVIFR Position) DMA Channel 7 Interrupt Set */ -#define DEVIFR_DMA_ (_U_(0x7F) << DEVIFR_DMA__Pos) /**< (DEVIFR Mask) DMA_ */ - -/* -------- DEVIMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */ - -#define DEVIMR_OFFSET (0x10) /**< (DEVIMR) Device Global Interrupt Mask Register Offset */ - -#define DEVIMR_SUSPE_Pos 0 /**< (DEVIMR) Suspend Interrupt Mask Position */ -#define DEVIMR_SUSPE (_U_(0x1) << DEVIMR_SUSPE_Pos) /**< (DEVIMR) Suspend Interrupt Mask Mask */ -#define DEVIMR_MSOFE_Pos 1 /**< (DEVIMR) Micro Start of Frame Interrupt Mask Position */ -#define DEVIMR_MSOFE (_U_(0x1) << DEVIMR_MSOFE_Pos) /**< (DEVIMR) Micro Start of Frame Interrupt Mask Mask */ -#define DEVIMR_SOFE_Pos 2 /**< (DEVIMR) Start of Frame Interrupt Mask Position */ -#define DEVIMR_SOFE (_U_(0x1) << DEVIMR_SOFE_Pos) /**< (DEVIMR) Start of Frame Interrupt Mask Mask */ -#define DEVIMR_EORSTE_Pos 3 /**< (DEVIMR) End of Reset Interrupt Mask Position */ -#define DEVIMR_EORSTE (_U_(0x1) << DEVIMR_EORSTE_Pos) /**< (DEVIMR) End of Reset Interrupt Mask Mask */ -#define DEVIMR_WAKEUPE_Pos 4 /**< (DEVIMR) Wake-Up Interrupt Mask Position */ -#define DEVIMR_WAKEUPE (_U_(0x1) << DEVIMR_WAKEUPE_Pos) /**< (DEVIMR) Wake-Up Interrupt Mask Mask */ -#define DEVIMR_EORSME_Pos 5 /**< (DEVIMR) End of Resume Interrupt Mask Position */ -#define DEVIMR_EORSME (_U_(0x1) << DEVIMR_EORSME_Pos) /**< (DEVIMR) End of Resume Interrupt Mask Mask */ -#define DEVIMR_UPRSME_Pos 6 /**< (DEVIMR) Upstream Resume Interrupt Mask Position */ -#define DEVIMR_UPRSME (_U_(0x1) << DEVIMR_UPRSME_Pos) /**< (DEVIMR) Upstream Resume Interrupt Mask Mask */ -#define DEVIMR_PEP_0_Pos 12 /**< (DEVIMR) Endpoint 0 Interrupt Mask Position */ -#define DEVIMR_PEP_0 (_U_(0x1) << DEVIMR_PEP_0_Pos) /**< (DEVIMR) Endpoint 0 Interrupt Mask Mask */ -#define DEVIMR_PEP_1_Pos 13 /**< (DEVIMR) Endpoint 1 Interrupt Mask Position */ -#define DEVIMR_PEP_1 (_U_(0x1) << DEVIMR_PEP_1_Pos) /**< (DEVIMR) Endpoint 1 Interrupt Mask Mask */ -#define DEVIMR_PEP_2_Pos 14 /**< (DEVIMR) Endpoint 2 Interrupt Mask Position */ -#define DEVIMR_PEP_2 (_U_(0x1) << DEVIMR_PEP_2_Pos) /**< (DEVIMR) Endpoint 2 Interrupt Mask Mask */ -#define DEVIMR_PEP_3_Pos 15 /**< (DEVIMR) Endpoint 3 Interrupt Mask Position */ -#define DEVIMR_PEP_3 (_U_(0x1) << DEVIMR_PEP_3_Pos) /**< (DEVIMR) Endpoint 3 Interrupt Mask Mask */ -#define DEVIMR_PEP_4_Pos 16 /**< (DEVIMR) Endpoint 4 Interrupt Mask Position */ -#define DEVIMR_PEP_4 (_U_(0x1) << DEVIMR_PEP_4_Pos) /**< (DEVIMR) Endpoint 4 Interrupt Mask Mask */ -#define DEVIMR_PEP_5_Pos 17 /**< (DEVIMR) Endpoint 5 Interrupt Mask Position */ -#define DEVIMR_PEP_5 (_U_(0x1) << DEVIMR_PEP_5_Pos) /**< (DEVIMR) Endpoint 5 Interrupt Mask Mask */ -#define DEVIMR_PEP_6_Pos 18 /**< (DEVIMR) Endpoint 6 Interrupt Mask Position */ -#define DEVIMR_PEP_6 (_U_(0x1) << DEVIMR_PEP_6_Pos) /**< (DEVIMR) Endpoint 6 Interrupt Mask Mask */ -#define DEVIMR_PEP_7_Pos 19 /**< (DEVIMR) Endpoint 7 Interrupt Mask Position */ -#define DEVIMR_PEP_7 (_U_(0x1) << DEVIMR_PEP_7_Pos) /**< (DEVIMR) Endpoint 7 Interrupt Mask Mask */ -#define DEVIMR_PEP_8_Pos 20 /**< (DEVIMR) Endpoint 8 Interrupt Mask Position */ -#define DEVIMR_PEP_8 (_U_(0x1) << DEVIMR_PEP_8_Pos) /**< (DEVIMR) Endpoint 8 Interrupt Mask Mask */ -#define DEVIMR_PEP_9_Pos 21 /**< (DEVIMR) Endpoint 9 Interrupt Mask Position */ -#define DEVIMR_PEP_9 (_U_(0x1) << DEVIMR_PEP_9_Pos) /**< (DEVIMR) Endpoint 9 Interrupt Mask Mask */ -#define DEVIMR_DMA_1_Pos 25 /**< (DEVIMR) DMA Channel 1 Interrupt Mask Position */ -#define DEVIMR_DMA_1 (_U_(0x1) << DEVIMR_DMA_1_Pos) /**< (DEVIMR) DMA Channel 1 Interrupt Mask Mask */ -#define DEVIMR_DMA_2_Pos 26 /**< (DEVIMR) DMA Channel 2 Interrupt Mask Position */ -#define DEVIMR_DMA_2 (_U_(0x1) << DEVIMR_DMA_2_Pos) /**< (DEVIMR) DMA Channel 2 Interrupt Mask Mask */ -#define DEVIMR_DMA_3_Pos 27 /**< (DEVIMR) DMA Channel 3 Interrupt Mask Position */ -#define DEVIMR_DMA_3 (_U_(0x1) << DEVIMR_DMA_3_Pos) /**< (DEVIMR) DMA Channel 3 Interrupt Mask Mask */ -#define DEVIMR_DMA_4_Pos 28 /**< (DEVIMR) DMA Channel 4 Interrupt Mask Position */ -#define DEVIMR_DMA_4 (_U_(0x1) << DEVIMR_DMA_4_Pos) /**< (DEVIMR) DMA Channel 4 Interrupt Mask Mask */ -#define DEVIMR_DMA_5_Pos 29 /**< (DEVIMR) DMA Channel 5 Interrupt Mask Position */ -#define DEVIMR_DMA_5 (_U_(0x1) << DEVIMR_DMA_5_Pos) /**< (DEVIMR) DMA Channel 5 Interrupt Mask Mask */ -#define DEVIMR_DMA_6_Pos 30 /**< (DEVIMR) DMA Channel 6 Interrupt Mask Position */ -#define DEVIMR_DMA_6 (_U_(0x1) << DEVIMR_DMA_6_Pos) /**< (DEVIMR) DMA Channel 6 Interrupt Mask Mask */ -#define DEVIMR_DMA_7_Pos 31 /**< (DEVIMR) DMA Channel 7 Interrupt Mask Position */ -#define DEVIMR_DMA_7 (_U_(0x1) << DEVIMR_DMA_7_Pos) /**< (DEVIMR) DMA Channel 7 Interrupt Mask Mask */ -#define DEVIMR_Msk _U_(0xFE3FF07F) /**< (DEVIMR) Register Mask */ - -#define DEVIMR_PEP__Pos 12 /**< (DEVIMR Position) Endpoint x Interrupt Mask */ -#define DEVIMR_PEP_ (_U_(0x3FF) << DEVIMR_PEP__Pos) /**< (DEVIMR Mask) PEP_ */ -#define DEVIMR_DMA__Pos 25 /**< (DEVIMR Position) DMA Channel 7 Interrupt Mask */ -#define DEVIMR_DMA_ (_U_(0x7F) << DEVIMR_DMA__Pos) /**< (DEVIMR Mask) DMA_ */ - -/* -------- DEVIDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */ - -#define DEVIDR_OFFSET (0x14) /**< (DEVIDR) Device Global Interrupt Disable Register Offset */ - -#define DEVIDR_SUSPEC_Pos 0 /**< (DEVIDR) Suspend Interrupt Disable Position */ -#define DEVIDR_SUSPEC (_U_(0x1) << DEVIDR_SUSPEC_Pos) /**< (DEVIDR) Suspend Interrupt Disable Mask */ -#define DEVIDR_MSOFEC_Pos 1 /**< (DEVIDR) Micro Start of Frame Interrupt Disable Position */ -#define DEVIDR_MSOFEC (_U_(0x1) << DEVIDR_MSOFEC_Pos) /**< (DEVIDR) Micro Start of Frame Interrupt Disable Mask */ -#define DEVIDR_SOFEC_Pos 2 /**< (DEVIDR) Start of Frame Interrupt Disable Position */ -#define DEVIDR_SOFEC (_U_(0x1) << DEVIDR_SOFEC_Pos) /**< (DEVIDR) Start of Frame Interrupt Disable Mask */ -#define DEVIDR_EORSTEC_Pos 3 /**< (DEVIDR) End of Reset Interrupt Disable Position */ -#define DEVIDR_EORSTEC (_U_(0x1) << DEVIDR_EORSTEC_Pos) /**< (DEVIDR) End of Reset Interrupt Disable Mask */ -#define DEVIDR_WAKEUPEC_Pos 4 /**< (DEVIDR) Wake-Up Interrupt Disable Position */ -#define DEVIDR_WAKEUPEC (_U_(0x1) << DEVIDR_WAKEUPEC_Pos) /**< (DEVIDR) Wake-Up Interrupt Disable Mask */ -#define DEVIDR_EORSMEC_Pos 5 /**< (DEVIDR) End of Resume Interrupt Disable Position */ -#define DEVIDR_EORSMEC (_U_(0x1) << DEVIDR_EORSMEC_Pos) /**< (DEVIDR) End of Resume Interrupt Disable Mask */ -#define DEVIDR_UPRSMEC_Pos 6 /**< (DEVIDR) Upstream Resume Interrupt Disable Position */ -#define DEVIDR_UPRSMEC (_U_(0x1) << DEVIDR_UPRSMEC_Pos) /**< (DEVIDR) Upstream Resume Interrupt Disable Mask */ -#define DEVIDR_PEP_0_Pos 12 /**< (DEVIDR) Endpoint 0 Interrupt Disable Position */ -#define DEVIDR_PEP_0 (_U_(0x1) << DEVIDR_PEP_0_Pos) /**< (DEVIDR) Endpoint 0 Interrupt Disable Mask */ -#define DEVIDR_PEP_1_Pos 13 /**< (DEVIDR) Endpoint 1 Interrupt Disable Position */ -#define DEVIDR_PEP_1 (_U_(0x1) << DEVIDR_PEP_1_Pos) /**< (DEVIDR) Endpoint 1 Interrupt Disable Mask */ -#define DEVIDR_PEP_2_Pos 14 /**< (DEVIDR) Endpoint 2 Interrupt Disable Position */ -#define DEVIDR_PEP_2 (_U_(0x1) << DEVIDR_PEP_2_Pos) /**< (DEVIDR) Endpoint 2 Interrupt Disable Mask */ -#define DEVIDR_PEP_3_Pos 15 /**< (DEVIDR) Endpoint 3 Interrupt Disable Position */ -#define DEVIDR_PEP_3 (_U_(0x1) << DEVIDR_PEP_3_Pos) /**< (DEVIDR) Endpoint 3 Interrupt Disable Mask */ -#define DEVIDR_PEP_4_Pos 16 /**< (DEVIDR) Endpoint 4 Interrupt Disable Position */ -#define DEVIDR_PEP_4 (_U_(0x1) << DEVIDR_PEP_4_Pos) /**< (DEVIDR) Endpoint 4 Interrupt Disable Mask */ -#define DEVIDR_PEP_5_Pos 17 /**< (DEVIDR) Endpoint 5 Interrupt Disable Position */ -#define DEVIDR_PEP_5 (_U_(0x1) << DEVIDR_PEP_5_Pos) /**< (DEVIDR) Endpoint 5 Interrupt Disable Mask */ -#define DEVIDR_PEP_6_Pos 18 /**< (DEVIDR) Endpoint 6 Interrupt Disable Position */ -#define DEVIDR_PEP_6 (_U_(0x1) << DEVIDR_PEP_6_Pos) /**< (DEVIDR) Endpoint 6 Interrupt Disable Mask */ -#define DEVIDR_PEP_7_Pos 19 /**< (DEVIDR) Endpoint 7 Interrupt Disable Position */ -#define DEVIDR_PEP_7 (_U_(0x1) << DEVIDR_PEP_7_Pos) /**< (DEVIDR) Endpoint 7 Interrupt Disable Mask */ -#define DEVIDR_PEP_8_Pos 20 /**< (DEVIDR) Endpoint 8 Interrupt Disable Position */ -#define DEVIDR_PEP_8 (_U_(0x1) << DEVIDR_PEP_8_Pos) /**< (DEVIDR) Endpoint 8 Interrupt Disable Mask */ -#define DEVIDR_PEP_9_Pos 21 /**< (DEVIDR) Endpoint 9 Interrupt Disable Position */ -#define DEVIDR_PEP_9 (_U_(0x1) << DEVIDR_PEP_9_Pos) /**< (DEVIDR) Endpoint 9 Interrupt Disable Mask */ -#define DEVIDR_DMA_1_Pos 25 /**< (DEVIDR) DMA Channel 1 Interrupt Disable Position */ -#define DEVIDR_DMA_1 (_U_(0x1) << DEVIDR_DMA_1_Pos) /**< (DEVIDR) DMA Channel 1 Interrupt Disable Mask */ -#define DEVIDR_DMA_2_Pos 26 /**< (DEVIDR) DMA Channel 2 Interrupt Disable Position */ -#define DEVIDR_DMA_2 (_U_(0x1) << DEVIDR_DMA_2_Pos) /**< (DEVIDR) DMA Channel 2 Interrupt Disable Mask */ -#define DEVIDR_DMA_3_Pos 27 /**< (DEVIDR) DMA Channel 3 Interrupt Disable Position */ -#define DEVIDR_DMA_3 (_U_(0x1) << DEVIDR_DMA_3_Pos) /**< (DEVIDR) DMA Channel 3 Interrupt Disable Mask */ -#define DEVIDR_DMA_4_Pos 28 /**< (DEVIDR) DMA Channel 4 Interrupt Disable Position */ -#define DEVIDR_DMA_4 (_U_(0x1) << DEVIDR_DMA_4_Pos) /**< (DEVIDR) DMA Channel 4 Interrupt Disable Mask */ -#define DEVIDR_DMA_5_Pos 29 /**< (DEVIDR) DMA Channel 5 Interrupt Disable Position */ -#define DEVIDR_DMA_5 (_U_(0x1) << DEVIDR_DMA_5_Pos) /**< (DEVIDR) DMA Channel 5 Interrupt Disable Mask */ -#define DEVIDR_DMA_6_Pos 30 /**< (DEVIDR) DMA Channel 6 Interrupt Disable Position */ -#define DEVIDR_DMA_6 (_U_(0x1) << DEVIDR_DMA_6_Pos) /**< (DEVIDR) DMA Channel 6 Interrupt Disable Mask */ -#define DEVIDR_DMA_7_Pos 31 /**< (DEVIDR) DMA Channel 7 Interrupt Disable Position */ -#define DEVIDR_DMA_7 (_U_(0x1) << DEVIDR_DMA_7_Pos) /**< (DEVIDR) DMA Channel 7 Interrupt Disable Mask */ -#define DEVIDR_Msk _U_(0xFE3FF07F) /**< (DEVIDR) Register Mask */ - -#define DEVIDR_PEP__Pos 12 /**< (DEVIDR Position) Endpoint x Interrupt Disable */ -#define DEVIDR_PEP_ (_U_(0x3FF) << DEVIDR_PEP__Pos) /**< (DEVIDR Mask) PEP_ */ -#define DEVIDR_DMA__Pos 25 /**< (DEVIDR Position) DMA Channel 7 Interrupt Disable */ -#define DEVIDR_DMA_ (_U_(0x7F) << DEVIDR_DMA__Pos) /**< (DEVIDR Mask) DMA_ */ - -/* -------- DEVIER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */ - -#define DEVIER_OFFSET (0x18) /**< (DEVIER) Device Global Interrupt Enable Register Offset */ - -#define DEVIER_SUSPES_Pos 0 /**< (DEVIER) Suspend Interrupt Enable Position */ -#define DEVIER_SUSPES (_U_(0x1) << DEVIER_SUSPES_Pos) /**< (DEVIER) Suspend Interrupt Enable Mask */ -#define DEVIER_MSOFES_Pos 1 /**< (DEVIER) Micro Start of Frame Interrupt Enable Position */ -#define DEVIER_MSOFES (_U_(0x1) << DEVIER_MSOFES_Pos) /**< (DEVIER) Micro Start of Frame Interrupt Enable Mask */ -#define DEVIER_SOFES_Pos 2 /**< (DEVIER) Start of Frame Interrupt Enable Position */ -#define DEVIER_SOFES (_U_(0x1) << DEVIER_SOFES_Pos) /**< (DEVIER) Start of Frame Interrupt Enable Mask */ -#define DEVIER_EORSTES_Pos 3 /**< (DEVIER) End of Reset Interrupt Enable Position */ -#define DEVIER_EORSTES (_U_(0x1) << DEVIER_EORSTES_Pos) /**< (DEVIER) End of Reset Interrupt Enable Mask */ -#define DEVIER_WAKEUPES_Pos 4 /**< (DEVIER) Wake-Up Interrupt Enable Position */ -#define DEVIER_WAKEUPES (_U_(0x1) << DEVIER_WAKEUPES_Pos) /**< (DEVIER) Wake-Up Interrupt Enable Mask */ -#define DEVIER_EORSMES_Pos 5 /**< (DEVIER) End of Resume Interrupt Enable Position */ -#define DEVIER_EORSMES (_U_(0x1) << DEVIER_EORSMES_Pos) /**< (DEVIER) End of Resume Interrupt Enable Mask */ -#define DEVIER_UPRSMES_Pos 6 /**< (DEVIER) Upstream Resume Interrupt Enable Position */ -#define DEVIER_UPRSMES (_U_(0x1) << DEVIER_UPRSMES_Pos) /**< (DEVIER) Upstream Resume Interrupt Enable Mask */ -#define DEVIER_PEP_0_Pos 12 /**< (DEVIER) Endpoint 0 Interrupt Enable Position */ -#define DEVIER_PEP_0 (_U_(0x1) << DEVIER_PEP_0_Pos) /**< (DEVIER) Endpoint 0 Interrupt Enable Mask */ -#define DEVIER_PEP_1_Pos 13 /**< (DEVIER) Endpoint 1 Interrupt Enable Position */ -#define DEVIER_PEP_1 (_U_(0x1) << DEVIER_PEP_1_Pos) /**< (DEVIER) Endpoint 1 Interrupt Enable Mask */ -#define DEVIER_PEP_2_Pos 14 /**< (DEVIER) Endpoint 2 Interrupt Enable Position */ -#define DEVIER_PEP_2 (_U_(0x1) << DEVIER_PEP_2_Pos) /**< (DEVIER) Endpoint 2 Interrupt Enable Mask */ -#define DEVIER_PEP_3_Pos 15 /**< (DEVIER) Endpoint 3 Interrupt Enable Position */ -#define DEVIER_PEP_3 (_U_(0x1) << DEVIER_PEP_3_Pos) /**< (DEVIER) Endpoint 3 Interrupt Enable Mask */ -#define DEVIER_PEP_4_Pos 16 /**< (DEVIER) Endpoint 4 Interrupt Enable Position */ -#define DEVIER_PEP_4 (_U_(0x1) << DEVIER_PEP_4_Pos) /**< (DEVIER) Endpoint 4 Interrupt Enable Mask */ -#define DEVIER_PEP_5_Pos 17 /**< (DEVIER) Endpoint 5 Interrupt Enable Position */ -#define DEVIER_PEP_5 (_U_(0x1) << DEVIER_PEP_5_Pos) /**< (DEVIER) Endpoint 5 Interrupt Enable Mask */ -#define DEVIER_PEP_6_Pos 18 /**< (DEVIER) Endpoint 6 Interrupt Enable Position */ -#define DEVIER_PEP_6 (_U_(0x1) << DEVIER_PEP_6_Pos) /**< (DEVIER) Endpoint 6 Interrupt Enable Mask */ -#define DEVIER_PEP_7_Pos 19 /**< (DEVIER) Endpoint 7 Interrupt Enable Position */ -#define DEVIER_PEP_7 (_U_(0x1) << DEVIER_PEP_7_Pos) /**< (DEVIER) Endpoint 7 Interrupt Enable Mask */ -#define DEVIER_PEP_8_Pos 20 /**< (DEVIER) Endpoint 8 Interrupt Enable Position */ -#define DEVIER_PEP_8 (_U_(0x1) << DEVIER_PEP_8_Pos) /**< (DEVIER) Endpoint 8 Interrupt Enable Mask */ -#define DEVIER_PEP_9_Pos 21 /**< (DEVIER) Endpoint 9 Interrupt Enable Position */ -#define DEVIER_PEP_9 (_U_(0x1) << DEVIER_PEP_9_Pos) /**< (DEVIER) Endpoint 9 Interrupt Enable Mask */ -#define DEVIER_DMA_1_Pos 25 /**< (DEVIER) DMA Channel 1 Interrupt Enable Position */ -#define DEVIER_DMA_1 (_U_(0x1) << DEVIER_DMA_1_Pos) /**< (DEVIER) DMA Channel 1 Interrupt Enable Mask */ -#define DEVIER_DMA_2_Pos 26 /**< (DEVIER) DMA Channel 2 Interrupt Enable Position */ -#define DEVIER_DMA_2 (_U_(0x1) << DEVIER_DMA_2_Pos) /**< (DEVIER) DMA Channel 2 Interrupt Enable Mask */ -#define DEVIER_DMA_3_Pos 27 /**< (DEVIER) DMA Channel 3 Interrupt Enable Position */ -#define DEVIER_DMA_3 (_U_(0x1) << DEVIER_DMA_3_Pos) /**< (DEVIER) DMA Channel 3 Interrupt Enable Mask */ -#define DEVIER_DMA_4_Pos 28 /**< (DEVIER) DMA Channel 4 Interrupt Enable Position */ -#define DEVIER_DMA_4 (_U_(0x1) << DEVIER_DMA_4_Pos) /**< (DEVIER) DMA Channel 4 Interrupt Enable Mask */ -#define DEVIER_DMA_5_Pos 29 /**< (DEVIER) DMA Channel 5 Interrupt Enable Position */ -#define DEVIER_DMA_5 (_U_(0x1) << DEVIER_DMA_5_Pos) /**< (DEVIER) DMA Channel 5 Interrupt Enable Mask */ -#define DEVIER_DMA_6_Pos 30 /**< (DEVIER) DMA Channel 6 Interrupt Enable Position */ -#define DEVIER_DMA_6 (_U_(0x1) << DEVIER_DMA_6_Pos) /**< (DEVIER) DMA Channel 6 Interrupt Enable Mask */ -#define DEVIER_DMA_7_Pos 31 /**< (DEVIER) DMA Channel 7 Interrupt Enable Position */ -#define DEVIER_DMA_7 (_U_(0x1) << DEVIER_DMA_7_Pos) /**< (DEVIER) DMA Channel 7 Interrupt Enable Mask */ -#define DEVIER_Msk _U_(0xFE3FF07F) /**< (DEVIER) Register Mask */ - -#define DEVIER_PEP__Pos 12 /**< (DEVIER Position) Endpoint x Interrupt Enable */ -#define DEVIER_PEP_ (_U_(0x3FF) << DEVIER_PEP__Pos) /**< (DEVIER Mask) PEP_ */ -#define DEVIER_DMA__Pos 25 /**< (DEVIER Position) DMA Channel 7 Interrupt Enable */ -#define DEVIER_DMA_ (_U_(0x7F) << DEVIER_DMA__Pos) /**< (DEVIER Mask) DMA_ */ - -/* -------- DEVEPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */ - -#define DEVEPT_OFFSET (0x1C) /**< (DEVEPT) Device Endpoint Register Offset */ - -#define DEVEPT_EPEN0_Pos 0 /**< (DEVEPT) Endpoint 0 Enable Position */ -#define DEVEPT_EPEN0 (_U_(0x1) << DEVEPT_EPEN0_Pos) /**< (DEVEPT) Endpoint 0 Enable Mask */ -#define DEVEPT_EPEN1_Pos 1 /**< (DEVEPT) Endpoint 1 Enable Position */ -#define DEVEPT_EPEN1 (_U_(0x1) << DEVEPT_EPEN1_Pos) /**< (DEVEPT) Endpoint 1 Enable Mask */ -#define DEVEPT_EPEN2_Pos 2 /**< (DEVEPT) Endpoint 2 Enable Position */ -#define DEVEPT_EPEN2 (_U_(0x1) << DEVEPT_EPEN2_Pos) /**< (DEVEPT) Endpoint 2 Enable Mask */ -#define DEVEPT_EPEN3_Pos 3 /**< (DEVEPT) Endpoint 3 Enable Position */ -#define DEVEPT_EPEN3 (_U_(0x1) << DEVEPT_EPEN3_Pos) /**< (DEVEPT) Endpoint 3 Enable Mask */ -#define DEVEPT_EPEN4_Pos 4 /**< (DEVEPT) Endpoint 4 Enable Position */ -#define DEVEPT_EPEN4 (_U_(0x1) << DEVEPT_EPEN4_Pos) /**< (DEVEPT) Endpoint 4 Enable Mask */ -#define DEVEPT_EPEN5_Pos 5 /**< (DEVEPT) Endpoint 5 Enable Position */ -#define DEVEPT_EPEN5 (_U_(0x1) << DEVEPT_EPEN5_Pos) /**< (DEVEPT) Endpoint 5 Enable Mask */ -#define DEVEPT_EPEN6_Pos 6 /**< (DEVEPT) Endpoint 6 Enable Position */ -#define DEVEPT_EPEN6 (_U_(0x1) << DEVEPT_EPEN6_Pos) /**< (DEVEPT) Endpoint 6 Enable Mask */ -#define DEVEPT_EPEN7_Pos 7 /**< (DEVEPT) Endpoint 7 Enable Position */ -#define DEVEPT_EPEN7 (_U_(0x1) << DEVEPT_EPEN7_Pos) /**< (DEVEPT) Endpoint 7 Enable Mask */ -#define DEVEPT_EPEN8_Pos 8 /**< (DEVEPT) Endpoint 8 Enable Position */ -#define DEVEPT_EPEN8 (_U_(0x1) << DEVEPT_EPEN8_Pos) /**< (DEVEPT) Endpoint 8 Enable Mask */ -#define DEVEPT_EPEN9_Pos 9 /**< (DEVEPT) Endpoint 9 Enable Position */ -#define DEVEPT_EPEN9 (_U_(0x1) << DEVEPT_EPEN9_Pos) /**< (DEVEPT) Endpoint 9 Enable Mask */ -#define DEVEPT_EPRST0_Pos 16 /**< (DEVEPT) Endpoint 0 Reset Position */ -#define DEVEPT_EPRST0 (_U_(0x1) << DEVEPT_EPRST0_Pos) /**< (DEVEPT) Endpoint 0 Reset Mask */ -#define DEVEPT_EPRST1_Pos 17 /**< (DEVEPT) Endpoint 1 Reset Position */ -#define DEVEPT_EPRST1 (_U_(0x1) << DEVEPT_EPRST1_Pos) /**< (DEVEPT) Endpoint 1 Reset Mask */ -#define DEVEPT_EPRST2_Pos 18 /**< (DEVEPT) Endpoint 2 Reset Position */ -#define DEVEPT_EPRST2 (_U_(0x1) << DEVEPT_EPRST2_Pos) /**< (DEVEPT) Endpoint 2 Reset Mask */ -#define DEVEPT_EPRST3_Pos 19 /**< (DEVEPT) Endpoint 3 Reset Position */ -#define DEVEPT_EPRST3 (_U_(0x1) << DEVEPT_EPRST3_Pos) /**< (DEVEPT) Endpoint 3 Reset Mask */ -#define DEVEPT_EPRST4_Pos 20 /**< (DEVEPT) Endpoint 4 Reset Position */ -#define DEVEPT_EPRST4 (_U_(0x1) << DEVEPT_EPRST4_Pos) /**< (DEVEPT) Endpoint 4 Reset Mask */ -#define DEVEPT_EPRST5_Pos 21 /**< (DEVEPT) Endpoint 5 Reset Position */ -#define DEVEPT_EPRST5 (_U_(0x1) << DEVEPT_EPRST5_Pos) /**< (DEVEPT) Endpoint 5 Reset Mask */ -#define DEVEPT_EPRST6_Pos 22 /**< (DEVEPT) Endpoint 6 Reset Position */ -#define DEVEPT_EPRST6 (_U_(0x1) << DEVEPT_EPRST6_Pos) /**< (DEVEPT) Endpoint 6 Reset Mask */ -#define DEVEPT_EPRST7_Pos 23 /**< (DEVEPT) Endpoint 7 Reset Position */ -#define DEVEPT_EPRST7 (_U_(0x1) << DEVEPT_EPRST7_Pos) /**< (DEVEPT) Endpoint 7 Reset Mask */ -#define DEVEPT_EPRST8_Pos 24 /**< (DEVEPT) Endpoint 8 Reset Position */ -#define DEVEPT_EPRST8 (_U_(0x1) << DEVEPT_EPRST8_Pos) /**< (DEVEPT) Endpoint 8 Reset Mask */ -#define DEVEPT_EPRST9_Pos 25 /**< (DEVEPT) Endpoint 9 Reset Position */ -#define DEVEPT_EPRST9 (_U_(0x1) << DEVEPT_EPRST9_Pos) /**< (DEVEPT) Endpoint 9 Reset Mask */ -#define DEVEPT_Msk _U_(0x3FF03FF) /**< (DEVEPT) Register Mask */ - -#define DEVEPT_EPEN_Pos 0 /**< (DEVEPT Position) Endpoint x Enable */ -#define DEVEPT_EPEN (_U_(0x3FF) << DEVEPT_EPEN_Pos) /**< (DEVEPT Mask) EPEN */ -#define DEVEPT_EPRST_Pos 16 /**< (DEVEPT Position) Endpoint 9 Reset */ -#define DEVEPT_EPRST (_U_(0x3FF) << DEVEPT_EPRST_Pos) /**< (DEVEPT Mask) EPRST */ - -/* -------- DEVFNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */ - -#define DEVFNUM_OFFSET (0x20) /**< (DEVFNUM) Device Frame Number Register Offset */ - -#define DEVFNUM_MFNUM_Pos 0 /**< (DEVFNUM) Micro Frame Number Position */ -#define DEVFNUM_MFNUM (_U_(0x7) << DEVFNUM_MFNUM_Pos) /**< (DEVFNUM) Micro Frame Number Mask */ -#define DEVFNUM_FNUM_Pos 3 /**< (DEVFNUM) Frame Number Position */ -#define DEVFNUM_FNUM (_U_(0x7FF) << DEVFNUM_FNUM_Pos) /**< (DEVFNUM) Frame Number Mask */ -#define DEVFNUM_FNCERR_Pos 15 /**< (DEVFNUM) Frame Number CRC Error Position */ -#define DEVFNUM_FNCERR (_U_(0x1) << DEVFNUM_FNCERR_Pos) /**< (DEVFNUM) Frame Number CRC Error Mask */ -#define DEVFNUM_Msk _U_(0xBFFF) /**< (DEVFNUM) Register Mask */ - - -/* -------- DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */ - -#define DEVEPTCFG_OFFSET (0x100) /**< (DEVEPTCFG) Device Endpoint Configuration Register Offset */ - -#define DEVEPTCFG_ALLOC_Pos 1 /**< (DEVEPTCFG) Endpoint Memory Allocate Position */ -#define DEVEPTCFG_ALLOC (_U_(0x1) << DEVEPTCFG_ALLOC_Pos) /**< (DEVEPTCFG) Endpoint Memory Allocate Mask */ -#define DEVEPTCFG_EPBK_Pos 2 /**< (DEVEPTCFG) Endpoint Banks Position */ -#define DEVEPTCFG_EPBK (_U_(0x3) << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Endpoint Banks Mask */ -#define DEVEPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (DEVEPTCFG) Single-bank endpoint */ -#define DEVEPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (DEVEPTCFG) Double-bank endpoint */ -#define DEVEPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (DEVEPTCFG) Triple-bank endpoint */ -#define DEVEPTCFG_EPBK_1_BANK (DEVEPTCFG_EPBK_1_BANK_Val << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Single-bank endpoint Position */ -#define DEVEPTCFG_EPBK_2_BANK (DEVEPTCFG_EPBK_2_BANK_Val << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Double-bank endpoint Position */ -#define DEVEPTCFG_EPBK_3_BANK (DEVEPTCFG_EPBK_3_BANK_Val << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Triple-bank endpoint Position */ -#define DEVEPTCFG_EPSIZE_Pos 4 /**< (DEVEPTCFG) Endpoint Size Position */ -#define DEVEPTCFG_EPSIZE (_U_(0x7) << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) Endpoint Size Mask */ -#define DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (DEVEPTCFG) 8 bytes */ -#define DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (DEVEPTCFG) 16 bytes */ -#define DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (DEVEPTCFG) 32 bytes */ -#define DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (DEVEPTCFG) 64 bytes */ -#define DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (DEVEPTCFG) 128 bytes */ -#define DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (DEVEPTCFG) 256 bytes */ -#define DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (DEVEPTCFG) 512 bytes */ -#define DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (DEVEPTCFG) 1024 bytes */ -#define DEVEPTCFG_EPSIZE_8_BYTE (DEVEPTCFG_EPSIZE_8_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 8 bytes Position */ -#define DEVEPTCFG_EPSIZE_16_BYTE (DEVEPTCFG_EPSIZE_16_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 16 bytes Position */ -#define DEVEPTCFG_EPSIZE_32_BYTE (DEVEPTCFG_EPSIZE_32_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 32 bytes Position */ -#define DEVEPTCFG_EPSIZE_64_BYTE (DEVEPTCFG_EPSIZE_64_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 64 bytes Position */ -#define DEVEPTCFG_EPSIZE_128_BYTE (DEVEPTCFG_EPSIZE_128_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 128 bytes Position */ -#define DEVEPTCFG_EPSIZE_256_BYTE (DEVEPTCFG_EPSIZE_256_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 256 bytes Position */ -#define DEVEPTCFG_EPSIZE_512_BYTE (DEVEPTCFG_EPSIZE_512_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 512 bytes Position */ -#define DEVEPTCFG_EPSIZE_1024_BYTE (DEVEPTCFG_EPSIZE_1024_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 1024 bytes Position */ -#define DEVEPTCFG_EPDIR_Pos 8 /**< (DEVEPTCFG) Endpoint Direction Position */ -#define DEVEPTCFG_EPDIR (_U_(0x1) << DEVEPTCFG_EPDIR_Pos) /**< (DEVEPTCFG) Endpoint Direction Mask */ -#define DEVEPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (DEVEPTCFG) The endpoint direction is OUT. */ -#define DEVEPTCFG_EPDIR_IN_Val _U_(0x1) /**< (DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). */ -#define DEVEPTCFG_EPDIR_OUT (DEVEPTCFG_EPDIR_OUT_Val << DEVEPTCFG_EPDIR_Pos) /**< (DEVEPTCFG) The endpoint direction is OUT. Position */ -#define DEVEPTCFG_EPDIR_IN (DEVEPTCFG_EPDIR_IN_Val << DEVEPTCFG_EPDIR_Pos) /**< (DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ -#define DEVEPTCFG_AUTOSW_Pos 9 /**< (DEVEPTCFG) Automatic Switch Position */ -#define DEVEPTCFG_AUTOSW (_U_(0x1) << DEVEPTCFG_AUTOSW_Pos) /**< (DEVEPTCFG) Automatic Switch Mask */ -#define DEVEPTCFG_EPTYPE_Pos 11 /**< (DEVEPTCFG) Endpoint Type Position */ -#define DEVEPTCFG_EPTYPE (_U_(0x3) << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Endpoint Type Mask */ -#define DEVEPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (DEVEPTCFG) Control */ -#define DEVEPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (DEVEPTCFG) Isochronous */ -#define DEVEPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (DEVEPTCFG) Bulk */ -#define DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (DEVEPTCFG) Interrupt */ -#define DEVEPTCFG_EPTYPE_CTRL (DEVEPTCFG_EPTYPE_CTRL_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Control Position */ -#define DEVEPTCFG_EPTYPE_ISO (DEVEPTCFG_EPTYPE_ISO_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Isochronous Position */ -#define DEVEPTCFG_EPTYPE_BLK (DEVEPTCFG_EPTYPE_BLK_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Bulk Position */ -#define DEVEPTCFG_EPTYPE_INTRPT (DEVEPTCFG_EPTYPE_INTRPT_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Interrupt Position */ -#define DEVEPTCFG_NBTRANS_Pos 13 /**< (DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */ -#define DEVEPTCFG_NBTRANS (_U_(0x3) << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ -#define DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ -#define DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (DEVEPTCFG) Default value: one transaction per microframe. */ -#define DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ -#define DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ -#define DEVEPTCFG_NBTRANS_0_TRANS (DEVEPTCFG_NBTRANS_0_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ -#define DEVEPTCFG_NBTRANS_1_TRANS (DEVEPTCFG_NBTRANS_1_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Default value: one transaction per microframe. Position */ -#define DEVEPTCFG_NBTRANS_2_TRANS (DEVEPTCFG_NBTRANS_2_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ -#define DEVEPTCFG_NBTRANS_3_TRANS (DEVEPTCFG_NBTRANS_3_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ -#define DEVEPTCFG_Msk _U_(0x7B7E) /**< (DEVEPTCFG) Register Mask */ - - -/* -------- DEVEPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */ - -#define DEVEPTISR_OFFSET (0x130) /**< (DEVEPTISR) Device Endpoint Interrupt Status Register Offset */ - -#define DEVEPTISR_TXINI_Pos 0 /**< (DEVEPTISR) Transmitted IN Data Interrupt Position */ -#define DEVEPTISR_TXINI (_U_(0x1) << DEVEPTISR_TXINI_Pos) /**< (DEVEPTISR) Transmitted IN Data Interrupt Mask */ -#define DEVEPTISR_RXOUTI_Pos 1 /**< (DEVEPTISR) Received OUT Data Interrupt Position */ -#define DEVEPTISR_RXOUTI (_U_(0x1) << DEVEPTISR_RXOUTI_Pos) /**< (DEVEPTISR) Received OUT Data Interrupt Mask */ -#define DEVEPTISR_OVERFI_Pos 5 /**< (DEVEPTISR) Overflow Interrupt Position */ -#define DEVEPTISR_OVERFI (_U_(0x1) << DEVEPTISR_OVERFI_Pos) /**< (DEVEPTISR) Overflow Interrupt Mask */ -#define DEVEPTISR_SHORTPACKET_Pos 7 /**< (DEVEPTISR) Short Packet Interrupt Position */ -#define DEVEPTISR_SHORTPACKET (_U_(0x1) << DEVEPTISR_SHORTPACKET_Pos) /**< (DEVEPTISR) Short Packet Interrupt Mask */ -#define DEVEPTISR_DTSEQ_Pos 8 /**< (DEVEPTISR) Data Toggle Sequence Position */ -#define DEVEPTISR_DTSEQ (_U_(0x3) << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Data Toggle Sequence Mask */ -#define DEVEPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (DEVEPTISR) Data0 toggle sequence */ -#define DEVEPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (DEVEPTISR) Data1 toggle sequence */ -#define DEVEPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ -#define DEVEPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ -#define DEVEPTISR_DTSEQ_DATA0 (DEVEPTISR_DTSEQ_DATA0_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Data0 toggle sequence Position */ -#define DEVEPTISR_DTSEQ_DATA1 (DEVEPTISR_DTSEQ_DATA1_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Data1 toggle sequence Position */ -#define DEVEPTISR_DTSEQ_DATA2 (DEVEPTISR_DTSEQ_DATA2_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ -#define DEVEPTISR_DTSEQ_MDATA (DEVEPTISR_DTSEQ_MDATA_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ -#define DEVEPTISR_NBUSYBK_Pos 12 /**< (DEVEPTISR) Number of Busy Banks Position */ -#define DEVEPTISR_NBUSYBK (_U_(0x3) << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) Number of Busy Banks Mask */ -#define DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (DEVEPTISR) 0 busy bank (all banks free) */ -#define DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (DEVEPTISR) 1 busy bank */ -#define DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (DEVEPTISR) 2 busy banks */ -#define DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (DEVEPTISR) 3 busy banks */ -#define DEVEPTISR_NBUSYBK_0_BUSY (DEVEPTISR_NBUSYBK_0_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 0 busy bank (all banks free) Position */ -#define DEVEPTISR_NBUSYBK_1_BUSY (DEVEPTISR_NBUSYBK_1_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 1 busy bank Position */ -#define DEVEPTISR_NBUSYBK_2_BUSY (DEVEPTISR_NBUSYBK_2_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 2 busy banks Position */ -#define DEVEPTISR_NBUSYBK_3_BUSY (DEVEPTISR_NBUSYBK_3_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 3 busy banks Position */ -#define DEVEPTISR_CURRBK_Pos 14 /**< (DEVEPTISR) Current Bank Position */ -#define DEVEPTISR_CURRBK (_U_(0x3) << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current Bank Mask */ -#define DEVEPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (DEVEPTISR) Current bank is bank0 */ -#define DEVEPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (DEVEPTISR) Current bank is bank1 */ -#define DEVEPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (DEVEPTISR) Current bank is bank2 */ -#define DEVEPTISR_CURRBK_BANK0 (DEVEPTISR_CURRBK_BANK0_Val << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current bank is bank0 Position */ -#define DEVEPTISR_CURRBK_BANK1 (DEVEPTISR_CURRBK_BANK1_Val << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current bank is bank1 Position */ -#define DEVEPTISR_CURRBK_BANK2 (DEVEPTISR_CURRBK_BANK2_Val << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current bank is bank2 Position */ -#define DEVEPTISR_RWALL_Pos 16 /**< (DEVEPTISR) Read/Write Allowed Position */ -#define DEVEPTISR_RWALL (_U_(0x1) << DEVEPTISR_RWALL_Pos) /**< (DEVEPTISR) Read/Write Allowed Mask */ -#define DEVEPTISR_CFGOK_Pos 18 /**< (DEVEPTISR) Configuration OK Status Position */ -#define DEVEPTISR_CFGOK (_U_(0x1) << DEVEPTISR_CFGOK_Pos) /**< (DEVEPTISR) Configuration OK Status Mask */ -#define DEVEPTISR_BYCT_Pos 20 /**< (DEVEPTISR) Byte Count Position */ -#define DEVEPTISR_BYCT (_U_(0x7FF) << DEVEPTISR_BYCT_Pos) /**< (DEVEPTISR) Byte Count Mask */ -#define DEVEPTISR_Msk _U_(0x7FF5F3A3) /**< (DEVEPTISR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTISR_CTRL_RXSTPI_Pos 2 /**< (DEVEPTISR) Received SETUP Interrupt Position */ -#define DEVEPTISR_CTRL_RXSTPI (_U_(0x1) << DEVEPTISR_CTRL_RXSTPI_Pos) /**< (DEVEPTISR) Received SETUP Interrupt Mask */ -#define DEVEPTISR_CTRL_NAKOUTI_Pos 3 /**< (DEVEPTISR) NAKed OUT Interrupt Position */ -#define DEVEPTISR_CTRL_NAKOUTI (_U_(0x1) << DEVEPTISR_CTRL_NAKOUTI_Pos) /**< (DEVEPTISR) NAKed OUT Interrupt Mask */ -#define DEVEPTISR_CTRL_NAKINI_Pos 4 /**< (DEVEPTISR) NAKed IN Interrupt Position */ -#define DEVEPTISR_CTRL_NAKINI (_U_(0x1) << DEVEPTISR_CTRL_NAKINI_Pos) /**< (DEVEPTISR) NAKed IN Interrupt Mask */ -#define DEVEPTISR_CTRL_STALLEDI_Pos 6 /**< (DEVEPTISR) STALLed Interrupt Position */ -#define DEVEPTISR_CTRL_STALLEDI (_U_(0x1) << DEVEPTISR_CTRL_STALLEDI_Pos) /**< (DEVEPTISR) STALLed Interrupt Mask */ -#define DEVEPTISR_CTRL_CTRLDIR_Pos 17 /**< (DEVEPTISR) Control Direction Position */ -#define DEVEPTISR_CTRL_CTRLDIR (_U_(0x1) << DEVEPTISR_CTRL_CTRLDIR_Pos) /**< (DEVEPTISR) Control Direction Mask */ -#define DEVEPTISR_CTRL_Msk _U_(0x2005C) /**< (DEVEPTISR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTISR_ISO_UNDERFI_Pos 2 /**< (DEVEPTISR) Underflow Interrupt Position */ -#define DEVEPTISR_ISO_UNDERFI (_U_(0x1) << DEVEPTISR_ISO_UNDERFI_Pos) /**< (DEVEPTISR) Underflow Interrupt Mask */ -#define DEVEPTISR_ISO_HBISOINERRI_Pos 3 /**< (DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ -#define DEVEPTISR_ISO_HBISOINERRI (_U_(0x1) << DEVEPTISR_ISO_HBISOINERRI_Pos) /**< (DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ -#define DEVEPTISR_ISO_HBISOFLUSHI_Pos 4 /**< (DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */ -#define DEVEPTISR_ISO_HBISOFLUSHI (_U_(0x1) << DEVEPTISR_ISO_HBISOFLUSHI_Pos) /**< (DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */ -#define DEVEPTISR_ISO_CRCERRI_Pos 6 /**< (DEVEPTISR) CRC Error Interrupt Position */ -#define DEVEPTISR_ISO_CRCERRI (_U_(0x1) << DEVEPTISR_ISO_CRCERRI_Pos) /**< (DEVEPTISR) CRC Error Interrupt Mask */ -#define DEVEPTISR_ISO_ERRORTRANS_Pos 10 /**< (DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */ -#define DEVEPTISR_ISO_ERRORTRANS (_U_(0x1) << DEVEPTISR_ISO_ERRORTRANS_Pos) /**< (DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */ -#define DEVEPTISR_ISO_Msk _U_(0x45C) /**< (DEVEPTISR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTISR_BLK_RXSTPI_Pos 2 /**< (DEVEPTISR) Received SETUP Interrupt Position */ -#define DEVEPTISR_BLK_RXSTPI (_U_(0x1) << DEVEPTISR_BLK_RXSTPI_Pos) /**< (DEVEPTISR) Received SETUP Interrupt Mask */ -#define DEVEPTISR_BLK_NAKOUTI_Pos 3 /**< (DEVEPTISR) NAKed OUT Interrupt Position */ -#define DEVEPTISR_BLK_NAKOUTI (_U_(0x1) << DEVEPTISR_BLK_NAKOUTI_Pos) /**< (DEVEPTISR) NAKed OUT Interrupt Mask */ -#define DEVEPTISR_BLK_NAKINI_Pos 4 /**< (DEVEPTISR) NAKed IN Interrupt Position */ -#define DEVEPTISR_BLK_NAKINI (_U_(0x1) << DEVEPTISR_BLK_NAKINI_Pos) /**< (DEVEPTISR) NAKed IN Interrupt Mask */ -#define DEVEPTISR_BLK_STALLEDI_Pos 6 /**< (DEVEPTISR) STALLed Interrupt Position */ -#define DEVEPTISR_BLK_STALLEDI (_U_(0x1) << DEVEPTISR_BLK_STALLEDI_Pos) /**< (DEVEPTISR) STALLed Interrupt Mask */ -#define DEVEPTISR_BLK_CTRLDIR_Pos 17 /**< (DEVEPTISR) Control Direction Position */ -#define DEVEPTISR_BLK_CTRLDIR (_U_(0x1) << DEVEPTISR_BLK_CTRLDIR_Pos) /**< (DEVEPTISR) Control Direction Mask */ -#define DEVEPTISR_BLK_Msk _U_(0x2005C) /**< (DEVEPTISR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTISR_INTRPT_RXSTPI_Pos 2 /**< (DEVEPTISR) Received SETUP Interrupt Position */ -#define DEVEPTISR_INTRPT_RXSTPI (_U_(0x1) << DEVEPTISR_INTRPT_RXSTPI_Pos) /**< (DEVEPTISR) Received SETUP Interrupt Mask */ -#define DEVEPTISR_INTRPT_NAKOUTI_Pos 3 /**< (DEVEPTISR) NAKed OUT Interrupt Position */ -#define DEVEPTISR_INTRPT_NAKOUTI (_U_(0x1) << DEVEPTISR_INTRPT_NAKOUTI_Pos) /**< (DEVEPTISR) NAKed OUT Interrupt Mask */ -#define DEVEPTISR_INTRPT_NAKINI_Pos 4 /**< (DEVEPTISR) NAKed IN Interrupt Position */ -#define DEVEPTISR_INTRPT_NAKINI (_U_(0x1) << DEVEPTISR_INTRPT_NAKINI_Pos) /**< (DEVEPTISR) NAKed IN Interrupt Mask */ -#define DEVEPTISR_INTRPT_STALLEDI_Pos 6 /**< (DEVEPTISR) STALLed Interrupt Position */ -#define DEVEPTISR_INTRPT_STALLEDI (_U_(0x1) << DEVEPTISR_INTRPT_STALLEDI_Pos) /**< (DEVEPTISR) STALLed Interrupt Mask */ -#define DEVEPTISR_INTRPT_CTRLDIR_Pos 17 /**< (DEVEPTISR) Control Direction Position */ -#define DEVEPTISR_INTRPT_CTRLDIR (_U_(0x1) << DEVEPTISR_INTRPT_CTRLDIR_Pos) /**< (DEVEPTISR) Control Direction Mask */ -#define DEVEPTISR_INTRPT_Msk _U_(0x2005C) /**< (DEVEPTISR_INTRPT) Register Mask */ - - -/* -------- DEVEPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */ - -#define DEVEPTICR_OFFSET (0x160) /**< (DEVEPTICR) Device Endpoint Interrupt Clear Register Offset */ - -#define DEVEPTICR_TXINIC_Pos 0 /**< (DEVEPTICR) Transmitted IN Data Interrupt Clear Position */ -#define DEVEPTICR_TXINIC (_U_(0x1) << DEVEPTICR_TXINIC_Pos) /**< (DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */ -#define DEVEPTICR_RXOUTIC_Pos 1 /**< (DEVEPTICR) Received OUT Data Interrupt Clear Position */ -#define DEVEPTICR_RXOUTIC (_U_(0x1) << DEVEPTICR_RXOUTIC_Pos) /**< (DEVEPTICR) Received OUT Data Interrupt Clear Mask */ -#define DEVEPTICR_OVERFIC_Pos 5 /**< (DEVEPTICR) Overflow Interrupt Clear Position */ -#define DEVEPTICR_OVERFIC (_U_(0x1) << DEVEPTICR_OVERFIC_Pos) /**< (DEVEPTICR) Overflow Interrupt Clear Mask */ -#define DEVEPTICR_SHORTPACKETC_Pos 7 /**< (DEVEPTICR) Short Packet Interrupt Clear Position */ -#define DEVEPTICR_SHORTPACKETC (_U_(0x1) << DEVEPTICR_SHORTPACKETC_Pos) /**< (DEVEPTICR) Short Packet Interrupt Clear Mask */ -#define DEVEPTICR_Msk _U_(0xA3) /**< (DEVEPTICR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTICR_CTRL_RXSTPIC_Pos 2 /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */ -#define DEVEPTICR_CTRL_RXSTPIC (_U_(0x1) << DEVEPTICR_CTRL_RXSTPIC_Pos) /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_NAKOUTIC_Pos 3 /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTICR_CTRL_NAKOUTIC (_U_(0x1) << DEVEPTICR_CTRL_NAKOUTIC_Pos) /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_NAKINIC_Pos 4 /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */ -#define DEVEPTICR_CTRL_NAKINIC (_U_(0x1) << DEVEPTICR_CTRL_NAKINIC_Pos) /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_STALLEDIC_Pos 6 /**< (DEVEPTICR) STALLed Interrupt Clear Position */ -#define DEVEPTICR_CTRL_STALLEDIC (_U_(0x1) << DEVEPTICR_CTRL_STALLEDIC_Pos) /**< (DEVEPTICR) STALLed Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_Msk _U_(0x5C) /**< (DEVEPTICR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTICR_ISO_UNDERFIC_Pos 2 /**< (DEVEPTICR) Underflow Interrupt Clear Position */ -#define DEVEPTICR_ISO_UNDERFIC (_U_(0x1) << DEVEPTICR_ISO_UNDERFIC_Pos) /**< (DEVEPTICR) Underflow Interrupt Clear Mask */ -#define DEVEPTICR_ISO_HBISOINERRIC_Pos 3 /**< (DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ -#define DEVEPTICR_ISO_HBISOINERRIC (_U_(0x1) << DEVEPTICR_ISO_HBISOINERRIC_Pos) /**< (DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ -#define DEVEPTICR_ISO_HBISOFLUSHIC_Pos 4 /**< (DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ -#define DEVEPTICR_ISO_HBISOFLUSHIC (_U_(0x1) << DEVEPTICR_ISO_HBISOFLUSHIC_Pos) /**< (DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ -#define DEVEPTICR_ISO_CRCERRIC_Pos 6 /**< (DEVEPTICR) CRC Error Interrupt Clear Position */ -#define DEVEPTICR_ISO_CRCERRIC (_U_(0x1) << DEVEPTICR_ISO_CRCERRIC_Pos) /**< (DEVEPTICR) CRC Error Interrupt Clear Mask */ -#define DEVEPTICR_ISO_Msk _U_(0x5C) /**< (DEVEPTICR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTICR_BLK_RXSTPIC_Pos 2 /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */ -#define DEVEPTICR_BLK_RXSTPIC (_U_(0x1) << DEVEPTICR_BLK_RXSTPIC_Pos) /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTICR_BLK_NAKOUTIC_Pos 3 /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTICR_BLK_NAKOUTIC (_U_(0x1) << DEVEPTICR_BLK_NAKOUTIC_Pos) /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTICR_BLK_NAKINIC_Pos 4 /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */ -#define DEVEPTICR_BLK_NAKINIC (_U_(0x1) << DEVEPTICR_BLK_NAKINIC_Pos) /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTICR_BLK_STALLEDIC_Pos 6 /**< (DEVEPTICR) STALLed Interrupt Clear Position */ -#define DEVEPTICR_BLK_STALLEDIC (_U_(0x1) << DEVEPTICR_BLK_STALLEDIC_Pos) /**< (DEVEPTICR) STALLed Interrupt Clear Mask */ -#define DEVEPTICR_BLK_Msk _U_(0x5C) /**< (DEVEPTICR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTICR_INTRPT_RXSTPIC_Pos 2 /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_RXSTPIC (_U_(0x1) << DEVEPTICR_INTRPT_RXSTPIC_Pos) /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_NAKOUTIC_Pos 3 /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_NAKOUTIC (_U_(0x1) << DEVEPTICR_INTRPT_NAKOUTIC_Pos) /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_NAKINIC_Pos 4 /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_NAKINIC (_U_(0x1) << DEVEPTICR_INTRPT_NAKINIC_Pos) /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_STALLEDIC_Pos 6 /**< (DEVEPTICR) STALLed Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_STALLEDIC (_U_(0x1) << DEVEPTICR_INTRPT_STALLEDIC_Pos) /**< (DEVEPTICR) STALLed Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_Msk _U_(0x5C) /**< (DEVEPTICR_INTRPT) Register Mask */ - - -/* -------- DEVEPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */ - -#define DEVEPTIFR_OFFSET (0x190) /**< (DEVEPTIFR) Device Endpoint Interrupt Set Register Offset */ - -#define DEVEPTIFR_TXINIS_Pos 0 /**< (DEVEPTIFR) Transmitted IN Data Interrupt Set Position */ -#define DEVEPTIFR_TXINIS (_U_(0x1) << DEVEPTIFR_TXINIS_Pos) /**< (DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */ -#define DEVEPTIFR_RXOUTIS_Pos 1 /**< (DEVEPTIFR) Received OUT Data Interrupt Set Position */ -#define DEVEPTIFR_RXOUTIS (_U_(0x1) << DEVEPTIFR_RXOUTIS_Pos) /**< (DEVEPTIFR) Received OUT Data Interrupt Set Mask */ -#define DEVEPTIFR_OVERFIS_Pos 5 /**< (DEVEPTIFR) Overflow Interrupt Set Position */ -#define DEVEPTIFR_OVERFIS (_U_(0x1) << DEVEPTIFR_OVERFIS_Pos) /**< (DEVEPTIFR) Overflow Interrupt Set Mask */ -#define DEVEPTIFR_SHORTPACKETS_Pos 7 /**< (DEVEPTIFR) Short Packet Interrupt Set Position */ -#define DEVEPTIFR_SHORTPACKETS (_U_(0x1) << DEVEPTIFR_SHORTPACKETS_Pos) /**< (DEVEPTIFR) Short Packet Interrupt Set Mask */ -#define DEVEPTIFR_NBUSYBKS_Pos 12 /**< (DEVEPTIFR) Number of Busy Banks Interrupt Set Position */ -#define DEVEPTIFR_NBUSYBKS (_U_(0x1) << DEVEPTIFR_NBUSYBKS_Pos) /**< (DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */ -#define DEVEPTIFR_Msk _U_(0x10A3) /**< (DEVEPTIFR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIFR_CTRL_RXSTPIS_Pos 2 /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */ -#define DEVEPTIFR_CTRL_RXSTPIS (_U_(0x1) << DEVEPTIFR_CTRL_RXSTPIS_Pos) /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_NAKOUTIS_Pos 3 /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */ -#define DEVEPTIFR_CTRL_NAKOUTIS (_U_(0x1) << DEVEPTIFR_CTRL_NAKOUTIS_Pos) /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_NAKINIS_Pos 4 /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */ -#define DEVEPTIFR_CTRL_NAKINIS (_U_(0x1) << DEVEPTIFR_CTRL_NAKINIS_Pos) /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_STALLEDIS_Pos 6 /**< (DEVEPTIFR) STALLed Interrupt Set Position */ -#define DEVEPTIFR_CTRL_STALLEDIS (_U_(0x1) << DEVEPTIFR_CTRL_STALLEDIS_Pos) /**< (DEVEPTIFR) STALLed Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_Msk _U_(0x5C) /**< (DEVEPTIFR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIFR_ISO_UNDERFIS_Pos 2 /**< (DEVEPTIFR) Underflow Interrupt Set Position */ -#define DEVEPTIFR_ISO_UNDERFIS (_U_(0x1) << DEVEPTIFR_ISO_UNDERFIS_Pos) /**< (DEVEPTIFR) Underflow Interrupt Set Mask */ -#define DEVEPTIFR_ISO_HBISOINERRIS_Pos 3 /**< (DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */ -#define DEVEPTIFR_ISO_HBISOINERRIS (_U_(0x1) << DEVEPTIFR_ISO_HBISOINERRIS_Pos) /**< (DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */ -#define DEVEPTIFR_ISO_HBISOFLUSHIS_Pos 4 /**< (DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */ -#define DEVEPTIFR_ISO_HBISOFLUSHIS (_U_(0x1) << DEVEPTIFR_ISO_HBISOFLUSHIS_Pos) /**< (DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */ -#define DEVEPTIFR_ISO_CRCERRIS_Pos 6 /**< (DEVEPTIFR) CRC Error Interrupt Set Position */ -#define DEVEPTIFR_ISO_CRCERRIS (_U_(0x1) << DEVEPTIFR_ISO_CRCERRIS_Pos) /**< (DEVEPTIFR) CRC Error Interrupt Set Mask */ -#define DEVEPTIFR_ISO_Msk _U_(0x5C) /**< (DEVEPTIFR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIFR_BLK_RXSTPIS_Pos 2 /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */ -#define DEVEPTIFR_BLK_RXSTPIS (_U_(0x1) << DEVEPTIFR_BLK_RXSTPIS_Pos) /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */ -#define DEVEPTIFR_BLK_NAKOUTIS_Pos 3 /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */ -#define DEVEPTIFR_BLK_NAKOUTIS (_U_(0x1) << DEVEPTIFR_BLK_NAKOUTIS_Pos) /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */ -#define DEVEPTIFR_BLK_NAKINIS_Pos 4 /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */ -#define DEVEPTIFR_BLK_NAKINIS (_U_(0x1) << DEVEPTIFR_BLK_NAKINIS_Pos) /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */ -#define DEVEPTIFR_BLK_STALLEDIS_Pos 6 /**< (DEVEPTIFR) STALLed Interrupt Set Position */ -#define DEVEPTIFR_BLK_STALLEDIS (_U_(0x1) << DEVEPTIFR_BLK_STALLEDIS_Pos) /**< (DEVEPTIFR) STALLed Interrupt Set Mask */ -#define DEVEPTIFR_BLK_Msk _U_(0x5C) /**< (DEVEPTIFR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIFR_INTRPT_RXSTPIS_Pos 2 /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_RXSTPIS (_U_(0x1) << DEVEPTIFR_INTRPT_RXSTPIS_Pos) /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_NAKOUTIS_Pos 3 /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_NAKOUTIS (_U_(0x1) << DEVEPTIFR_INTRPT_NAKOUTIS_Pos) /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_NAKINIS_Pos 4 /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_NAKINIS (_U_(0x1) << DEVEPTIFR_INTRPT_NAKINIS_Pos) /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_STALLEDIS_Pos 6 /**< (DEVEPTIFR) STALLed Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_STALLEDIS (_U_(0x1) << DEVEPTIFR_INTRPT_STALLEDIS_Pos) /**< (DEVEPTIFR) STALLed Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_Msk _U_(0x5C) /**< (DEVEPTIFR_INTRPT) Register Mask */ - - -/* -------- DEVEPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */ - -#define DEVEPTIMR_OFFSET (0x1C0) /**< (DEVEPTIMR) Device Endpoint Interrupt Mask Register Offset */ - -#define DEVEPTIMR_TXINE_Pos 0 /**< (DEVEPTIMR) Transmitted IN Data Interrupt Position */ -#define DEVEPTIMR_TXINE (_U_(0x1) << DEVEPTIMR_TXINE_Pos) /**< (DEVEPTIMR) Transmitted IN Data Interrupt Mask */ -#define DEVEPTIMR_RXOUTE_Pos 1 /**< (DEVEPTIMR) Received OUT Data Interrupt Position */ -#define DEVEPTIMR_RXOUTE (_U_(0x1) << DEVEPTIMR_RXOUTE_Pos) /**< (DEVEPTIMR) Received OUT Data Interrupt Mask */ -#define DEVEPTIMR_OVERFE_Pos 5 /**< (DEVEPTIMR) Overflow Interrupt Position */ -#define DEVEPTIMR_OVERFE (_U_(0x1) << DEVEPTIMR_OVERFE_Pos) /**< (DEVEPTIMR) Overflow Interrupt Mask */ -#define DEVEPTIMR_SHORTPACKETE_Pos 7 /**< (DEVEPTIMR) Short Packet Interrupt Position */ -#define DEVEPTIMR_SHORTPACKETE (_U_(0x1) << DEVEPTIMR_SHORTPACKETE_Pos) /**< (DEVEPTIMR) Short Packet Interrupt Mask */ -#define DEVEPTIMR_NBUSYBKE_Pos 12 /**< (DEVEPTIMR) Number of Busy Banks Interrupt Position */ -#define DEVEPTIMR_NBUSYBKE (_U_(0x1) << DEVEPTIMR_NBUSYBKE_Pos) /**< (DEVEPTIMR) Number of Busy Banks Interrupt Mask */ -#define DEVEPTIMR_KILLBK_Pos 13 /**< (DEVEPTIMR) Kill IN Bank Position */ -#define DEVEPTIMR_KILLBK (_U_(0x1) << DEVEPTIMR_KILLBK_Pos) /**< (DEVEPTIMR) Kill IN Bank Mask */ -#define DEVEPTIMR_FIFOCON_Pos 14 /**< (DEVEPTIMR) FIFO Control Position */ -#define DEVEPTIMR_FIFOCON (_U_(0x1) << DEVEPTIMR_FIFOCON_Pos) /**< (DEVEPTIMR) FIFO Control Mask */ -#define DEVEPTIMR_EPDISHDMA_Pos 16 /**< (DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */ -#define DEVEPTIMR_EPDISHDMA (_U_(0x1) << DEVEPTIMR_EPDISHDMA_Pos) /**< (DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ -#define DEVEPTIMR_RSTDT_Pos 18 /**< (DEVEPTIMR) Reset Data Toggle Position */ -#define DEVEPTIMR_RSTDT (_U_(0x1) << DEVEPTIMR_RSTDT_Pos) /**< (DEVEPTIMR) Reset Data Toggle Mask */ -#define DEVEPTIMR_Msk _U_(0x570A3) /**< (DEVEPTIMR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIMR_CTRL_RXSTPE_Pos 2 /**< (DEVEPTIMR) Received SETUP Interrupt Position */ -#define DEVEPTIMR_CTRL_RXSTPE (_U_(0x1) << DEVEPTIMR_CTRL_RXSTPE_Pos) /**< (DEVEPTIMR) Received SETUP Interrupt Mask */ -#define DEVEPTIMR_CTRL_NAKOUTE_Pos 3 /**< (DEVEPTIMR) NAKed OUT Interrupt Position */ -#define DEVEPTIMR_CTRL_NAKOUTE (_U_(0x1) << DEVEPTIMR_CTRL_NAKOUTE_Pos) /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */ -#define DEVEPTIMR_CTRL_NAKINE_Pos 4 /**< (DEVEPTIMR) NAKed IN Interrupt Position */ -#define DEVEPTIMR_CTRL_NAKINE (_U_(0x1) << DEVEPTIMR_CTRL_NAKINE_Pos) /**< (DEVEPTIMR) NAKed IN Interrupt Mask */ -#define DEVEPTIMR_CTRL_STALLEDE_Pos 6 /**< (DEVEPTIMR) STALLed Interrupt Position */ -#define DEVEPTIMR_CTRL_STALLEDE (_U_(0x1) << DEVEPTIMR_CTRL_STALLEDE_Pos) /**< (DEVEPTIMR) STALLed Interrupt Mask */ -#define DEVEPTIMR_CTRL_NYETDIS_Pos 17 /**< (DEVEPTIMR) NYET Token Disable Position */ -#define DEVEPTIMR_CTRL_NYETDIS (_U_(0x1) << DEVEPTIMR_CTRL_NYETDIS_Pos) /**< (DEVEPTIMR) NYET Token Disable Mask */ -#define DEVEPTIMR_CTRL_STALLRQ_Pos 19 /**< (DEVEPTIMR) STALL Request Position */ -#define DEVEPTIMR_CTRL_STALLRQ (_U_(0x1) << DEVEPTIMR_CTRL_STALLRQ_Pos) /**< (DEVEPTIMR) STALL Request Mask */ -#define DEVEPTIMR_CTRL_Msk _U_(0xA005C) /**< (DEVEPTIMR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIMR_ISO_UNDERFE_Pos 2 /**< (DEVEPTIMR) Underflow Interrupt Position */ -#define DEVEPTIMR_ISO_UNDERFE (_U_(0x1) << DEVEPTIMR_ISO_UNDERFE_Pos) /**< (DEVEPTIMR) Underflow Interrupt Mask */ -#define DEVEPTIMR_ISO_HBISOINERRE_Pos 3 /**< (DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ -#define DEVEPTIMR_ISO_HBISOINERRE (_U_(0x1) << DEVEPTIMR_ISO_HBISOINERRE_Pos) /**< (DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ -#define DEVEPTIMR_ISO_HBISOFLUSHE_Pos 4 /**< (DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */ -#define DEVEPTIMR_ISO_HBISOFLUSHE (_U_(0x1) << DEVEPTIMR_ISO_HBISOFLUSHE_Pos) /**< (DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */ -#define DEVEPTIMR_ISO_CRCERRE_Pos 6 /**< (DEVEPTIMR) CRC Error Interrupt Position */ -#define DEVEPTIMR_ISO_CRCERRE (_U_(0x1) << DEVEPTIMR_ISO_CRCERRE_Pos) /**< (DEVEPTIMR) CRC Error Interrupt Mask */ -#define DEVEPTIMR_ISO_MDATAE_Pos 8 /**< (DEVEPTIMR) MData Interrupt Position */ -#define DEVEPTIMR_ISO_MDATAE (_U_(0x1) << DEVEPTIMR_ISO_MDATAE_Pos) /**< (DEVEPTIMR) MData Interrupt Mask */ -#define DEVEPTIMR_ISO_DATAXE_Pos 9 /**< (DEVEPTIMR) DataX Interrupt Position */ -#define DEVEPTIMR_ISO_DATAXE (_U_(0x1) << DEVEPTIMR_ISO_DATAXE_Pos) /**< (DEVEPTIMR) DataX Interrupt Mask */ -#define DEVEPTIMR_ISO_ERRORTRANSE_Pos 10 /**< (DEVEPTIMR) Transaction Error Interrupt Position */ -#define DEVEPTIMR_ISO_ERRORTRANSE (_U_(0x1) << DEVEPTIMR_ISO_ERRORTRANSE_Pos) /**< (DEVEPTIMR) Transaction Error Interrupt Mask */ -#define DEVEPTIMR_ISO_Msk _U_(0x75C) /**< (DEVEPTIMR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIMR_BLK_RXSTPE_Pos 2 /**< (DEVEPTIMR) Received SETUP Interrupt Position */ -#define DEVEPTIMR_BLK_RXSTPE (_U_(0x1) << DEVEPTIMR_BLK_RXSTPE_Pos) /**< (DEVEPTIMR) Received SETUP Interrupt Mask */ -#define DEVEPTIMR_BLK_NAKOUTE_Pos 3 /**< (DEVEPTIMR) NAKed OUT Interrupt Position */ -#define DEVEPTIMR_BLK_NAKOUTE (_U_(0x1) << DEVEPTIMR_BLK_NAKOUTE_Pos) /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */ -#define DEVEPTIMR_BLK_NAKINE_Pos 4 /**< (DEVEPTIMR) NAKed IN Interrupt Position */ -#define DEVEPTIMR_BLK_NAKINE (_U_(0x1) << DEVEPTIMR_BLK_NAKINE_Pos) /**< (DEVEPTIMR) NAKed IN Interrupt Mask */ -#define DEVEPTIMR_BLK_STALLEDE_Pos 6 /**< (DEVEPTIMR) STALLed Interrupt Position */ -#define DEVEPTIMR_BLK_STALLEDE (_U_(0x1) << DEVEPTIMR_BLK_STALLEDE_Pos) /**< (DEVEPTIMR) STALLed Interrupt Mask */ -#define DEVEPTIMR_BLK_NYETDIS_Pos 17 /**< (DEVEPTIMR) NYET Token Disable Position */ -#define DEVEPTIMR_BLK_NYETDIS (_U_(0x1) << DEVEPTIMR_BLK_NYETDIS_Pos) /**< (DEVEPTIMR) NYET Token Disable Mask */ -#define DEVEPTIMR_BLK_STALLRQ_Pos 19 /**< (DEVEPTIMR) STALL Request Position */ -#define DEVEPTIMR_BLK_STALLRQ (_U_(0x1) << DEVEPTIMR_BLK_STALLRQ_Pos) /**< (DEVEPTIMR) STALL Request Mask */ -#define DEVEPTIMR_BLK_Msk _U_(0xA005C) /**< (DEVEPTIMR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIMR_INTRPT_RXSTPE_Pos 2 /**< (DEVEPTIMR) Received SETUP Interrupt Position */ -#define DEVEPTIMR_INTRPT_RXSTPE (_U_(0x1) << DEVEPTIMR_INTRPT_RXSTPE_Pos) /**< (DEVEPTIMR) Received SETUP Interrupt Mask */ -#define DEVEPTIMR_INTRPT_NAKOUTE_Pos 3 /**< (DEVEPTIMR) NAKed OUT Interrupt Position */ -#define DEVEPTIMR_INTRPT_NAKOUTE (_U_(0x1) << DEVEPTIMR_INTRPT_NAKOUTE_Pos) /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */ -#define DEVEPTIMR_INTRPT_NAKINE_Pos 4 /**< (DEVEPTIMR) NAKed IN Interrupt Position */ -#define DEVEPTIMR_INTRPT_NAKINE (_U_(0x1) << DEVEPTIMR_INTRPT_NAKINE_Pos) /**< (DEVEPTIMR) NAKed IN Interrupt Mask */ -#define DEVEPTIMR_INTRPT_STALLEDE_Pos 6 /**< (DEVEPTIMR) STALLed Interrupt Position */ -#define DEVEPTIMR_INTRPT_STALLEDE (_U_(0x1) << DEVEPTIMR_INTRPT_STALLEDE_Pos) /**< (DEVEPTIMR) STALLed Interrupt Mask */ -#define DEVEPTIMR_INTRPT_NYETDIS_Pos 17 /**< (DEVEPTIMR) NYET Token Disable Position */ -#define DEVEPTIMR_INTRPT_NYETDIS (_U_(0x1) << DEVEPTIMR_INTRPT_NYETDIS_Pos) /**< (DEVEPTIMR) NYET Token Disable Mask */ -#define DEVEPTIMR_INTRPT_STALLRQ_Pos 19 /**< (DEVEPTIMR) STALL Request Position */ -#define DEVEPTIMR_INTRPT_STALLRQ (_U_(0x1) << DEVEPTIMR_INTRPT_STALLRQ_Pos) /**< (DEVEPTIMR) STALL Request Mask */ -#define DEVEPTIMR_INTRPT_Msk _U_(0xA005C) /**< (DEVEPTIMR_INTRPT) Register Mask */ - - -/* -------- DEVEPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */ - -#define DEVEPTIER_OFFSET (0x1F0) /**< (DEVEPTIER) Device Endpoint Interrupt Enable Register Offset */ - -#define DEVEPTIER_TXINES_Pos 0 /**< (DEVEPTIER) Transmitted IN Data Interrupt Enable Position */ -#define DEVEPTIER_TXINES (_U_(0x1) << DEVEPTIER_TXINES_Pos) /**< (DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */ -#define DEVEPTIER_RXOUTES_Pos 1 /**< (DEVEPTIER) Received OUT Data Interrupt Enable Position */ -#define DEVEPTIER_RXOUTES (_U_(0x1) << DEVEPTIER_RXOUTES_Pos) /**< (DEVEPTIER) Received OUT Data Interrupt Enable Mask */ -#define DEVEPTIER_OVERFES_Pos 5 /**< (DEVEPTIER) Overflow Interrupt Enable Position */ -#define DEVEPTIER_OVERFES (_U_(0x1) << DEVEPTIER_OVERFES_Pos) /**< (DEVEPTIER) Overflow Interrupt Enable Mask */ -#define DEVEPTIER_SHORTPACKETES_Pos 7 /**< (DEVEPTIER) Short Packet Interrupt Enable Position */ -#define DEVEPTIER_SHORTPACKETES (_U_(0x1) << DEVEPTIER_SHORTPACKETES_Pos) /**< (DEVEPTIER) Short Packet Interrupt Enable Mask */ -#define DEVEPTIER_NBUSYBKES_Pos 12 /**< (DEVEPTIER) Number of Busy Banks Interrupt Enable Position */ -#define DEVEPTIER_NBUSYBKES (_U_(0x1) << DEVEPTIER_NBUSYBKES_Pos) /**< (DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */ -#define DEVEPTIER_KILLBKS_Pos 13 /**< (DEVEPTIER) Kill IN Bank Position */ -#define DEVEPTIER_KILLBKS (_U_(0x1) << DEVEPTIER_KILLBKS_Pos) /**< (DEVEPTIER) Kill IN Bank Mask */ -#define DEVEPTIER_FIFOCONS_Pos 14 /**< (DEVEPTIER) FIFO Control Position */ -#define DEVEPTIER_FIFOCONS (_U_(0x1) << DEVEPTIER_FIFOCONS_Pos) /**< (DEVEPTIER) FIFO Control Mask */ -#define DEVEPTIER_EPDISHDMAS_Pos 16 /**< (DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ -#define DEVEPTIER_EPDISHDMAS (_U_(0x1) << DEVEPTIER_EPDISHDMAS_Pos) /**< (DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ -#define DEVEPTIER_RSTDTS_Pos 18 /**< (DEVEPTIER) Reset Data Toggle Enable Position */ -#define DEVEPTIER_RSTDTS (_U_(0x1) << DEVEPTIER_RSTDTS_Pos) /**< (DEVEPTIER) Reset Data Toggle Enable Mask */ -#define DEVEPTIER_Msk _U_(0x570A3) /**< (DEVEPTIER) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIER_CTRL_RXSTPES_Pos 2 /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */ -#define DEVEPTIER_CTRL_RXSTPES (_U_(0x1) << DEVEPTIER_CTRL_RXSTPES_Pos) /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_NAKOUTES_Pos 3 /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */ -#define DEVEPTIER_CTRL_NAKOUTES (_U_(0x1) << DEVEPTIER_CTRL_NAKOUTES_Pos) /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_NAKINES_Pos 4 /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */ -#define DEVEPTIER_CTRL_NAKINES (_U_(0x1) << DEVEPTIER_CTRL_NAKINES_Pos) /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_STALLEDES_Pos 6 /**< (DEVEPTIER) STALLed Interrupt Enable Position */ -#define DEVEPTIER_CTRL_STALLEDES (_U_(0x1) << DEVEPTIER_CTRL_STALLEDES_Pos) /**< (DEVEPTIER) STALLed Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_NYETDISS_Pos 17 /**< (DEVEPTIER) NYET Token Disable Enable Position */ -#define DEVEPTIER_CTRL_NYETDISS (_U_(0x1) << DEVEPTIER_CTRL_NYETDISS_Pos) /**< (DEVEPTIER) NYET Token Disable Enable Mask */ -#define DEVEPTIER_CTRL_STALLRQS_Pos 19 /**< (DEVEPTIER) STALL Request Enable Position */ -#define DEVEPTIER_CTRL_STALLRQS (_U_(0x1) << DEVEPTIER_CTRL_STALLRQS_Pos) /**< (DEVEPTIER) STALL Request Enable Mask */ -#define DEVEPTIER_CTRL_Msk _U_(0xA005C) /**< (DEVEPTIER_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIER_ISO_UNDERFES_Pos 2 /**< (DEVEPTIER) Underflow Interrupt Enable Position */ -#define DEVEPTIER_ISO_UNDERFES (_U_(0x1) << DEVEPTIER_ISO_UNDERFES_Pos) /**< (DEVEPTIER) Underflow Interrupt Enable Mask */ -#define DEVEPTIER_ISO_HBISOINERRES_Pos 3 /**< (DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */ -#define DEVEPTIER_ISO_HBISOINERRES (_U_(0x1) << DEVEPTIER_ISO_HBISOINERRES_Pos) /**< (DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */ -#define DEVEPTIER_ISO_HBISOFLUSHES_Pos 4 /**< (DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */ -#define DEVEPTIER_ISO_HBISOFLUSHES (_U_(0x1) << DEVEPTIER_ISO_HBISOFLUSHES_Pos) /**< (DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */ -#define DEVEPTIER_ISO_CRCERRES_Pos 6 /**< (DEVEPTIER) CRC Error Interrupt Enable Position */ -#define DEVEPTIER_ISO_CRCERRES (_U_(0x1) << DEVEPTIER_ISO_CRCERRES_Pos) /**< (DEVEPTIER) CRC Error Interrupt Enable Mask */ -#define DEVEPTIER_ISO_MDATAES_Pos 8 /**< (DEVEPTIER) MData Interrupt Enable Position */ -#define DEVEPTIER_ISO_MDATAES (_U_(0x1) << DEVEPTIER_ISO_MDATAES_Pos) /**< (DEVEPTIER) MData Interrupt Enable Mask */ -#define DEVEPTIER_ISO_DATAXES_Pos 9 /**< (DEVEPTIER) DataX Interrupt Enable Position */ -#define DEVEPTIER_ISO_DATAXES (_U_(0x1) << DEVEPTIER_ISO_DATAXES_Pos) /**< (DEVEPTIER) DataX Interrupt Enable Mask */ -#define DEVEPTIER_ISO_ERRORTRANSES_Pos 10 /**< (DEVEPTIER) Transaction Error Interrupt Enable Position */ -#define DEVEPTIER_ISO_ERRORTRANSES (_U_(0x1) << DEVEPTIER_ISO_ERRORTRANSES_Pos) /**< (DEVEPTIER) Transaction Error Interrupt Enable Mask */ -#define DEVEPTIER_ISO_Msk _U_(0x75C) /**< (DEVEPTIER_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIER_BLK_RXSTPES_Pos 2 /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */ -#define DEVEPTIER_BLK_RXSTPES (_U_(0x1) << DEVEPTIER_BLK_RXSTPES_Pos) /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */ -#define DEVEPTIER_BLK_NAKOUTES_Pos 3 /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */ -#define DEVEPTIER_BLK_NAKOUTES (_U_(0x1) << DEVEPTIER_BLK_NAKOUTES_Pos) /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */ -#define DEVEPTIER_BLK_NAKINES_Pos 4 /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */ -#define DEVEPTIER_BLK_NAKINES (_U_(0x1) << DEVEPTIER_BLK_NAKINES_Pos) /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */ -#define DEVEPTIER_BLK_STALLEDES_Pos 6 /**< (DEVEPTIER) STALLed Interrupt Enable Position */ -#define DEVEPTIER_BLK_STALLEDES (_U_(0x1) << DEVEPTIER_BLK_STALLEDES_Pos) /**< (DEVEPTIER) STALLed Interrupt Enable Mask */ -#define DEVEPTIER_BLK_NYETDISS_Pos 17 /**< (DEVEPTIER) NYET Token Disable Enable Position */ -#define DEVEPTIER_BLK_NYETDISS (_U_(0x1) << DEVEPTIER_BLK_NYETDISS_Pos) /**< (DEVEPTIER) NYET Token Disable Enable Mask */ -#define DEVEPTIER_BLK_STALLRQS_Pos 19 /**< (DEVEPTIER) STALL Request Enable Position */ -#define DEVEPTIER_BLK_STALLRQS (_U_(0x1) << DEVEPTIER_BLK_STALLRQS_Pos) /**< (DEVEPTIER) STALL Request Enable Mask */ -#define DEVEPTIER_BLK_Msk _U_(0xA005C) /**< (DEVEPTIER_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIER_INTRPT_RXSTPES_Pos 2 /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_RXSTPES (_U_(0x1) << DEVEPTIER_INTRPT_RXSTPES_Pos) /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_NAKOUTES_Pos 3 /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_NAKOUTES (_U_(0x1) << DEVEPTIER_INTRPT_NAKOUTES_Pos) /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_NAKINES_Pos 4 /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_NAKINES (_U_(0x1) << DEVEPTIER_INTRPT_NAKINES_Pos) /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_STALLEDES_Pos 6 /**< (DEVEPTIER) STALLed Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_STALLEDES (_U_(0x1) << DEVEPTIER_INTRPT_STALLEDES_Pos) /**< (DEVEPTIER) STALLed Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_NYETDISS_Pos 17 /**< (DEVEPTIER) NYET Token Disable Enable Position */ -#define DEVEPTIER_INTRPT_NYETDISS (_U_(0x1) << DEVEPTIER_INTRPT_NYETDISS_Pos) /**< (DEVEPTIER) NYET Token Disable Enable Mask */ -#define DEVEPTIER_INTRPT_STALLRQS_Pos 19 /**< (DEVEPTIER) STALL Request Enable Position */ -#define DEVEPTIER_INTRPT_STALLRQS (_U_(0x1) << DEVEPTIER_INTRPT_STALLRQS_Pos) /**< (DEVEPTIER) STALL Request Enable Mask */ -#define DEVEPTIER_INTRPT_Msk _U_(0xA005C) /**< (DEVEPTIER_INTRPT) Register Mask */ - - -/* -------- DEVEPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */ - -#define DEVEPTIDR_OFFSET (0x220) /**< (DEVEPTIDR) Device Endpoint Interrupt Disable Register Offset */ - -#define DEVEPTIDR_TXINEC_Pos 0 /**< (DEVEPTIDR) Transmitted IN Interrupt Clear Position */ -#define DEVEPTIDR_TXINEC (_U_(0x1) << DEVEPTIDR_TXINEC_Pos) /**< (DEVEPTIDR) Transmitted IN Interrupt Clear Mask */ -#define DEVEPTIDR_RXOUTEC_Pos 1 /**< (DEVEPTIDR) Received OUT Data Interrupt Clear Position */ -#define DEVEPTIDR_RXOUTEC (_U_(0x1) << DEVEPTIDR_RXOUTEC_Pos) /**< (DEVEPTIDR) Received OUT Data Interrupt Clear Mask */ -#define DEVEPTIDR_OVERFEC_Pos 5 /**< (DEVEPTIDR) Overflow Interrupt Clear Position */ -#define DEVEPTIDR_OVERFEC (_U_(0x1) << DEVEPTIDR_OVERFEC_Pos) /**< (DEVEPTIDR) Overflow Interrupt Clear Mask */ -#define DEVEPTIDR_SHORTPACKETEC_Pos 7 /**< (DEVEPTIDR) Shortpacket Interrupt Clear Position */ -#define DEVEPTIDR_SHORTPACKETEC (_U_(0x1) << DEVEPTIDR_SHORTPACKETEC_Pos) /**< (DEVEPTIDR) Shortpacket Interrupt Clear Mask */ -#define DEVEPTIDR_NBUSYBKEC_Pos 12 /**< (DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */ -#define DEVEPTIDR_NBUSYBKEC (_U_(0x1) << DEVEPTIDR_NBUSYBKEC_Pos) /**< (DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */ -#define DEVEPTIDR_FIFOCONC_Pos 14 /**< (DEVEPTIDR) FIFO Control Clear Position */ -#define DEVEPTIDR_FIFOCONC (_U_(0x1) << DEVEPTIDR_FIFOCONC_Pos) /**< (DEVEPTIDR) FIFO Control Clear Mask */ -#define DEVEPTIDR_EPDISHDMAC_Pos 16 /**< (DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ -#define DEVEPTIDR_EPDISHDMAC (_U_(0x1) << DEVEPTIDR_EPDISHDMAC_Pos) /**< (DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ -#define DEVEPTIDR_Msk _U_(0x150A3) /**< (DEVEPTIDR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIDR_CTRL_RXSTPEC_Pos 2 /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_RXSTPEC (_U_(0x1) << DEVEPTIDR_CTRL_RXSTPEC_Pos) /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_NAKOUTEC_Pos 3 /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_NAKOUTEC (_U_(0x1) << DEVEPTIDR_CTRL_NAKOUTEC_Pos) /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_NAKINEC_Pos 4 /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_NAKINEC (_U_(0x1) << DEVEPTIDR_CTRL_NAKINEC_Pos) /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_STALLEDEC_Pos 6 /**< (DEVEPTIDR) STALLed Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_STALLEDEC (_U_(0x1) << DEVEPTIDR_CTRL_STALLEDEC_Pos) /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_NYETDISC_Pos 17 /**< (DEVEPTIDR) NYET Token Disable Clear Position */ -#define DEVEPTIDR_CTRL_NYETDISC (_U_(0x1) << DEVEPTIDR_CTRL_NYETDISC_Pos) /**< (DEVEPTIDR) NYET Token Disable Clear Mask */ -#define DEVEPTIDR_CTRL_STALLRQC_Pos 19 /**< (DEVEPTIDR) STALL Request Clear Position */ -#define DEVEPTIDR_CTRL_STALLRQC (_U_(0x1) << DEVEPTIDR_CTRL_STALLRQC_Pos) /**< (DEVEPTIDR) STALL Request Clear Mask */ -#define DEVEPTIDR_CTRL_Msk _U_(0xA005C) /**< (DEVEPTIDR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIDR_ISO_UNDERFEC_Pos 2 /**< (DEVEPTIDR) Underflow Interrupt Clear Position */ -#define DEVEPTIDR_ISO_UNDERFEC (_U_(0x1) << DEVEPTIDR_ISO_UNDERFEC_Pos) /**< (DEVEPTIDR) Underflow Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_HBISOINERREC_Pos 3 /**< (DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ -#define DEVEPTIDR_ISO_HBISOINERREC (_U_(0x1) << DEVEPTIDR_ISO_HBISOINERREC_Pos) /**< (DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_HBISOFLUSHEC_Pos 4 /**< (DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ -#define DEVEPTIDR_ISO_HBISOFLUSHEC (_U_(0x1) << DEVEPTIDR_ISO_HBISOFLUSHEC_Pos) /**< (DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_MDATAEC_Pos 8 /**< (DEVEPTIDR) MData Interrupt Clear Position */ -#define DEVEPTIDR_ISO_MDATAEC (_U_(0x1) << DEVEPTIDR_ISO_MDATAEC_Pos) /**< (DEVEPTIDR) MData Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_DATAXEC_Pos 9 /**< (DEVEPTIDR) DataX Interrupt Clear Position */ -#define DEVEPTIDR_ISO_DATAXEC (_U_(0x1) << DEVEPTIDR_ISO_DATAXEC_Pos) /**< (DEVEPTIDR) DataX Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_ERRORTRANSEC_Pos 10 /**< (DEVEPTIDR) Transaction Error Interrupt Clear Position */ -#define DEVEPTIDR_ISO_ERRORTRANSEC (_U_(0x1) << DEVEPTIDR_ISO_ERRORTRANSEC_Pos) /**< (DEVEPTIDR) Transaction Error Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_Msk _U_(0x71C) /**< (DEVEPTIDR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIDR_BLK_RXSTPEC_Pos 2 /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */ -#define DEVEPTIDR_BLK_RXSTPEC (_U_(0x1) << DEVEPTIDR_BLK_RXSTPEC_Pos) /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_NAKOUTEC_Pos 3 /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTIDR_BLK_NAKOUTEC (_U_(0x1) << DEVEPTIDR_BLK_NAKOUTEC_Pos) /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_NAKINEC_Pos 4 /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */ -#define DEVEPTIDR_BLK_NAKINEC (_U_(0x1) << DEVEPTIDR_BLK_NAKINEC_Pos) /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_STALLEDEC_Pos 6 /**< (DEVEPTIDR) STALLed Interrupt Clear Position */ -#define DEVEPTIDR_BLK_STALLEDEC (_U_(0x1) << DEVEPTIDR_BLK_STALLEDEC_Pos) /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_NYETDISC_Pos 17 /**< (DEVEPTIDR) NYET Token Disable Clear Position */ -#define DEVEPTIDR_BLK_NYETDISC (_U_(0x1) << DEVEPTIDR_BLK_NYETDISC_Pos) /**< (DEVEPTIDR) NYET Token Disable Clear Mask */ -#define DEVEPTIDR_BLK_STALLRQC_Pos 19 /**< (DEVEPTIDR) STALL Request Clear Position */ -#define DEVEPTIDR_BLK_STALLRQC (_U_(0x1) << DEVEPTIDR_BLK_STALLRQC_Pos) /**< (DEVEPTIDR) STALL Request Clear Mask */ -#define DEVEPTIDR_BLK_Msk _U_(0xA005C) /**< (DEVEPTIDR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIDR_INTRPT_RXSTPEC_Pos 2 /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_RXSTPEC (_U_(0x1) << DEVEPTIDR_INTRPT_RXSTPEC_Pos) /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_NAKOUTEC_Pos 3 /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_NAKOUTEC (_U_(0x1) << DEVEPTIDR_INTRPT_NAKOUTEC_Pos) /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_NAKINEC_Pos 4 /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_NAKINEC (_U_(0x1) << DEVEPTIDR_INTRPT_NAKINEC_Pos) /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_STALLEDEC_Pos 6 /**< (DEVEPTIDR) STALLed Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_STALLEDEC (_U_(0x1) << DEVEPTIDR_INTRPT_STALLEDEC_Pos) /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_NYETDISC_Pos 17 /**< (DEVEPTIDR) NYET Token Disable Clear Position */ -#define DEVEPTIDR_INTRPT_NYETDISC (_U_(0x1) << DEVEPTIDR_INTRPT_NYETDISC_Pos) /**< (DEVEPTIDR) NYET Token Disable Clear Mask */ -#define DEVEPTIDR_INTRPT_STALLRQC_Pos 19 /**< (DEVEPTIDR) STALL Request Clear Position */ -#define DEVEPTIDR_INTRPT_STALLRQC (_U_(0x1) << DEVEPTIDR_INTRPT_STALLRQC_Pos) /**< (DEVEPTIDR) STALL Request Clear Mask */ -#define DEVEPTIDR_INTRPT_Msk _U_(0xA005C) /**< (DEVEPTIDR_INTRPT) Register Mask */ - - -/* -------- HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ - -#define HSTCTRL_OFFSET (0x400) /**< (HSTCTRL) Host General Control Register Offset */ - -#define HSTCTRL_SOFE_Pos 8 /**< (HSTCTRL) Start of Frame Generation Enable Position */ -#define HSTCTRL_SOFE (_U_(0x1) << HSTCTRL_SOFE_Pos) /**< (HSTCTRL) Start of Frame Generation Enable Mask */ -#define HSTCTRL_RESET_Pos 9 /**< (HSTCTRL) Send USB Reset Position */ -#define HSTCTRL_RESET (_U_(0x1) << HSTCTRL_RESET_Pos) /**< (HSTCTRL) Send USB Reset Mask */ -#define HSTCTRL_RESUME_Pos 10 /**< (HSTCTRL) Send USB Resume Position */ -#define HSTCTRL_RESUME (_U_(0x1) << HSTCTRL_RESUME_Pos) /**< (HSTCTRL) Send USB Resume Mask */ -#define HSTCTRL_SPDCONF_Pos 12 /**< (HSTCTRL) Mode Configuration Position */ -#define HSTCTRL_SPDCONF (_U_(0x3) << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) Mode Configuration Mask */ -#define HSTCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ -#define HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (HSTCTRL) For a better consumption, if high speed is not needed. */ -#define HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (HSTCTRL) Forced high speed. */ -#define HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ -#define HSTCTRL_SPDCONF_NORMAL (HSTCTRL_SPDCONF_NORMAL_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ -#define HSTCTRL_SPDCONF_LOW_POWER (HSTCTRL_SPDCONF_LOW_POWER_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) For a better consumption, if high speed is not needed. Position */ -#define HSTCTRL_SPDCONF_HIGH_SPEED (HSTCTRL_SPDCONF_HIGH_SPEED_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) Forced high speed. Position */ -#define HSTCTRL_SPDCONF_FORCED_FS (HSTCTRL_SPDCONF_FORCED_FS_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position */ -#define HSTCTRL_Msk _U_(0x3700) /**< (HSTCTRL) Register Mask */ - - -/* -------- HSTISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */ - -#define HSTISR_OFFSET (0x404) /**< (HSTISR) Host Global Interrupt Status Register Offset */ - -#define HSTISR_DCONNI_Pos 0 /**< (HSTISR) Device Connection Interrupt Position */ -#define HSTISR_DCONNI (_U_(0x1) << HSTISR_DCONNI_Pos) /**< (HSTISR) Device Connection Interrupt Mask */ -#define HSTISR_DDISCI_Pos 1 /**< (HSTISR) Device Disconnection Interrupt Position */ -#define HSTISR_DDISCI (_U_(0x1) << HSTISR_DDISCI_Pos) /**< (HSTISR) Device Disconnection Interrupt Mask */ -#define HSTISR_RSTI_Pos 2 /**< (HSTISR) USB Reset Sent Interrupt Position */ -#define HSTISR_RSTI (_U_(0x1) << HSTISR_RSTI_Pos) /**< (HSTISR) USB Reset Sent Interrupt Mask */ -#define HSTISR_RSMEDI_Pos 3 /**< (HSTISR) Downstream Resume Sent Interrupt Position */ -#define HSTISR_RSMEDI (_U_(0x1) << HSTISR_RSMEDI_Pos) /**< (HSTISR) Downstream Resume Sent Interrupt Mask */ -#define HSTISR_RXRSMI_Pos 4 /**< (HSTISR) Upstream Resume Received Interrupt Position */ -#define HSTISR_RXRSMI (_U_(0x1) << HSTISR_RXRSMI_Pos) /**< (HSTISR) Upstream Resume Received Interrupt Mask */ -#define HSTISR_HSOFI_Pos 5 /**< (HSTISR) Host Start of Frame Interrupt Position */ -#define HSTISR_HSOFI (_U_(0x1) << HSTISR_HSOFI_Pos) /**< (HSTISR) Host Start of Frame Interrupt Mask */ -#define HSTISR_HWUPI_Pos 6 /**< (HSTISR) Host Wake-Up Interrupt Position */ -#define HSTISR_HWUPI (_U_(0x1) << HSTISR_HWUPI_Pos) /**< (HSTISR) Host Wake-Up Interrupt Mask */ -#define HSTISR_PEP_0_Pos 8 /**< (HSTISR) Pipe 0 Interrupt Position */ -#define HSTISR_PEP_0 (_U_(0x1) << HSTISR_PEP_0_Pos) /**< (HSTISR) Pipe 0 Interrupt Mask */ -#define HSTISR_PEP_1_Pos 9 /**< (HSTISR) Pipe 1 Interrupt Position */ -#define HSTISR_PEP_1 (_U_(0x1) << HSTISR_PEP_1_Pos) /**< (HSTISR) Pipe 1 Interrupt Mask */ -#define HSTISR_PEP_2_Pos 10 /**< (HSTISR) Pipe 2 Interrupt Position */ -#define HSTISR_PEP_2 (_U_(0x1) << HSTISR_PEP_2_Pos) /**< (HSTISR) Pipe 2 Interrupt Mask */ -#define HSTISR_PEP_3_Pos 11 /**< (HSTISR) Pipe 3 Interrupt Position */ -#define HSTISR_PEP_3 (_U_(0x1) << HSTISR_PEP_3_Pos) /**< (HSTISR) Pipe 3 Interrupt Mask */ -#define HSTISR_PEP_4_Pos 12 /**< (HSTISR) Pipe 4 Interrupt Position */ -#define HSTISR_PEP_4 (_U_(0x1) << HSTISR_PEP_4_Pos) /**< (HSTISR) Pipe 4 Interrupt Mask */ -#define HSTISR_PEP_5_Pos 13 /**< (HSTISR) Pipe 5 Interrupt Position */ -#define HSTISR_PEP_5 (_U_(0x1) << HSTISR_PEP_5_Pos) /**< (HSTISR) Pipe 5 Interrupt Mask */ -#define HSTISR_PEP_6_Pos 14 /**< (HSTISR) Pipe 6 Interrupt Position */ -#define HSTISR_PEP_6 (_U_(0x1) << HSTISR_PEP_6_Pos) /**< (HSTISR) Pipe 6 Interrupt Mask */ -#define HSTISR_PEP_7_Pos 15 /**< (HSTISR) Pipe 7 Interrupt Position */ -#define HSTISR_PEP_7 (_U_(0x1) << HSTISR_PEP_7_Pos) /**< (HSTISR) Pipe 7 Interrupt Mask */ -#define HSTISR_PEP_8_Pos 16 /**< (HSTISR) Pipe 8 Interrupt Position */ -#define HSTISR_PEP_8 (_U_(0x1) << HSTISR_PEP_8_Pos) /**< (HSTISR) Pipe 8 Interrupt Mask */ -#define HSTISR_PEP_9_Pos 17 /**< (HSTISR) Pipe 9 Interrupt Position */ -#define HSTISR_PEP_9 (_U_(0x1) << HSTISR_PEP_9_Pos) /**< (HSTISR) Pipe 9 Interrupt Mask */ -#define HSTISR_DMA_0_Pos 25 /**< (HSTISR) DMA Channel 0 Interrupt Position */ -#define HSTISR_DMA_0 (_U_(0x1) << HSTISR_DMA_0_Pos) /**< (HSTISR) DMA Channel 0 Interrupt Mask */ -#define HSTISR_DMA_1_Pos 26 /**< (HSTISR) DMA Channel 1 Interrupt Position */ -#define HSTISR_DMA_1 (_U_(0x1) << HSTISR_DMA_1_Pos) /**< (HSTISR) DMA Channel 1 Interrupt Mask */ -#define HSTISR_DMA_2_Pos 27 /**< (HSTISR) DMA Channel 2 Interrupt Position */ -#define HSTISR_DMA_2 (_U_(0x1) << HSTISR_DMA_2_Pos) /**< (HSTISR) DMA Channel 2 Interrupt Mask */ -#define HSTISR_DMA_3_Pos 28 /**< (HSTISR) DMA Channel 3 Interrupt Position */ -#define HSTISR_DMA_3 (_U_(0x1) << HSTISR_DMA_3_Pos) /**< (HSTISR) DMA Channel 3 Interrupt Mask */ -#define HSTISR_DMA_4_Pos 29 /**< (HSTISR) DMA Channel 4 Interrupt Position */ -#define HSTISR_DMA_4 (_U_(0x1) << HSTISR_DMA_4_Pos) /**< (HSTISR) DMA Channel 4 Interrupt Mask */ -#define HSTISR_DMA_5_Pos 30 /**< (HSTISR) DMA Channel 5 Interrupt Position */ -#define HSTISR_DMA_5 (_U_(0x1) << HSTISR_DMA_5_Pos) /**< (HSTISR) DMA Channel 5 Interrupt Mask */ -#define HSTISR_DMA_6_Pos 31 /**< (HSTISR) DMA Channel 6 Interrupt Position */ -#define HSTISR_DMA_6 (_U_(0x1) << HSTISR_DMA_6_Pos) /**< (HSTISR) DMA Channel 6 Interrupt Mask */ -#define HSTISR_Msk _U_(0xFE03FF7F) /**< (HSTISR) Register Mask */ - -#define HSTISR_PEP__Pos 8 /**< (HSTISR Position) Pipe x Interrupt */ -#define HSTISR_PEP_ (_U_(0x3FF) << HSTISR_PEP__Pos) /**< (HSTISR Mask) PEP_ */ -#define HSTISR_DMA__Pos 25 /**< (HSTISR Position) DMA Channel 6 Interrupt */ -#define HSTISR_DMA_ (_U_(0x7F) << HSTISR_DMA__Pos) /**< (HSTISR Mask) DMA_ */ - -/* -------- HSTICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */ - -#define HSTICR_OFFSET (0x408) /**< (HSTICR) Host Global Interrupt Clear Register Offset */ - -#define HSTICR_DCONNIC_Pos 0 /**< (HSTICR) Device Connection Interrupt Clear Position */ -#define HSTICR_DCONNIC (_U_(0x1) << HSTICR_DCONNIC_Pos) /**< (HSTICR) Device Connection Interrupt Clear Mask */ -#define HSTICR_DDISCIC_Pos 1 /**< (HSTICR) Device Disconnection Interrupt Clear Position */ -#define HSTICR_DDISCIC (_U_(0x1) << HSTICR_DDISCIC_Pos) /**< (HSTICR) Device Disconnection Interrupt Clear Mask */ -#define HSTICR_RSTIC_Pos 2 /**< (HSTICR) USB Reset Sent Interrupt Clear Position */ -#define HSTICR_RSTIC (_U_(0x1) << HSTICR_RSTIC_Pos) /**< (HSTICR) USB Reset Sent Interrupt Clear Mask */ -#define HSTICR_RSMEDIC_Pos 3 /**< (HSTICR) Downstream Resume Sent Interrupt Clear Position */ -#define HSTICR_RSMEDIC (_U_(0x1) << HSTICR_RSMEDIC_Pos) /**< (HSTICR) Downstream Resume Sent Interrupt Clear Mask */ -#define HSTICR_RXRSMIC_Pos 4 /**< (HSTICR) Upstream Resume Received Interrupt Clear Position */ -#define HSTICR_RXRSMIC (_U_(0x1) << HSTICR_RXRSMIC_Pos) /**< (HSTICR) Upstream Resume Received Interrupt Clear Mask */ -#define HSTICR_HSOFIC_Pos 5 /**< (HSTICR) Host Start of Frame Interrupt Clear Position */ -#define HSTICR_HSOFIC (_U_(0x1) << HSTICR_HSOFIC_Pos) /**< (HSTICR) Host Start of Frame Interrupt Clear Mask */ -#define HSTICR_HWUPIC_Pos 6 /**< (HSTICR) Host Wake-Up Interrupt Clear Position */ -#define HSTICR_HWUPIC (_U_(0x1) << HSTICR_HWUPIC_Pos) /**< (HSTICR) Host Wake-Up Interrupt Clear Mask */ -#define HSTICR_Msk _U_(0x7F) /**< (HSTICR) Register Mask */ - - -/* -------- HSTIFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */ - -#define HSTIFR_OFFSET (0x40C) /**< (HSTIFR) Host Global Interrupt Set Register Offset */ - -#define HSTIFR_DCONNIS_Pos 0 /**< (HSTIFR) Device Connection Interrupt Set Position */ -#define HSTIFR_DCONNIS (_U_(0x1) << HSTIFR_DCONNIS_Pos) /**< (HSTIFR) Device Connection Interrupt Set Mask */ -#define HSTIFR_DDISCIS_Pos 1 /**< (HSTIFR) Device Disconnection Interrupt Set Position */ -#define HSTIFR_DDISCIS (_U_(0x1) << HSTIFR_DDISCIS_Pos) /**< (HSTIFR) Device Disconnection Interrupt Set Mask */ -#define HSTIFR_RSTIS_Pos 2 /**< (HSTIFR) USB Reset Sent Interrupt Set Position */ -#define HSTIFR_RSTIS (_U_(0x1) << HSTIFR_RSTIS_Pos) /**< (HSTIFR) USB Reset Sent Interrupt Set Mask */ -#define HSTIFR_RSMEDIS_Pos 3 /**< (HSTIFR) Downstream Resume Sent Interrupt Set Position */ -#define HSTIFR_RSMEDIS (_U_(0x1) << HSTIFR_RSMEDIS_Pos) /**< (HSTIFR) Downstream Resume Sent Interrupt Set Mask */ -#define HSTIFR_RXRSMIS_Pos 4 /**< (HSTIFR) Upstream Resume Received Interrupt Set Position */ -#define HSTIFR_RXRSMIS (_U_(0x1) << HSTIFR_RXRSMIS_Pos) /**< (HSTIFR) Upstream Resume Received Interrupt Set Mask */ -#define HSTIFR_HSOFIS_Pos 5 /**< (HSTIFR) Host Start of Frame Interrupt Set Position */ -#define HSTIFR_HSOFIS (_U_(0x1) << HSTIFR_HSOFIS_Pos) /**< (HSTIFR) Host Start of Frame Interrupt Set Mask */ -#define HSTIFR_HWUPIS_Pos 6 /**< (HSTIFR) Host Wake-Up Interrupt Set Position */ -#define HSTIFR_HWUPIS (_U_(0x1) << HSTIFR_HWUPIS_Pos) /**< (HSTIFR) Host Wake-Up Interrupt Set Mask */ -#define HSTIFR_DMA_0_Pos 25 /**< (HSTIFR) DMA Channel 0 Interrupt Set Position */ -#define HSTIFR_DMA_0 (_U_(0x1) << HSTIFR_DMA_0_Pos) /**< (HSTIFR) DMA Channel 0 Interrupt Set Mask */ -#define HSTIFR_DMA_1_Pos 26 /**< (HSTIFR) DMA Channel 1 Interrupt Set Position */ -#define HSTIFR_DMA_1 (_U_(0x1) << HSTIFR_DMA_1_Pos) /**< (HSTIFR) DMA Channel 1 Interrupt Set Mask */ -#define HSTIFR_DMA_2_Pos 27 /**< (HSTIFR) DMA Channel 2 Interrupt Set Position */ -#define HSTIFR_DMA_2 (_U_(0x1) << HSTIFR_DMA_2_Pos) /**< (HSTIFR) DMA Channel 2 Interrupt Set Mask */ -#define HSTIFR_DMA_3_Pos 28 /**< (HSTIFR) DMA Channel 3 Interrupt Set Position */ -#define HSTIFR_DMA_3 (_U_(0x1) << HSTIFR_DMA_3_Pos) /**< (HSTIFR) DMA Channel 3 Interrupt Set Mask */ -#define HSTIFR_DMA_4_Pos 29 /**< (HSTIFR) DMA Channel 4 Interrupt Set Position */ -#define HSTIFR_DMA_4 (_U_(0x1) << HSTIFR_DMA_4_Pos) /**< (HSTIFR) DMA Channel 4 Interrupt Set Mask */ -#define HSTIFR_DMA_5_Pos 30 /**< (HSTIFR) DMA Channel 5 Interrupt Set Position */ -#define HSTIFR_DMA_5 (_U_(0x1) << HSTIFR_DMA_5_Pos) /**< (HSTIFR) DMA Channel 5 Interrupt Set Mask */ -#define HSTIFR_DMA_6_Pos 31 /**< (HSTIFR) DMA Channel 6 Interrupt Set Position */ -#define HSTIFR_DMA_6 (_U_(0x1) << HSTIFR_DMA_6_Pos) /**< (HSTIFR) DMA Channel 6 Interrupt Set Mask */ -#define HSTIFR_Msk _U_(0xFE00007F) /**< (HSTIFR) Register Mask */ - -#define HSTIFR_DMA__Pos 25 /**< (HSTIFR Position) DMA Channel 6 Interrupt Set */ -#define HSTIFR_DMA_ (_U_(0x7F) << HSTIFR_DMA__Pos) /**< (HSTIFR Mask) DMA_ */ - -/* -------- HSTIMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */ - -#define HSTIMR_OFFSET (0x410) /**< (HSTIMR) Host Global Interrupt Mask Register Offset */ - -#define HSTIMR_DCONNIE_Pos 0 /**< (HSTIMR) Device Connection Interrupt Enable Position */ -#define HSTIMR_DCONNIE (_U_(0x1) << HSTIMR_DCONNIE_Pos) /**< (HSTIMR) Device Connection Interrupt Enable Mask */ -#define HSTIMR_DDISCIE_Pos 1 /**< (HSTIMR) Device Disconnection Interrupt Enable Position */ -#define HSTIMR_DDISCIE (_U_(0x1) << HSTIMR_DDISCIE_Pos) /**< (HSTIMR) Device Disconnection Interrupt Enable Mask */ -#define HSTIMR_RSTIE_Pos 2 /**< (HSTIMR) USB Reset Sent Interrupt Enable Position */ -#define HSTIMR_RSTIE (_U_(0x1) << HSTIMR_RSTIE_Pos) /**< (HSTIMR) USB Reset Sent Interrupt Enable Mask */ -#define HSTIMR_RSMEDIE_Pos 3 /**< (HSTIMR) Downstream Resume Sent Interrupt Enable Position */ -#define HSTIMR_RSMEDIE (_U_(0x1) << HSTIMR_RSMEDIE_Pos) /**< (HSTIMR) Downstream Resume Sent Interrupt Enable Mask */ -#define HSTIMR_RXRSMIE_Pos 4 /**< (HSTIMR) Upstream Resume Received Interrupt Enable Position */ -#define HSTIMR_RXRSMIE (_U_(0x1) << HSTIMR_RXRSMIE_Pos) /**< (HSTIMR) Upstream Resume Received Interrupt Enable Mask */ -#define HSTIMR_HSOFIE_Pos 5 /**< (HSTIMR) Host Start of Frame Interrupt Enable Position */ -#define HSTIMR_HSOFIE (_U_(0x1) << HSTIMR_HSOFIE_Pos) /**< (HSTIMR) Host Start of Frame Interrupt Enable Mask */ -#define HSTIMR_HWUPIE_Pos 6 /**< (HSTIMR) Host Wake-Up Interrupt Enable Position */ -#define HSTIMR_HWUPIE (_U_(0x1) << HSTIMR_HWUPIE_Pos) /**< (HSTIMR) Host Wake-Up Interrupt Enable Mask */ -#define HSTIMR_PEP_0_Pos 8 /**< (HSTIMR) Pipe 0 Interrupt Enable Position */ -#define HSTIMR_PEP_0 (_U_(0x1) << HSTIMR_PEP_0_Pos) /**< (HSTIMR) Pipe 0 Interrupt Enable Mask */ -#define HSTIMR_PEP_1_Pos 9 /**< (HSTIMR) Pipe 1 Interrupt Enable Position */ -#define HSTIMR_PEP_1 (_U_(0x1) << HSTIMR_PEP_1_Pos) /**< (HSTIMR) Pipe 1 Interrupt Enable Mask */ -#define HSTIMR_PEP_2_Pos 10 /**< (HSTIMR) Pipe 2 Interrupt Enable Position */ -#define HSTIMR_PEP_2 (_U_(0x1) << HSTIMR_PEP_2_Pos) /**< (HSTIMR) Pipe 2 Interrupt Enable Mask */ -#define HSTIMR_PEP_3_Pos 11 /**< (HSTIMR) Pipe 3 Interrupt Enable Position */ -#define HSTIMR_PEP_3 (_U_(0x1) << HSTIMR_PEP_3_Pos) /**< (HSTIMR) Pipe 3 Interrupt Enable Mask */ -#define HSTIMR_PEP_4_Pos 12 /**< (HSTIMR) Pipe 4 Interrupt Enable Position */ -#define HSTIMR_PEP_4 (_U_(0x1) << HSTIMR_PEP_4_Pos) /**< (HSTIMR) Pipe 4 Interrupt Enable Mask */ -#define HSTIMR_PEP_5_Pos 13 /**< (HSTIMR) Pipe 5 Interrupt Enable Position */ -#define HSTIMR_PEP_5 (_U_(0x1) << HSTIMR_PEP_5_Pos) /**< (HSTIMR) Pipe 5 Interrupt Enable Mask */ -#define HSTIMR_PEP_6_Pos 14 /**< (HSTIMR) Pipe 6 Interrupt Enable Position */ -#define HSTIMR_PEP_6 (_U_(0x1) << HSTIMR_PEP_6_Pos) /**< (HSTIMR) Pipe 6 Interrupt Enable Mask */ -#define HSTIMR_PEP_7_Pos 15 /**< (HSTIMR) Pipe 7 Interrupt Enable Position */ -#define HSTIMR_PEP_7 (_U_(0x1) << HSTIMR_PEP_7_Pos) /**< (HSTIMR) Pipe 7 Interrupt Enable Mask */ -#define HSTIMR_PEP_8_Pos 16 /**< (HSTIMR) Pipe 8 Interrupt Enable Position */ -#define HSTIMR_PEP_8 (_U_(0x1) << HSTIMR_PEP_8_Pos) /**< (HSTIMR) Pipe 8 Interrupt Enable Mask */ -#define HSTIMR_PEP_9_Pos 17 /**< (HSTIMR) Pipe 9 Interrupt Enable Position */ -#define HSTIMR_PEP_9 (_U_(0x1) << HSTIMR_PEP_9_Pos) /**< (HSTIMR) Pipe 9 Interrupt Enable Mask */ -#define HSTIMR_DMA_0_Pos 25 /**< (HSTIMR) DMA Channel 0 Interrupt Enable Position */ -#define HSTIMR_DMA_0 (_U_(0x1) << HSTIMR_DMA_0_Pos) /**< (HSTIMR) DMA Channel 0 Interrupt Enable Mask */ -#define HSTIMR_DMA_1_Pos 26 /**< (HSTIMR) DMA Channel 1 Interrupt Enable Position */ -#define HSTIMR_DMA_1 (_U_(0x1) << HSTIMR_DMA_1_Pos) /**< (HSTIMR) DMA Channel 1 Interrupt Enable Mask */ -#define HSTIMR_DMA_2_Pos 27 /**< (HSTIMR) DMA Channel 2 Interrupt Enable Position */ -#define HSTIMR_DMA_2 (_U_(0x1) << HSTIMR_DMA_2_Pos) /**< (HSTIMR) DMA Channel 2 Interrupt Enable Mask */ -#define HSTIMR_DMA_3_Pos 28 /**< (HSTIMR) DMA Channel 3 Interrupt Enable Position */ -#define HSTIMR_DMA_3 (_U_(0x1) << HSTIMR_DMA_3_Pos) /**< (HSTIMR) DMA Channel 3 Interrupt Enable Mask */ -#define HSTIMR_DMA_4_Pos 29 /**< (HSTIMR) DMA Channel 4 Interrupt Enable Position */ -#define HSTIMR_DMA_4 (_U_(0x1) << HSTIMR_DMA_4_Pos) /**< (HSTIMR) DMA Channel 4 Interrupt Enable Mask */ -#define HSTIMR_DMA_5_Pos 30 /**< (HSTIMR) DMA Channel 5 Interrupt Enable Position */ -#define HSTIMR_DMA_5 (_U_(0x1) << HSTIMR_DMA_5_Pos) /**< (HSTIMR) DMA Channel 5 Interrupt Enable Mask */ -#define HSTIMR_DMA_6_Pos 31 /**< (HSTIMR) DMA Channel 6 Interrupt Enable Position */ -#define HSTIMR_DMA_6 (_U_(0x1) << HSTIMR_DMA_6_Pos) /**< (HSTIMR) DMA Channel 6 Interrupt Enable Mask */ -#define HSTIMR_Msk _U_(0xFE03FF7F) /**< (HSTIMR) Register Mask */ - -#define HSTIMR_PEP__Pos 8 /**< (HSTIMR Position) Pipe x Interrupt Enable */ -#define HSTIMR_PEP_ (_U_(0x3FF) << HSTIMR_PEP__Pos) /**< (HSTIMR Mask) PEP_ */ -#define HSTIMR_DMA__Pos 25 /**< (HSTIMR Position) DMA Channel 6 Interrupt Enable */ -#define HSTIMR_DMA_ (_U_(0x7F) << HSTIMR_DMA__Pos) /**< (HSTIMR Mask) DMA_ */ - -/* -------- HSTIDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */ - -#define HSTIDR_OFFSET (0x414) /**< (HSTIDR) Host Global Interrupt Disable Register Offset */ - -#define HSTIDR_DCONNIEC_Pos 0 /**< (HSTIDR) Device Connection Interrupt Disable Position */ -#define HSTIDR_DCONNIEC (_U_(0x1) << HSTIDR_DCONNIEC_Pos) /**< (HSTIDR) Device Connection Interrupt Disable Mask */ -#define HSTIDR_DDISCIEC_Pos 1 /**< (HSTIDR) Device Disconnection Interrupt Disable Position */ -#define HSTIDR_DDISCIEC (_U_(0x1) << HSTIDR_DDISCIEC_Pos) /**< (HSTIDR) Device Disconnection Interrupt Disable Mask */ -#define HSTIDR_RSTIEC_Pos 2 /**< (HSTIDR) USB Reset Sent Interrupt Disable Position */ -#define HSTIDR_RSTIEC (_U_(0x1) << HSTIDR_RSTIEC_Pos) /**< (HSTIDR) USB Reset Sent Interrupt Disable Mask */ -#define HSTIDR_RSMEDIEC_Pos 3 /**< (HSTIDR) Downstream Resume Sent Interrupt Disable Position */ -#define HSTIDR_RSMEDIEC (_U_(0x1) << HSTIDR_RSMEDIEC_Pos) /**< (HSTIDR) Downstream Resume Sent Interrupt Disable Mask */ -#define HSTIDR_RXRSMIEC_Pos 4 /**< (HSTIDR) Upstream Resume Received Interrupt Disable Position */ -#define HSTIDR_RXRSMIEC (_U_(0x1) << HSTIDR_RXRSMIEC_Pos) /**< (HSTIDR) Upstream Resume Received Interrupt Disable Mask */ -#define HSTIDR_HSOFIEC_Pos 5 /**< (HSTIDR) Host Start of Frame Interrupt Disable Position */ -#define HSTIDR_HSOFIEC (_U_(0x1) << HSTIDR_HSOFIEC_Pos) /**< (HSTIDR) Host Start of Frame Interrupt Disable Mask */ -#define HSTIDR_HWUPIEC_Pos 6 /**< (HSTIDR) Host Wake-Up Interrupt Disable Position */ -#define HSTIDR_HWUPIEC (_U_(0x1) << HSTIDR_HWUPIEC_Pos) /**< (HSTIDR) Host Wake-Up Interrupt Disable Mask */ -#define HSTIDR_PEP_0_Pos 8 /**< (HSTIDR) Pipe 0 Interrupt Disable Position */ -#define HSTIDR_PEP_0 (_U_(0x1) << HSTIDR_PEP_0_Pos) /**< (HSTIDR) Pipe 0 Interrupt Disable Mask */ -#define HSTIDR_PEP_1_Pos 9 /**< (HSTIDR) Pipe 1 Interrupt Disable Position */ -#define HSTIDR_PEP_1 (_U_(0x1) << HSTIDR_PEP_1_Pos) /**< (HSTIDR) Pipe 1 Interrupt Disable Mask */ -#define HSTIDR_PEP_2_Pos 10 /**< (HSTIDR) Pipe 2 Interrupt Disable Position */ -#define HSTIDR_PEP_2 (_U_(0x1) << HSTIDR_PEP_2_Pos) /**< (HSTIDR) Pipe 2 Interrupt Disable Mask */ -#define HSTIDR_PEP_3_Pos 11 /**< (HSTIDR) Pipe 3 Interrupt Disable Position */ -#define HSTIDR_PEP_3 (_U_(0x1) << HSTIDR_PEP_3_Pos) /**< (HSTIDR) Pipe 3 Interrupt Disable Mask */ -#define HSTIDR_PEP_4_Pos 12 /**< (HSTIDR) Pipe 4 Interrupt Disable Position */ -#define HSTIDR_PEP_4 (_U_(0x1) << HSTIDR_PEP_4_Pos) /**< (HSTIDR) Pipe 4 Interrupt Disable Mask */ -#define HSTIDR_PEP_5_Pos 13 /**< (HSTIDR) Pipe 5 Interrupt Disable Position */ -#define HSTIDR_PEP_5 (_U_(0x1) << HSTIDR_PEP_5_Pos) /**< (HSTIDR) Pipe 5 Interrupt Disable Mask */ -#define HSTIDR_PEP_6_Pos 14 /**< (HSTIDR) Pipe 6 Interrupt Disable Position */ -#define HSTIDR_PEP_6 (_U_(0x1) << HSTIDR_PEP_6_Pos) /**< (HSTIDR) Pipe 6 Interrupt Disable Mask */ -#define HSTIDR_PEP_7_Pos 15 /**< (HSTIDR) Pipe 7 Interrupt Disable Position */ -#define HSTIDR_PEP_7 (_U_(0x1) << HSTIDR_PEP_7_Pos) /**< (HSTIDR) Pipe 7 Interrupt Disable Mask */ -#define HSTIDR_PEP_8_Pos 16 /**< (HSTIDR) Pipe 8 Interrupt Disable Position */ -#define HSTIDR_PEP_8 (_U_(0x1) << HSTIDR_PEP_8_Pos) /**< (HSTIDR) Pipe 8 Interrupt Disable Mask */ -#define HSTIDR_PEP_9_Pos 17 /**< (HSTIDR) Pipe 9 Interrupt Disable Position */ -#define HSTIDR_PEP_9 (_U_(0x1) << HSTIDR_PEP_9_Pos) /**< (HSTIDR) Pipe 9 Interrupt Disable Mask */ -#define HSTIDR_DMA_0_Pos 25 /**< (HSTIDR) DMA Channel 0 Interrupt Disable Position */ -#define HSTIDR_DMA_0 (_U_(0x1) << HSTIDR_DMA_0_Pos) /**< (HSTIDR) DMA Channel 0 Interrupt Disable Mask */ -#define HSTIDR_DMA_1_Pos 26 /**< (HSTIDR) DMA Channel 1 Interrupt Disable Position */ -#define HSTIDR_DMA_1 (_U_(0x1) << HSTIDR_DMA_1_Pos) /**< (HSTIDR) DMA Channel 1 Interrupt Disable Mask */ -#define HSTIDR_DMA_2_Pos 27 /**< (HSTIDR) DMA Channel 2 Interrupt Disable Position */ -#define HSTIDR_DMA_2 (_U_(0x1) << HSTIDR_DMA_2_Pos) /**< (HSTIDR) DMA Channel 2 Interrupt Disable Mask */ -#define HSTIDR_DMA_3_Pos 28 /**< (HSTIDR) DMA Channel 3 Interrupt Disable Position */ -#define HSTIDR_DMA_3 (_U_(0x1) << HSTIDR_DMA_3_Pos) /**< (HSTIDR) DMA Channel 3 Interrupt Disable Mask */ -#define HSTIDR_DMA_4_Pos 29 /**< (HSTIDR) DMA Channel 4 Interrupt Disable Position */ -#define HSTIDR_DMA_4 (_U_(0x1) << HSTIDR_DMA_4_Pos) /**< (HSTIDR) DMA Channel 4 Interrupt Disable Mask */ -#define HSTIDR_DMA_5_Pos 30 /**< (HSTIDR) DMA Channel 5 Interrupt Disable Position */ -#define HSTIDR_DMA_5 (_U_(0x1) << HSTIDR_DMA_5_Pos) /**< (HSTIDR) DMA Channel 5 Interrupt Disable Mask */ -#define HSTIDR_DMA_6_Pos 31 /**< (HSTIDR) DMA Channel 6 Interrupt Disable Position */ -#define HSTIDR_DMA_6 (_U_(0x1) << HSTIDR_DMA_6_Pos) /**< (HSTIDR) DMA Channel 6 Interrupt Disable Mask */ -#define HSTIDR_Msk _U_(0xFE03FF7F) /**< (HSTIDR) Register Mask */ - -#define HSTIDR_PEP__Pos 8 /**< (HSTIDR Position) Pipe x Interrupt Disable */ -#define HSTIDR_PEP_ (_U_(0x3FF) << HSTIDR_PEP__Pos) /**< (HSTIDR Mask) PEP_ */ -#define HSTIDR_DMA__Pos 25 /**< (HSTIDR Position) DMA Channel 6 Interrupt Disable */ -#define HSTIDR_DMA_ (_U_(0x7F) << HSTIDR_DMA__Pos) /**< (HSTIDR Mask) DMA_ */ - -/* -------- HSTIER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */ - -#define HSTIER_OFFSET (0x418) /**< (HSTIER) Host Global Interrupt Enable Register Offset */ - -#define HSTIER_DCONNIES_Pos 0 /**< (HSTIER) Device Connection Interrupt Enable Position */ -#define HSTIER_DCONNIES (_U_(0x1) << HSTIER_DCONNIES_Pos) /**< (HSTIER) Device Connection Interrupt Enable Mask */ -#define HSTIER_DDISCIES_Pos 1 /**< (HSTIER) Device Disconnection Interrupt Enable Position */ -#define HSTIER_DDISCIES (_U_(0x1) << HSTIER_DDISCIES_Pos) /**< (HSTIER) Device Disconnection Interrupt Enable Mask */ -#define HSTIER_RSTIES_Pos 2 /**< (HSTIER) USB Reset Sent Interrupt Enable Position */ -#define HSTIER_RSTIES (_U_(0x1) << HSTIER_RSTIES_Pos) /**< (HSTIER) USB Reset Sent Interrupt Enable Mask */ -#define HSTIER_RSMEDIES_Pos 3 /**< (HSTIER) Downstream Resume Sent Interrupt Enable Position */ -#define HSTIER_RSMEDIES (_U_(0x1) << HSTIER_RSMEDIES_Pos) /**< (HSTIER) Downstream Resume Sent Interrupt Enable Mask */ -#define HSTIER_RXRSMIES_Pos 4 /**< (HSTIER) Upstream Resume Received Interrupt Enable Position */ -#define HSTIER_RXRSMIES (_U_(0x1) << HSTIER_RXRSMIES_Pos) /**< (HSTIER) Upstream Resume Received Interrupt Enable Mask */ -#define HSTIER_HSOFIES_Pos 5 /**< (HSTIER) Host Start of Frame Interrupt Enable Position */ -#define HSTIER_HSOFIES (_U_(0x1) << HSTIER_HSOFIES_Pos) /**< (HSTIER) Host Start of Frame Interrupt Enable Mask */ -#define HSTIER_HWUPIES_Pos 6 /**< (HSTIER) Host Wake-Up Interrupt Enable Position */ -#define HSTIER_HWUPIES (_U_(0x1) << HSTIER_HWUPIES_Pos) /**< (HSTIER) Host Wake-Up Interrupt Enable Mask */ -#define HSTIER_PEP_0_Pos 8 /**< (HSTIER) Pipe 0 Interrupt Enable Position */ -#define HSTIER_PEP_0 (_U_(0x1) << HSTIER_PEP_0_Pos) /**< (HSTIER) Pipe 0 Interrupt Enable Mask */ -#define HSTIER_PEP_1_Pos 9 /**< (HSTIER) Pipe 1 Interrupt Enable Position */ -#define HSTIER_PEP_1 (_U_(0x1) << HSTIER_PEP_1_Pos) /**< (HSTIER) Pipe 1 Interrupt Enable Mask */ -#define HSTIER_PEP_2_Pos 10 /**< (HSTIER) Pipe 2 Interrupt Enable Position */ -#define HSTIER_PEP_2 (_U_(0x1) << HSTIER_PEP_2_Pos) /**< (HSTIER) Pipe 2 Interrupt Enable Mask */ -#define HSTIER_PEP_3_Pos 11 /**< (HSTIER) Pipe 3 Interrupt Enable Position */ -#define HSTIER_PEP_3 (_U_(0x1) << HSTIER_PEP_3_Pos) /**< (HSTIER) Pipe 3 Interrupt Enable Mask */ -#define HSTIER_PEP_4_Pos 12 /**< (HSTIER) Pipe 4 Interrupt Enable Position */ -#define HSTIER_PEP_4 (_U_(0x1) << HSTIER_PEP_4_Pos) /**< (HSTIER) Pipe 4 Interrupt Enable Mask */ -#define HSTIER_PEP_5_Pos 13 /**< (HSTIER) Pipe 5 Interrupt Enable Position */ -#define HSTIER_PEP_5 (_U_(0x1) << HSTIER_PEP_5_Pos) /**< (HSTIER) Pipe 5 Interrupt Enable Mask */ -#define HSTIER_PEP_6_Pos 14 /**< (HSTIER) Pipe 6 Interrupt Enable Position */ -#define HSTIER_PEP_6 (_U_(0x1) << HSTIER_PEP_6_Pos) /**< (HSTIER) Pipe 6 Interrupt Enable Mask */ -#define HSTIER_PEP_7_Pos 15 /**< (HSTIER) Pipe 7 Interrupt Enable Position */ -#define HSTIER_PEP_7 (_U_(0x1) << HSTIER_PEP_7_Pos) /**< (HSTIER) Pipe 7 Interrupt Enable Mask */ -#define HSTIER_PEP_8_Pos 16 /**< (HSTIER) Pipe 8 Interrupt Enable Position */ -#define HSTIER_PEP_8 (_U_(0x1) << HSTIER_PEP_8_Pos) /**< (HSTIER) Pipe 8 Interrupt Enable Mask */ -#define HSTIER_PEP_9_Pos 17 /**< (HSTIER) Pipe 9 Interrupt Enable Position */ -#define HSTIER_PEP_9 (_U_(0x1) << HSTIER_PEP_9_Pos) /**< (HSTIER) Pipe 9 Interrupt Enable Mask */ -#define HSTIER_DMA_0_Pos 25 /**< (HSTIER) DMA Channel 0 Interrupt Enable Position */ -#define HSTIER_DMA_0 (_U_(0x1) << HSTIER_DMA_0_Pos) /**< (HSTIER) DMA Channel 0 Interrupt Enable Mask */ -#define HSTIER_DMA_1_Pos 26 /**< (HSTIER) DMA Channel 1 Interrupt Enable Position */ -#define HSTIER_DMA_1 (_U_(0x1) << HSTIER_DMA_1_Pos) /**< (HSTIER) DMA Channel 1 Interrupt Enable Mask */ -#define HSTIER_DMA_2_Pos 27 /**< (HSTIER) DMA Channel 2 Interrupt Enable Position */ -#define HSTIER_DMA_2 (_U_(0x1) << HSTIER_DMA_2_Pos) /**< (HSTIER) DMA Channel 2 Interrupt Enable Mask */ -#define HSTIER_DMA_3_Pos 28 /**< (HSTIER) DMA Channel 3 Interrupt Enable Position */ -#define HSTIER_DMA_3 (_U_(0x1) << HSTIER_DMA_3_Pos) /**< (HSTIER) DMA Channel 3 Interrupt Enable Mask */ -#define HSTIER_DMA_4_Pos 29 /**< (HSTIER) DMA Channel 4 Interrupt Enable Position */ -#define HSTIER_DMA_4 (_U_(0x1) << HSTIER_DMA_4_Pos) /**< (HSTIER) DMA Channel 4 Interrupt Enable Mask */ -#define HSTIER_DMA_5_Pos 30 /**< (HSTIER) DMA Channel 5 Interrupt Enable Position */ -#define HSTIER_DMA_5 (_U_(0x1) << HSTIER_DMA_5_Pos) /**< (HSTIER) DMA Channel 5 Interrupt Enable Mask */ -#define HSTIER_DMA_6_Pos 31 /**< (HSTIER) DMA Channel 6 Interrupt Enable Position */ -#define HSTIER_DMA_6 (_U_(0x1) << HSTIER_DMA_6_Pos) /**< (HSTIER) DMA Channel 6 Interrupt Enable Mask */ -#define HSTIER_Msk _U_(0xFE03FF7F) /**< (HSTIER) Register Mask */ - -#define HSTIER_PEP__Pos 8 /**< (HSTIER Position) Pipe x Interrupt Enable */ -#define HSTIER_PEP_ (_U_(0x3FF) << HSTIER_PEP__Pos) /**< (HSTIER Mask) PEP_ */ -#define HSTIER_DMA__Pos 25 /**< (HSTIER Position) DMA Channel 6 Interrupt Enable */ -#define HSTIER_DMA_ (_U_(0x7F) << HSTIER_DMA__Pos) /**< (HSTIER Mask) DMA_ */ - -/* -------- HSTPIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */ - -#define HSTPIP_OFFSET (0x41C) /**< (HSTPIP) Host Pipe Register Offset */ - -#define HSTPIP_PEN0_Pos 0 /**< (HSTPIP) Pipe 0 Enable Position */ -#define HSTPIP_PEN0 (_U_(0x1) << HSTPIP_PEN0_Pos) /**< (HSTPIP) Pipe 0 Enable Mask */ -#define HSTPIP_PEN1_Pos 1 /**< (HSTPIP) Pipe 1 Enable Position */ -#define HSTPIP_PEN1 (_U_(0x1) << HSTPIP_PEN1_Pos) /**< (HSTPIP) Pipe 1 Enable Mask */ -#define HSTPIP_PEN2_Pos 2 /**< (HSTPIP) Pipe 2 Enable Position */ -#define HSTPIP_PEN2 (_U_(0x1) << HSTPIP_PEN2_Pos) /**< (HSTPIP) Pipe 2 Enable Mask */ -#define HSTPIP_PEN3_Pos 3 /**< (HSTPIP) Pipe 3 Enable Position */ -#define HSTPIP_PEN3 (_U_(0x1) << HSTPIP_PEN3_Pos) /**< (HSTPIP) Pipe 3 Enable Mask */ -#define HSTPIP_PEN4_Pos 4 /**< (HSTPIP) Pipe 4 Enable Position */ -#define HSTPIP_PEN4 (_U_(0x1) << HSTPIP_PEN4_Pos) /**< (HSTPIP) Pipe 4 Enable Mask */ -#define HSTPIP_PEN5_Pos 5 /**< (HSTPIP) Pipe 5 Enable Position */ -#define HSTPIP_PEN5 (_U_(0x1) << HSTPIP_PEN5_Pos) /**< (HSTPIP) Pipe 5 Enable Mask */ -#define HSTPIP_PEN6_Pos 6 /**< (HSTPIP) Pipe 6 Enable Position */ -#define HSTPIP_PEN6 (_U_(0x1) << HSTPIP_PEN6_Pos) /**< (HSTPIP) Pipe 6 Enable Mask */ -#define HSTPIP_PEN7_Pos 7 /**< (HSTPIP) Pipe 7 Enable Position */ -#define HSTPIP_PEN7 (_U_(0x1) << HSTPIP_PEN7_Pos) /**< (HSTPIP) Pipe 7 Enable Mask */ -#define HSTPIP_PEN8_Pos 8 /**< (HSTPIP) Pipe 8 Enable Position */ -#define HSTPIP_PEN8 (_U_(0x1) << HSTPIP_PEN8_Pos) /**< (HSTPIP) Pipe 8 Enable Mask */ -#define HSTPIP_PRST0_Pos 16 /**< (HSTPIP) Pipe 0 Reset Position */ -#define HSTPIP_PRST0 (_U_(0x1) << HSTPIP_PRST0_Pos) /**< (HSTPIP) Pipe 0 Reset Mask */ -#define HSTPIP_PRST1_Pos 17 /**< (HSTPIP) Pipe 1 Reset Position */ -#define HSTPIP_PRST1 (_U_(0x1) << HSTPIP_PRST1_Pos) /**< (HSTPIP) Pipe 1 Reset Mask */ -#define HSTPIP_PRST2_Pos 18 /**< (HSTPIP) Pipe 2 Reset Position */ -#define HSTPIP_PRST2 (_U_(0x1) << HSTPIP_PRST2_Pos) /**< (HSTPIP) Pipe 2 Reset Mask */ -#define HSTPIP_PRST3_Pos 19 /**< (HSTPIP) Pipe 3 Reset Position */ -#define HSTPIP_PRST3 (_U_(0x1) << HSTPIP_PRST3_Pos) /**< (HSTPIP) Pipe 3 Reset Mask */ -#define HSTPIP_PRST4_Pos 20 /**< (HSTPIP) Pipe 4 Reset Position */ -#define HSTPIP_PRST4 (_U_(0x1) << HSTPIP_PRST4_Pos) /**< (HSTPIP) Pipe 4 Reset Mask */ -#define HSTPIP_PRST5_Pos 21 /**< (HSTPIP) Pipe 5 Reset Position */ -#define HSTPIP_PRST5 (_U_(0x1) << HSTPIP_PRST5_Pos) /**< (HSTPIP) Pipe 5 Reset Mask */ -#define HSTPIP_PRST6_Pos 22 /**< (HSTPIP) Pipe 6 Reset Position */ -#define HSTPIP_PRST6 (_U_(0x1) << HSTPIP_PRST6_Pos) /**< (HSTPIP) Pipe 6 Reset Mask */ -#define HSTPIP_PRST7_Pos 23 /**< (HSTPIP) Pipe 7 Reset Position */ -#define HSTPIP_PRST7 (_U_(0x1) << HSTPIP_PRST7_Pos) /**< (HSTPIP) Pipe 7 Reset Mask */ -#define HSTPIP_PRST8_Pos 24 /**< (HSTPIP) Pipe 8 Reset Position */ -#define HSTPIP_PRST8 (_U_(0x1) << HSTPIP_PRST8_Pos) /**< (HSTPIP) Pipe 8 Reset Mask */ -#define HSTPIP_Msk _U_(0x1FF01FF) /**< (HSTPIP) Register Mask */ - -#define HSTPIP_PEN_Pos 0 /**< (HSTPIP Position) Pipe x Enable */ -#define HSTPIP_PEN (_U_(0x1FF) << HSTPIP_PEN_Pos) /**< (HSTPIP Mask) PEN */ -#define HSTPIP_PRST_Pos 16 /**< (HSTPIP Position) Pipe 8 Reset */ -#define HSTPIP_PRST (_U_(0x1FF) << HSTPIP_PRST_Pos) /**< (HSTPIP Mask) PRST */ - -/* -------- HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ - -#define HSTFNUM_OFFSET (0x420) /**< (HSTFNUM) Host Frame Number Register Offset */ - -#define HSTFNUM_MFNUM_Pos 0 /**< (HSTFNUM) Micro Frame Number Position */ -#define HSTFNUM_MFNUM (_U_(0x7) << HSTFNUM_MFNUM_Pos) /**< (HSTFNUM) Micro Frame Number Mask */ -#define HSTFNUM_FNUM_Pos 3 /**< (HSTFNUM) Frame Number Position */ -#define HSTFNUM_FNUM (_U_(0x7FF) << HSTFNUM_FNUM_Pos) /**< (HSTFNUM) Frame Number Mask */ -#define HSTFNUM_FLENHIGH_Pos 16 /**< (HSTFNUM) Frame Length Position */ -#define HSTFNUM_FLENHIGH (_U_(0xFF) << HSTFNUM_FLENHIGH_Pos) /**< (HSTFNUM) Frame Length Mask */ -#define HSTFNUM_Msk _U_(0xFF3FFF) /**< (HSTFNUM) Register Mask */ - - -/* -------- HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ - -#define HSTADDR1_OFFSET (0x424) /**< (HSTADDR1) Host Address 1 Register Offset */ - -#define HSTADDR1_HSTADDRP0_Pos 0 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP0 (_U_(0x7F) << HSTADDR1_HSTADDRP0_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_HSTADDRP1_Pos 8 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP1 (_U_(0x7F) << HSTADDR1_HSTADDRP1_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_HSTADDRP2_Pos 16 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP2 (_U_(0x7F) << HSTADDR1_HSTADDRP2_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_HSTADDRP3_Pos 24 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP3 (_U_(0x7F) << HSTADDR1_HSTADDRP3_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_Msk _U_(0x7F7F7F7F) /**< (HSTADDR1) Register Mask */ - - -/* -------- HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ - -#define HSTADDR2_OFFSET (0x428) /**< (HSTADDR2) Host Address 2 Register Offset */ - -#define HSTADDR2_HSTADDRP4_Pos 0 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP4 (_U_(0x7F) << HSTADDR2_HSTADDRP4_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_HSTADDRP5_Pos 8 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP5 (_U_(0x7F) << HSTADDR2_HSTADDRP5_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_HSTADDRP6_Pos 16 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP6 (_U_(0x7F) << HSTADDR2_HSTADDRP6_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_HSTADDRP7_Pos 24 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP7 (_U_(0x7F) << HSTADDR2_HSTADDRP7_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_Msk _U_(0x7F7F7F7F) /**< (HSTADDR2) Register Mask */ - - -/* -------- HSTADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */ - -#define HSTADDR3_OFFSET (0x42C) /**< (HSTADDR3) Host Address 3 Register Offset */ - -#define HSTADDR3_HSTADDRP8_Pos 0 /**< (HSTADDR3) USB Host Address Position */ -#define HSTADDR3_HSTADDRP8 (_U_(0x7F) << HSTADDR3_HSTADDRP8_Pos) /**< (HSTADDR3) USB Host Address Mask */ -#define HSTADDR3_HSTADDRP9_Pos 8 /**< (HSTADDR3) USB Host Address Position */ -#define HSTADDR3_HSTADDRP9 (_U_(0x7F) << HSTADDR3_HSTADDRP9_Pos) /**< (HSTADDR3) USB Host Address Mask */ -#define HSTADDR3_Msk _U_(0x7F7F) /**< (HSTADDR3) Register Mask */ - - -/* -------- HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */ - -#define HSTPIPCFG_OFFSET (0x500) /**< (HSTPIPCFG) Host Pipe Configuration Register Offset */ - -#define HSTPIPCFG_ALLOC_Pos 1 /**< (HSTPIPCFG) Pipe Memory Allocate Position */ -#define HSTPIPCFG_ALLOC (_U_(0x1) << HSTPIPCFG_ALLOC_Pos) /**< (HSTPIPCFG) Pipe Memory Allocate Mask */ -#define HSTPIPCFG_PBK_Pos 2 /**< (HSTPIPCFG) Pipe Banks Position */ -#define HSTPIPCFG_PBK (_U_(0x3) << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Pipe Banks Mask */ -#define HSTPIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (HSTPIPCFG) Single-bank pipe */ -#define HSTPIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (HSTPIPCFG) Double-bank pipe */ -#define HSTPIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (HSTPIPCFG) Triple-bank pipe */ -#define HSTPIPCFG_PBK_1_BANK (HSTPIPCFG_PBK_1_BANK_Val << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Single-bank pipe Position */ -#define HSTPIPCFG_PBK_2_BANK (HSTPIPCFG_PBK_2_BANK_Val << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Double-bank pipe Position */ -#define HSTPIPCFG_PBK_3_BANK (HSTPIPCFG_PBK_3_BANK_Val << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Triple-bank pipe Position */ -#define HSTPIPCFG_PSIZE_Pos 4 /**< (HSTPIPCFG) Pipe Size Position */ -#define HSTPIPCFG_PSIZE (_U_(0x7) << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) Pipe Size Mask */ -#define HSTPIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (HSTPIPCFG) 8 bytes */ -#define HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (HSTPIPCFG) 16 bytes */ -#define HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (HSTPIPCFG) 32 bytes */ -#define HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (HSTPIPCFG) 64 bytes */ -#define HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (HSTPIPCFG) 128 bytes */ -#define HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (HSTPIPCFG) 256 bytes */ -#define HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (HSTPIPCFG) 512 bytes */ -#define HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (HSTPIPCFG) 1024 bytes */ -#define HSTPIPCFG_PSIZE_8_BYTE (HSTPIPCFG_PSIZE_8_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 8 bytes Position */ -#define HSTPIPCFG_PSIZE_16_BYTE (HSTPIPCFG_PSIZE_16_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 16 bytes Position */ -#define HSTPIPCFG_PSIZE_32_BYTE (HSTPIPCFG_PSIZE_32_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 32 bytes Position */ -#define HSTPIPCFG_PSIZE_64_BYTE (HSTPIPCFG_PSIZE_64_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 64 bytes Position */ -#define HSTPIPCFG_PSIZE_128_BYTE (HSTPIPCFG_PSIZE_128_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 128 bytes Position */ -#define HSTPIPCFG_PSIZE_256_BYTE (HSTPIPCFG_PSIZE_256_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 256 bytes Position */ -#define HSTPIPCFG_PSIZE_512_BYTE (HSTPIPCFG_PSIZE_512_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 512 bytes Position */ -#define HSTPIPCFG_PSIZE_1024_BYTE (HSTPIPCFG_PSIZE_1024_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 1024 bytes Position */ -#define HSTPIPCFG_PTOKEN_Pos 8 /**< (HSTPIPCFG) Pipe Token Position */ -#define HSTPIPCFG_PTOKEN (_U_(0x3) << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) Pipe Token Mask */ -#define HSTPIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (HSTPIPCFG) SETUP */ -#define HSTPIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (HSTPIPCFG) IN */ -#define HSTPIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (HSTPIPCFG) OUT */ -#define HSTPIPCFG_PTOKEN_SETUP (HSTPIPCFG_PTOKEN_SETUP_Val << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) SETUP Position */ -#define HSTPIPCFG_PTOKEN_IN (HSTPIPCFG_PTOKEN_IN_Val << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) IN Position */ -#define HSTPIPCFG_PTOKEN_OUT (HSTPIPCFG_PTOKEN_OUT_Val << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) OUT Position */ -#define HSTPIPCFG_AUTOSW_Pos 10 /**< (HSTPIPCFG) Automatic Switch Position */ -#define HSTPIPCFG_AUTOSW (_U_(0x1) << HSTPIPCFG_AUTOSW_Pos) /**< (HSTPIPCFG) Automatic Switch Mask */ -#define HSTPIPCFG_PTYPE_Pos 12 /**< (HSTPIPCFG) Pipe Type Position */ -#define HSTPIPCFG_PTYPE (_U_(0x3) << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Pipe Type Mask */ -#define HSTPIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (HSTPIPCFG) Control */ -#define HSTPIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (HSTPIPCFG) Isochronous */ -#define HSTPIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (HSTPIPCFG) Bulk */ -#define HSTPIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (HSTPIPCFG) Interrupt */ -#define HSTPIPCFG_PTYPE_CTRL (HSTPIPCFG_PTYPE_CTRL_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Control Position */ -#define HSTPIPCFG_PTYPE_ISO (HSTPIPCFG_PTYPE_ISO_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Isochronous Position */ -#define HSTPIPCFG_PTYPE_BLK (HSTPIPCFG_PTYPE_BLK_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Bulk Position */ -#define HSTPIPCFG_PTYPE_INTRPT (HSTPIPCFG_PTYPE_INTRPT_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Interrupt Position */ -#define HSTPIPCFG_PEPNUM_Pos 16 /**< (HSTPIPCFG) Pipe Endpoint Number Position */ -#define HSTPIPCFG_PEPNUM (_U_(0xF) << HSTPIPCFG_PEPNUM_Pos) /**< (HSTPIPCFG) Pipe Endpoint Number Mask */ -#define HSTPIPCFG_INTFRQ_Pos 24 /**< (HSTPIPCFG) Pipe Interrupt Request Frequency Position */ -#define HSTPIPCFG_INTFRQ (_U_(0xFF) << HSTPIPCFG_INTFRQ_Pos) /**< (HSTPIPCFG) Pipe Interrupt Request Frequency Mask */ -#define HSTPIPCFG_Msk _U_(0xFF0F377E) /**< (HSTPIPCFG) Register Mask */ - -/* CTRL_BULK mode */ -#define HSTPIPCFG_CTRL_BULK_PINGEN_Pos 20 /**< (HSTPIPCFG) Ping Enable Position */ -#define HSTPIPCFG_CTRL_BULK_PINGEN (_U_(0x1) << HSTPIPCFG_CTRL_BULK_PINGEN_Pos) /**< (HSTPIPCFG) Ping Enable Mask */ -#define HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos 24 /**< (HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */ -#define HSTPIPCFG_CTRL_BULK_BINTERVAL (_U_(0xFF) << HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos) /**< (HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */ -#define HSTPIPCFG_CTRL_BULK_Msk _U_(0xFF100000) /**< (HSTPIPCFG_CTRL_BULK) Register Mask */ - - -/* -------- HSTPIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */ - -#define HSTPIPISR_OFFSET (0x530) /**< (HSTPIPISR) Host Pipe Status Register Offset */ - -#define HSTPIPISR_RXINI_Pos 0 /**< (HSTPIPISR) Received IN Data Interrupt Position */ -#define HSTPIPISR_RXINI (_U_(0x1) << HSTPIPISR_RXINI_Pos) /**< (HSTPIPISR) Received IN Data Interrupt Mask */ -#define HSTPIPISR_TXOUTI_Pos 1 /**< (HSTPIPISR) Transmitted OUT Data Interrupt Position */ -#define HSTPIPISR_TXOUTI (_U_(0x1) << HSTPIPISR_TXOUTI_Pos) /**< (HSTPIPISR) Transmitted OUT Data Interrupt Mask */ -#define HSTPIPISR_PERRI_Pos 3 /**< (HSTPIPISR) Pipe Error Interrupt Position */ -#define HSTPIPISR_PERRI (_U_(0x1) << HSTPIPISR_PERRI_Pos) /**< (HSTPIPISR) Pipe Error Interrupt Mask */ -#define HSTPIPISR_NAKEDI_Pos 4 /**< (HSTPIPISR) NAKed Interrupt Position */ -#define HSTPIPISR_NAKEDI (_U_(0x1) << HSTPIPISR_NAKEDI_Pos) /**< (HSTPIPISR) NAKed Interrupt Mask */ -#define HSTPIPISR_OVERFI_Pos 5 /**< (HSTPIPISR) Overflow Interrupt Position */ -#define HSTPIPISR_OVERFI (_U_(0x1) << HSTPIPISR_OVERFI_Pos) /**< (HSTPIPISR) Overflow Interrupt Mask */ -#define HSTPIPISR_SHORTPACKETI_Pos 7 /**< (HSTPIPISR) Short Packet Interrupt Position */ -#define HSTPIPISR_SHORTPACKETI (_U_(0x1) << HSTPIPISR_SHORTPACKETI_Pos) /**< (HSTPIPISR) Short Packet Interrupt Mask */ -#define HSTPIPISR_DTSEQ_Pos 8 /**< (HSTPIPISR) Data Toggle Sequence Position */ -#define HSTPIPISR_DTSEQ (_U_(0x3) << HSTPIPISR_DTSEQ_Pos) /**< (HSTPIPISR) Data Toggle Sequence Mask */ -#define HSTPIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (HSTPIPISR) Data0 toggle sequence */ -#define HSTPIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (HSTPIPISR) Data1 toggle sequence */ -#define HSTPIPISR_DTSEQ_DATA0 (HSTPIPISR_DTSEQ_DATA0_Val << HSTPIPISR_DTSEQ_Pos) /**< (HSTPIPISR) Data0 toggle sequence Position */ -#define HSTPIPISR_DTSEQ_DATA1 (HSTPIPISR_DTSEQ_DATA1_Val << HSTPIPISR_DTSEQ_Pos) /**< (HSTPIPISR) Data1 toggle sequence Position */ -#define HSTPIPISR_NBUSYBK_Pos 12 /**< (HSTPIPISR) Number of Busy Banks Position */ -#define HSTPIPISR_NBUSYBK (_U_(0x3) << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) Number of Busy Banks Mask */ -#define HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (HSTPIPISR) 0 busy bank (all banks free) */ -#define HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (HSTPIPISR) 1 busy bank */ -#define HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (HSTPIPISR) 2 busy banks */ -#define HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (HSTPIPISR) 3 busy banks */ -#define HSTPIPISR_NBUSYBK_0_BUSY (HSTPIPISR_NBUSYBK_0_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 0 busy bank (all banks free) Position */ -#define HSTPIPISR_NBUSYBK_1_BUSY (HSTPIPISR_NBUSYBK_1_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 1 busy bank Position */ -#define HSTPIPISR_NBUSYBK_2_BUSY (HSTPIPISR_NBUSYBK_2_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 2 busy banks Position */ -#define HSTPIPISR_NBUSYBK_3_BUSY (HSTPIPISR_NBUSYBK_3_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 3 busy banks Position */ -#define HSTPIPISR_CURRBK_Pos 14 /**< (HSTPIPISR) Current Bank Position */ -#define HSTPIPISR_CURRBK (_U_(0x3) << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current Bank Mask */ -#define HSTPIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (HSTPIPISR) Current bank is bank0 */ -#define HSTPIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (HSTPIPISR) Current bank is bank1 */ -#define HSTPIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (HSTPIPISR) Current bank is bank2 */ -#define HSTPIPISR_CURRBK_BANK0 (HSTPIPISR_CURRBK_BANK0_Val << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current bank is bank0 Position */ -#define HSTPIPISR_CURRBK_BANK1 (HSTPIPISR_CURRBK_BANK1_Val << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current bank is bank1 Position */ -#define HSTPIPISR_CURRBK_BANK2 (HSTPIPISR_CURRBK_BANK2_Val << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current bank is bank2 Position */ -#define HSTPIPISR_RWALL_Pos 16 /**< (HSTPIPISR) Read/Write Allowed Position */ -#define HSTPIPISR_RWALL (_U_(0x1) << HSTPIPISR_RWALL_Pos) /**< (HSTPIPISR) Read/Write Allowed Mask */ -#define HSTPIPISR_CFGOK_Pos 18 /**< (HSTPIPISR) Configuration OK Status Position */ -#define HSTPIPISR_CFGOK (_U_(0x1) << HSTPIPISR_CFGOK_Pos) /**< (HSTPIPISR) Configuration OK Status Mask */ -#define HSTPIPISR_PBYCT_Pos 20 /**< (HSTPIPISR) Pipe Byte Count Position */ -#define HSTPIPISR_PBYCT (_U_(0x7FF) << HSTPIPISR_PBYCT_Pos) /**< (HSTPIPISR) Pipe Byte Count Mask */ -#define HSTPIPISR_Msk _U_(0x7FF5F3BB) /**< (HSTPIPISR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPISR_CTRL_TXSTPI_Pos 2 /**< (HSTPIPISR) Transmitted SETUP Interrupt Position */ -#define HSTPIPISR_CTRL_TXSTPI (_U_(0x1) << HSTPIPISR_CTRL_TXSTPI_Pos) /**< (HSTPIPISR) Transmitted SETUP Interrupt Mask */ -#define HSTPIPISR_CTRL_RXSTALLDI_Pos 6 /**< (HSTPIPISR) Received STALLed Interrupt Position */ -#define HSTPIPISR_CTRL_RXSTALLDI (_U_(0x1) << HSTPIPISR_CTRL_RXSTALLDI_Pos) /**< (HSTPIPISR) Received STALLed Interrupt Mask */ -#define HSTPIPISR_CTRL_Msk _U_(0x44) /**< (HSTPIPISR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPISR_ISO_UNDERFI_Pos 2 /**< (HSTPIPISR) Underflow Interrupt Position */ -#define HSTPIPISR_ISO_UNDERFI (_U_(0x1) << HSTPIPISR_ISO_UNDERFI_Pos) /**< (HSTPIPISR) Underflow Interrupt Mask */ -#define HSTPIPISR_ISO_CRCERRI_Pos 6 /**< (HSTPIPISR) CRC Error Interrupt Position */ -#define HSTPIPISR_ISO_CRCERRI (_U_(0x1) << HSTPIPISR_ISO_CRCERRI_Pos) /**< (HSTPIPISR) CRC Error Interrupt Mask */ -#define HSTPIPISR_ISO_Msk _U_(0x44) /**< (HSTPIPISR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPISR_BLK_TXSTPI_Pos 2 /**< (HSTPIPISR) Transmitted SETUP Interrupt Position */ -#define HSTPIPISR_BLK_TXSTPI (_U_(0x1) << HSTPIPISR_BLK_TXSTPI_Pos) /**< (HSTPIPISR) Transmitted SETUP Interrupt Mask */ -#define HSTPIPISR_BLK_RXSTALLDI_Pos 6 /**< (HSTPIPISR) Received STALLed Interrupt Position */ -#define HSTPIPISR_BLK_RXSTALLDI (_U_(0x1) << HSTPIPISR_BLK_RXSTALLDI_Pos) /**< (HSTPIPISR) Received STALLed Interrupt Mask */ -#define HSTPIPISR_BLK_Msk _U_(0x44) /**< (HSTPIPISR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPISR_INTRPT_UNDERFI_Pos 2 /**< (HSTPIPISR) Underflow Interrupt Position */ -#define HSTPIPISR_INTRPT_UNDERFI (_U_(0x1) << HSTPIPISR_INTRPT_UNDERFI_Pos) /**< (HSTPIPISR) Underflow Interrupt Mask */ -#define HSTPIPISR_INTRPT_RXSTALLDI_Pos 6 /**< (HSTPIPISR) Received STALLed Interrupt Position */ -#define HSTPIPISR_INTRPT_RXSTALLDI (_U_(0x1) << HSTPIPISR_INTRPT_RXSTALLDI_Pos) /**< (HSTPIPISR) Received STALLed Interrupt Mask */ -#define HSTPIPISR_INTRPT_Msk _U_(0x44) /**< (HSTPIPISR_INTRPT) Register Mask */ - - -/* -------- HSTPIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */ - -#define HSTPIPICR_OFFSET (0x560) /**< (HSTPIPICR) Host Pipe Clear Register Offset */ - -#define HSTPIPICR_RXINIC_Pos 0 /**< (HSTPIPICR) Received IN Data Interrupt Clear Position */ -#define HSTPIPICR_RXINIC (_U_(0x1) << HSTPIPICR_RXINIC_Pos) /**< (HSTPIPICR) Received IN Data Interrupt Clear Mask */ -#define HSTPIPICR_TXOUTIC_Pos 1 /**< (HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */ -#define HSTPIPICR_TXOUTIC (_U_(0x1) << HSTPIPICR_TXOUTIC_Pos) /**< (HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */ -#define HSTPIPICR_NAKEDIC_Pos 4 /**< (HSTPIPICR) NAKed Interrupt Clear Position */ -#define HSTPIPICR_NAKEDIC (_U_(0x1) << HSTPIPICR_NAKEDIC_Pos) /**< (HSTPIPICR) NAKed Interrupt Clear Mask */ -#define HSTPIPICR_OVERFIC_Pos 5 /**< (HSTPIPICR) Overflow Interrupt Clear Position */ -#define HSTPIPICR_OVERFIC (_U_(0x1) << HSTPIPICR_OVERFIC_Pos) /**< (HSTPIPICR) Overflow Interrupt Clear Mask */ -#define HSTPIPICR_SHORTPACKETIC_Pos 7 /**< (HSTPIPICR) Short Packet Interrupt Clear Position */ -#define HSTPIPICR_SHORTPACKETIC (_U_(0x1) << HSTPIPICR_SHORTPACKETIC_Pos) /**< (HSTPIPICR) Short Packet Interrupt Clear Mask */ -#define HSTPIPICR_Msk _U_(0xB3) /**< (HSTPIPICR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPICR_CTRL_TXSTPIC_Pos 2 /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ -#define HSTPIPICR_CTRL_TXSTPIC (_U_(0x1) << HSTPIPICR_CTRL_TXSTPIC_Pos) /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ -#define HSTPIPICR_CTRL_RXSTALLDIC_Pos 6 /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */ -#define HSTPIPICR_CTRL_RXSTALLDIC (_U_(0x1) << HSTPIPICR_CTRL_RXSTALLDIC_Pos) /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */ -#define HSTPIPICR_CTRL_Msk _U_(0x44) /**< (HSTPIPICR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPICR_ISO_UNDERFIC_Pos 2 /**< (HSTPIPICR) Underflow Interrupt Clear Position */ -#define HSTPIPICR_ISO_UNDERFIC (_U_(0x1) << HSTPIPICR_ISO_UNDERFIC_Pos) /**< (HSTPIPICR) Underflow Interrupt Clear Mask */ -#define HSTPIPICR_ISO_CRCERRIC_Pos 6 /**< (HSTPIPICR) CRC Error Interrupt Clear Position */ -#define HSTPIPICR_ISO_CRCERRIC (_U_(0x1) << HSTPIPICR_ISO_CRCERRIC_Pos) /**< (HSTPIPICR) CRC Error Interrupt Clear Mask */ -#define HSTPIPICR_ISO_Msk _U_(0x44) /**< (HSTPIPICR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPICR_BLK_TXSTPIC_Pos 2 /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ -#define HSTPIPICR_BLK_TXSTPIC (_U_(0x1) << HSTPIPICR_BLK_TXSTPIC_Pos) /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ -#define HSTPIPICR_BLK_RXSTALLDIC_Pos 6 /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */ -#define HSTPIPICR_BLK_RXSTALLDIC (_U_(0x1) << HSTPIPICR_BLK_RXSTALLDIC_Pos) /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */ -#define HSTPIPICR_BLK_Msk _U_(0x44) /**< (HSTPIPICR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPICR_INTRPT_UNDERFIC_Pos 2 /**< (HSTPIPICR) Underflow Interrupt Clear Position */ -#define HSTPIPICR_INTRPT_UNDERFIC (_U_(0x1) << HSTPIPICR_INTRPT_UNDERFIC_Pos) /**< (HSTPIPICR) Underflow Interrupt Clear Mask */ -#define HSTPIPICR_INTRPT_RXSTALLDIC_Pos 6 /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */ -#define HSTPIPICR_INTRPT_RXSTALLDIC (_U_(0x1) << HSTPIPICR_INTRPT_RXSTALLDIC_Pos) /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */ -#define HSTPIPICR_INTRPT_Msk _U_(0x44) /**< (HSTPIPICR_INTRPT) Register Mask */ - - -/* -------- HSTPIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */ - -#define HSTPIPIFR_OFFSET (0x590) /**< (HSTPIPIFR) Host Pipe Set Register Offset */ - -#define HSTPIPIFR_RXINIS_Pos 0 /**< (HSTPIPIFR) Received IN Data Interrupt Set Position */ -#define HSTPIPIFR_RXINIS (_U_(0x1) << HSTPIPIFR_RXINIS_Pos) /**< (HSTPIPIFR) Received IN Data Interrupt Set Mask */ -#define HSTPIPIFR_TXOUTIS_Pos 1 /**< (HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */ -#define HSTPIPIFR_TXOUTIS (_U_(0x1) << HSTPIPIFR_TXOUTIS_Pos) /**< (HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */ -#define HSTPIPIFR_PERRIS_Pos 3 /**< (HSTPIPIFR) Pipe Error Interrupt Set Position */ -#define HSTPIPIFR_PERRIS (_U_(0x1) << HSTPIPIFR_PERRIS_Pos) /**< (HSTPIPIFR) Pipe Error Interrupt Set Mask */ -#define HSTPIPIFR_NAKEDIS_Pos 4 /**< (HSTPIPIFR) NAKed Interrupt Set Position */ -#define HSTPIPIFR_NAKEDIS (_U_(0x1) << HSTPIPIFR_NAKEDIS_Pos) /**< (HSTPIPIFR) NAKed Interrupt Set Mask */ -#define HSTPIPIFR_OVERFIS_Pos 5 /**< (HSTPIPIFR) Overflow Interrupt Set Position */ -#define HSTPIPIFR_OVERFIS (_U_(0x1) << HSTPIPIFR_OVERFIS_Pos) /**< (HSTPIPIFR) Overflow Interrupt Set Mask */ -#define HSTPIPIFR_SHORTPACKETIS_Pos 7 /**< (HSTPIPIFR) Short Packet Interrupt Set Position */ -#define HSTPIPIFR_SHORTPACKETIS (_U_(0x1) << HSTPIPIFR_SHORTPACKETIS_Pos) /**< (HSTPIPIFR) Short Packet Interrupt Set Mask */ -#define HSTPIPIFR_NBUSYBKS_Pos 12 /**< (HSTPIPIFR) Number of Busy Banks Set Position */ -#define HSTPIPIFR_NBUSYBKS (_U_(0x1) << HSTPIPIFR_NBUSYBKS_Pos) /**< (HSTPIPIFR) Number of Busy Banks Set Mask */ -#define HSTPIPIFR_Msk _U_(0x10BB) /**< (HSTPIPIFR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIFR_CTRL_TXSTPIS_Pos 2 /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ -#define HSTPIPIFR_CTRL_TXSTPIS (_U_(0x1) << HSTPIPIFR_CTRL_TXSTPIS_Pos) /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ -#define HSTPIPIFR_CTRL_RXSTALLDIS_Pos 6 /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */ -#define HSTPIPIFR_CTRL_RXSTALLDIS (_U_(0x1) << HSTPIPIFR_CTRL_RXSTALLDIS_Pos) /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */ -#define HSTPIPIFR_CTRL_Msk _U_(0x44) /**< (HSTPIPIFR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIFR_ISO_UNDERFIS_Pos 2 /**< (HSTPIPIFR) Underflow Interrupt Set Position */ -#define HSTPIPIFR_ISO_UNDERFIS (_U_(0x1) << HSTPIPIFR_ISO_UNDERFIS_Pos) /**< (HSTPIPIFR) Underflow Interrupt Set Mask */ -#define HSTPIPIFR_ISO_CRCERRIS_Pos 6 /**< (HSTPIPIFR) CRC Error Interrupt Set Position */ -#define HSTPIPIFR_ISO_CRCERRIS (_U_(0x1) << HSTPIPIFR_ISO_CRCERRIS_Pos) /**< (HSTPIPIFR) CRC Error Interrupt Set Mask */ -#define HSTPIPIFR_ISO_Msk _U_(0x44) /**< (HSTPIPIFR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIFR_BLK_TXSTPIS_Pos 2 /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ -#define HSTPIPIFR_BLK_TXSTPIS (_U_(0x1) << HSTPIPIFR_BLK_TXSTPIS_Pos) /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ -#define HSTPIPIFR_BLK_RXSTALLDIS_Pos 6 /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */ -#define HSTPIPIFR_BLK_RXSTALLDIS (_U_(0x1) << HSTPIPIFR_BLK_RXSTALLDIS_Pos) /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */ -#define HSTPIPIFR_BLK_Msk _U_(0x44) /**< (HSTPIPIFR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIFR_INTRPT_UNDERFIS_Pos 2 /**< (HSTPIPIFR) Underflow Interrupt Set Position */ -#define HSTPIPIFR_INTRPT_UNDERFIS (_U_(0x1) << HSTPIPIFR_INTRPT_UNDERFIS_Pos) /**< (HSTPIPIFR) Underflow Interrupt Set Mask */ -#define HSTPIPIFR_INTRPT_RXSTALLDIS_Pos 6 /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */ -#define HSTPIPIFR_INTRPT_RXSTALLDIS (_U_(0x1) << HSTPIPIFR_INTRPT_RXSTALLDIS_Pos) /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */ -#define HSTPIPIFR_INTRPT_Msk _U_(0x44) /**< (HSTPIPIFR_INTRPT) Register Mask */ - - -/* -------- HSTPIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */ - -#define HSTPIPIMR_OFFSET (0x5C0) /**< (HSTPIPIMR) Host Pipe Mask Register Offset */ - -#define HSTPIPIMR_RXINE_Pos 0 /**< (HSTPIPIMR) Received IN Data Interrupt Enable Position */ -#define HSTPIPIMR_RXINE (_U_(0x1) << HSTPIPIMR_RXINE_Pos) /**< (HSTPIPIMR) Received IN Data Interrupt Enable Mask */ -#define HSTPIPIMR_TXOUTE_Pos 1 /**< (HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */ -#define HSTPIPIMR_TXOUTE (_U_(0x1) << HSTPIPIMR_TXOUTE_Pos) /**< (HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */ -#define HSTPIPIMR_PERRE_Pos 3 /**< (HSTPIPIMR) Pipe Error Interrupt Enable Position */ -#define HSTPIPIMR_PERRE (_U_(0x1) << HSTPIPIMR_PERRE_Pos) /**< (HSTPIPIMR) Pipe Error Interrupt Enable Mask */ -#define HSTPIPIMR_NAKEDE_Pos 4 /**< (HSTPIPIMR) NAKed Interrupt Enable Position */ -#define HSTPIPIMR_NAKEDE (_U_(0x1) << HSTPIPIMR_NAKEDE_Pos) /**< (HSTPIPIMR) NAKed Interrupt Enable Mask */ -#define HSTPIPIMR_OVERFIE_Pos 5 /**< (HSTPIPIMR) Overflow Interrupt Enable Position */ -#define HSTPIPIMR_OVERFIE (_U_(0x1) << HSTPIPIMR_OVERFIE_Pos) /**< (HSTPIPIMR) Overflow Interrupt Enable Mask */ -#define HSTPIPIMR_SHORTPACKETIE_Pos 7 /**< (HSTPIPIMR) Short Packet Interrupt Enable Position */ -#define HSTPIPIMR_SHORTPACKETIE (_U_(0x1) << HSTPIPIMR_SHORTPACKETIE_Pos) /**< (HSTPIPIMR) Short Packet Interrupt Enable Mask */ -#define HSTPIPIMR_NBUSYBKE_Pos 12 /**< (HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */ -#define HSTPIPIMR_NBUSYBKE (_U_(0x1) << HSTPIPIMR_NBUSYBKE_Pos) /**< (HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */ -#define HSTPIPIMR_FIFOCON_Pos 14 /**< (HSTPIPIMR) FIFO Control Position */ -#define HSTPIPIMR_FIFOCON (_U_(0x1) << HSTPIPIMR_FIFOCON_Pos) /**< (HSTPIPIMR) FIFO Control Mask */ -#define HSTPIPIMR_PDISHDMA_Pos 16 /**< (HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ -#define HSTPIPIMR_PDISHDMA (_U_(0x1) << HSTPIPIMR_PDISHDMA_Pos) /**< (HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ -#define HSTPIPIMR_PFREEZE_Pos 17 /**< (HSTPIPIMR) Pipe Freeze Position */ -#define HSTPIPIMR_PFREEZE (_U_(0x1) << HSTPIPIMR_PFREEZE_Pos) /**< (HSTPIPIMR) Pipe Freeze Mask */ -#define HSTPIPIMR_RSTDT_Pos 18 /**< (HSTPIPIMR) Reset Data Toggle Position */ -#define HSTPIPIMR_RSTDT (_U_(0x1) << HSTPIPIMR_RSTDT_Pos) /**< (HSTPIPIMR) Reset Data Toggle Mask */ -#define HSTPIPIMR_Msk _U_(0x750BB) /**< (HSTPIPIMR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIMR_CTRL_TXSTPE_Pos 2 /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIMR_CTRL_TXSTPE (_U_(0x1) << HSTPIPIMR_CTRL_TXSTPE_Pos) /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIMR_CTRL_RXSTALLDE_Pos 6 /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */ -#define HSTPIPIMR_CTRL_RXSTALLDE (_U_(0x1) << HSTPIPIMR_CTRL_RXSTALLDE_Pos) /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIMR_CTRL_Msk _U_(0x44) /**< (HSTPIPIMR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIMR_ISO_UNDERFIE_Pos 2 /**< (HSTPIPIMR) Underflow Interrupt Enable Position */ -#define HSTPIPIMR_ISO_UNDERFIE (_U_(0x1) << HSTPIPIMR_ISO_UNDERFIE_Pos) /**< (HSTPIPIMR) Underflow Interrupt Enable Mask */ -#define HSTPIPIMR_ISO_CRCERRE_Pos 6 /**< (HSTPIPIMR) CRC Error Interrupt Enable Position */ -#define HSTPIPIMR_ISO_CRCERRE (_U_(0x1) << HSTPIPIMR_ISO_CRCERRE_Pos) /**< (HSTPIPIMR) CRC Error Interrupt Enable Mask */ -#define HSTPIPIMR_ISO_Msk _U_(0x44) /**< (HSTPIPIMR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIMR_BLK_TXSTPE_Pos 2 /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIMR_BLK_TXSTPE (_U_(0x1) << HSTPIPIMR_BLK_TXSTPE_Pos) /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIMR_BLK_RXSTALLDE_Pos 6 /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */ -#define HSTPIPIMR_BLK_RXSTALLDE (_U_(0x1) << HSTPIPIMR_BLK_RXSTALLDE_Pos) /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIMR_BLK_Msk _U_(0x44) /**< (HSTPIPIMR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIMR_INTRPT_UNDERFIE_Pos 2 /**< (HSTPIPIMR) Underflow Interrupt Enable Position */ -#define HSTPIPIMR_INTRPT_UNDERFIE (_U_(0x1) << HSTPIPIMR_INTRPT_UNDERFIE_Pos) /**< (HSTPIPIMR) Underflow Interrupt Enable Mask */ -#define HSTPIPIMR_INTRPT_RXSTALLDE_Pos 6 /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */ -#define HSTPIPIMR_INTRPT_RXSTALLDE (_U_(0x1) << HSTPIPIMR_INTRPT_RXSTALLDE_Pos) /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIMR_INTRPT_Msk _U_(0x44) /**< (HSTPIPIMR_INTRPT) Register Mask */ - - -/* -------- HSTPIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */ - -#define HSTPIPIER_OFFSET (0x5F0) /**< (HSTPIPIER) Host Pipe Enable Register Offset */ - -#define HSTPIPIER_RXINES_Pos 0 /**< (HSTPIPIER) Received IN Data Interrupt Enable Position */ -#define HSTPIPIER_RXINES (_U_(0x1) << HSTPIPIER_RXINES_Pos) /**< (HSTPIPIER) Received IN Data Interrupt Enable Mask */ -#define HSTPIPIER_TXOUTES_Pos 1 /**< (HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */ -#define HSTPIPIER_TXOUTES (_U_(0x1) << HSTPIPIER_TXOUTES_Pos) /**< (HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */ -#define HSTPIPIER_PERRES_Pos 3 /**< (HSTPIPIER) Pipe Error Interrupt Enable Position */ -#define HSTPIPIER_PERRES (_U_(0x1) << HSTPIPIER_PERRES_Pos) /**< (HSTPIPIER) Pipe Error Interrupt Enable Mask */ -#define HSTPIPIER_NAKEDES_Pos 4 /**< (HSTPIPIER) NAKed Interrupt Enable Position */ -#define HSTPIPIER_NAKEDES (_U_(0x1) << HSTPIPIER_NAKEDES_Pos) /**< (HSTPIPIER) NAKed Interrupt Enable Mask */ -#define HSTPIPIER_OVERFIES_Pos 5 /**< (HSTPIPIER) Overflow Interrupt Enable Position */ -#define HSTPIPIER_OVERFIES (_U_(0x1) << HSTPIPIER_OVERFIES_Pos) /**< (HSTPIPIER) Overflow Interrupt Enable Mask */ -#define HSTPIPIER_SHORTPACKETIES_Pos 7 /**< (HSTPIPIER) Short Packet Interrupt Enable Position */ -#define HSTPIPIER_SHORTPACKETIES (_U_(0x1) << HSTPIPIER_SHORTPACKETIES_Pos) /**< (HSTPIPIER) Short Packet Interrupt Enable Mask */ -#define HSTPIPIER_NBUSYBKES_Pos 12 /**< (HSTPIPIER) Number of Busy Banks Enable Position */ -#define HSTPIPIER_NBUSYBKES (_U_(0x1) << HSTPIPIER_NBUSYBKES_Pos) /**< (HSTPIPIER) Number of Busy Banks Enable Mask */ -#define HSTPIPIER_PDISHDMAS_Pos 16 /**< (HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ -#define HSTPIPIER_PDISHDMAS (_U_(0x1) << HSTPIPIER_PDISHDMAS_Pos) /**< (HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ -#define HSTPIPIER_PFREEZES_Pos 17 /**< (HSTPIPIER) Pipe Freeze Enable Position */ -#define HSTPIPIER_PFREEZES (_U_(0x1) << HSTPIPIER_PFREEZES_Pos) /**< (HSTPIPIER) Pipe Freeze Enable Mask */ -#define HSTPIPIER_RSTDTS_Pos 18 /**< (HSTPIPIER) Reset Data Toggle Enable Position */ -#define HSTPIPIER_RSTDTS (_U_(0x1) << HSTPIPIER_RSTDTS_Pos) /**< (HSTPIPIER) Reset Data Toggle Enable Mask */ -#define HSTPIPIER_Msk _U_(0x710BB) /**< (HSTPIPIER) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIER_CTRL_TXSTPES_Pos 2 /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIER_CTRL_TXSTPES (_U_(0x1) << HSTPIPIER_CTRL_TXSTPES_Pos) /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIER_CTRL_RXSTALLDES_Pos 6 /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */ -#define HSTPIPIER_CTRL_RXSTALLDES (_U_(0x1) << HSTPIPIER_CTRL_RXSTALLDES_Pos) /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIER_CTRL_Msk _U_(0x44) /**< (HSTPIPIER_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIER_ISO_UNDERFIES_Pos 2 /**< (HSTPIPIER) Underflow Interrupt Enable Position */ -#define HSTPIPIER_ISO_UNDERFIES (_U_(0x1) << HSTPIPIER_ISO_UNDERFIES_Pos) /**< (HSTPIPIER) Underflow Interrupt Enable Mask */ -#define HSTPIPIER_ISO_CRCERRES_Pos 6 /**< (HSTPIPIER) CRC Error Interrupt Enable Position */ -#define HSTPIPIER_ISO_CRCERRES (_U_(0x1) << HSTPIPIER_ISO_CRCERRES_Pos) /**< (HSTPIPIER) CRC Error Interrupt Enable Mask */ -#define HSTPIPIER_ISO_Msk _U_(0x44) /**< (HSTPIPIER_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIER_BLK_TXSTPES_Pos 2 /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIER_BLK_TXSTPES (_U_(0x1) << HSTPIPIER_BLK_TXSTPES_Pos) /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIER_BLK_RXSTALLDES_Pos 6 /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */ -#define HSTPIPIER_BLK_RXSTALLDES (_U_(0x1) << HSTPIPIER_BLK_RXSTALLDES_Pos) /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIER_BLK_Msk _U_(0x44) /**< (HSTPIPIER_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIER_INTRPT_UNDERFIES_Pos 2 /**< (HSTPIPIER) Underflow Interrupt Enable Position */ -#define HSTPIPIER_INTRPT_UNDERFIES (_U_(0x1) << HSTPIPIER_INTRPT_UNDERFIES_Pos) /**< (HSTPIPIER) Underflow Interrupt Enable Mask */ -#define HSTPIPIER_INTRPT_RXSTALLDES_Pos 6 /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */ -#define HSTPIPIER_INTRPT_RXSTALLDES (_U_(0x1) << HSTPIPIER_INTRPT_RXSTALLDES_Pos) /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIER_INTRPT_Msk _U_(0x44) /**< (HSTPIPIER_INTRPT) Register Mask */ - - -/* -------- HSTPIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */ - -#define HSTPIPIDR_OFFSET (0x620) /**< (HSTPIPIDR) Host Pipe Disable Register Offset */ - -#define HSTPIPIDR_RXINEC_Pos 0 /**< (HSTPIPIDR) Received IN Data Interrupt Disable Position */ -#define HSTPIPIDR_RXINEC (_U_(0x1) << HSTPIPIDR_RXINEC_Pos) /**< (HSTPIPIDR) Received IN Data Interrupt Disable Mask */ -#define HSTPIPIDR_TXOUTEC_Pos 1 /**< (HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */ -#define HSTPIPIDR_TXOUTEC (_U_(0x1) << HSTPIPIDR_TXOUTEC_Pos) /**< (HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */ -#define HSTPIPIDR_PERREC_Pos 3 /**< (HSTPIPIDR) Pipe Error Interrupt Disable Position */ -#define HSTPIPIDR_PERREC (_U_(0x1) << HSTPIPIDR_PERREC_Pos) /**< (HSTPIPIDR) Pipe Error Interrupt Disable Mask */ -#define HSTPIPIDR_NAKEDEC_Pos 4 /**< (HSTPIPIDR) NAKed Interrupt Disable Position */ -#define HSTPIPIDR_NAKEDEC (_U_(0x1) << HSTPIPIDR_NAKEDEC_Pos) /**< (HSTPIPIDR) NAKed Interrupt Disable Mask */ -#define HSTPIPIDR_OVERFIEC_Pos 5 /**< (HSTPIPIDR) Overflow Interrupt Disable Position */ -#define HSTPIPIDR_OVERFIEC (_U_(0x1) << HSTPIPIDR_OVERFIEC_Pos) /**< (HSTPIPIDR) Overflow Interrupt Disable Mask */ -#define HSTPIPIDR_SHORTPACKETIEC_Pos 7 /**< (HSTPIPIDR) Short Packet Interrupt Disable Position */ -#define HSTPIPIDR_SHORTPACKETIEC (_U_(0x1) << HSTPIPIDR_SHORTPACKETIEC_Pos) /**< (HSTPIPIDR) Short Packet Interrupt Disable Mask */ -#define HSTPIPIDR_NBUSYBKEC_Pos 12 /**< (HSTPIPIDR) Number of Busy Banks Disable Position */ -#define HSTPIPIDR_NBUSYBKEC (_U_(0x1) << HSTPIPIDR_NBUSYBKEC_Pos) /**< (HSTPIPIDR) Number of Busy Banks Disable Mask */ -#define HSTPIPIDR_FIFOCONC_Pos 14 /**< (HSTPIPIDR) FIFO Control Disable Position */ -#define HSTPIPIDR_FIFOCONC (_U_(0x1) << HSTPIPIDR_FIFOCONC_Pos) /**< (HSTPIPIDR) FIFO Control Disable Mask */ -#define HSTPIPIDR_PDISHDMAC_Pos 16 /**< (HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ -#define HSTPIPIDR_PDISHDMAC (_U_(0x1) << HSTPIPIDR_PDISHDMAC_Pos) /**< (HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ -#define HSTPIPIDR_PFREEZEC_Pos 17 /**< (HSTPIPIDR) Pipe Freeze Disable Position */ -#define HSTPIPIDR_PFREEZEC (_U_(0x1) << HSTPIPIDR_PFREEZEC_Pos) /**< (HSTPIPIDR) Pipe Freeze Disable Mask */ -#define HSTPIPIDR_Msk _U_(0x350BB) /**< (HSTPIPIDR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIDR_CTRL_TXSTPEC_Pos 2 /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ -#define HSTPIPIDR_CTRL_TXSTPEC (_U_(0x1) << HSTPIPIDR_CTRL_TXSTPEC_Pos) /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ -#define HSTPIPIDR_CTRL_RXSTALLDEC_Pos 6 /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */ -#define HSTPIPIDR_CTRL_RXSTALLDEC (_U_(0x1) << HSTPIPIDR_CTRL_RXSTALLDEC_Pos) /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */ -#define HSTPIPIDR_CTRL_Msk _U_(0x44) /**< (HSTPIPIDR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIDR_ISO_UNDERFIEC_Pos 2 /**< (HSTPIPIDR) Underflow Interrupt Disable Position */ -#define HSTPIPIDR_ISO_UNDERFIEC (_U_(0x1) << HSTPIPIDR_ISO_UNDERFIEC_Pos) /**< (HSTPIPIDR) Underflow Interrupt Disable Mask */ -#define HSTPIPIDR_ISO_CRCERREC_Pos 6 /**< (HSTPIPIDR) CRC Error Interrupt Disable Position */ -#define HSTPIPIDR_ISO_CRCERREC (_U_(0x1) << HSTPIPIDR_ISO_CRCERREC_Pos) /**< (HSTPIPIDR) CRC Error Interrupt Disable Mask */ -#define HSTPIPIDR_ISO_Msk _U_(0x44) /**< (HSTPIPIDR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIDR_BLK_TXSTPEC_Pos 2 /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ -#define HSTPIPIDR_BLK_TXSTPEC (_U_(0x1) << HSTPIPIDR_BLK_TXSTPEC_Pos) /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ -#define HSTPIPIDR_BLK_RXSTALLDEC_Pos 6 /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */ -#define HSTPIPIDR_BLK_RXSTALLDEC (_U_(0x1) << HSTPIPIDR_BLK_RXSTALLDEC_Pos) /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */ -#define HSTPIPIDR_BLK_Msk _U_(0x44) /**< (HSTPIPIDR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIDR_INTRPT_UNDERFIEC_Pos 2 /**< (HSTPIPIDR) Underflow Interrupt Disable Position */ -#define HSTPIPIDR_INTRPT_UNDERFIEC (_U_(0x1) << HSTPIPIDR_INTRPT_UNDERFIEC_Pos) /**< (HSTPIPIDR) Underflow Interrupt Disable Mask */ -#define HSTPIPIDR_INTRPT_RXSTALLDEC_Pos 6 /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */ -#define HSTPIPIDR_INTRPT_RXSTALLDEC (_U_(0x1) << HSTPIPIDR_INTRPT_RXSTALLDEC_Pos) /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */ -#define HSTPIPIDR_INTRPT_Msk _U_(0x44) /**< (HSTPIPIDR_INTRPT) Register Mask */ - - -/* -------- HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */ - -#define HSTPIPINRQ_OFFSET (0x650) /**< (HSTPIPINRQ) Host Pipe IN Request Register Offset */ - -#define HSTPIPINRQ_INRQ_Pos 0 /**< (HSTPIPINRQ) IN Request Number before Freeze Position */ -#define HSTPIPINRQ_INRQ (_U_(0xFF) << HSTPIPINRQ_INRQ_Pos) /**< (HSTPIPINRQ) IN Request Number before Freeze Mask */ -#define HSTPIPINRQ_INMODE_Pos 8 /**< (HSTPIPINRQ) IN Request Mode Position */ -#define HSTPIPINRQ_INMODE (_U_(0x1) << HSTPIPINRQ_INMODE_Pos) /**< (HSTPIPINRQ) IN Request Mode Mask */ -#define HSTPIPINRQ_Msk _U_(0x1FF) /**< (HSTPIPINRQ) Register Mask */ - - -/* -------- HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */ - -#define HSTPIPERR_OFFSET (0x680) /**< (HSTPIPERR) Host Pipe Error Register Offset */ - -#define HSTPIPERR_DATATGL_Pos 0 /**< (HSTPIPERR) Data Toggle Error Position */ -#define HSTPIPERR_DATATGL (_U_(0x1) << HSTPIPERR_DATATGL_Pos) /**< (HSTPIPERR) Data Toggle Error Mask */ -#define HSTPIPERR_DATAPID_Pos 1 /**< (HSTPIPERR) Data PID Error Position */ -#define HSTPIPERR_DATAPID (_U_(0x1) << HSTPIPERR_DATAPID_Pos) /**< (HSTPIPERR) Data PID Error Mask */ -#define HSTPIPERR_PID_Pos 2 /**< (HSTPIPERR) Data PID Error Position */ -#define HSTPIPERR_PID (_U_(0x1) << HSTPIPERR_PID_Pos) /**< (HSTPIPERR) Data PID Error Mask */ -#define HSTPIPERR_TIMEOUT_Pos 3 /**< (HSTPIPERR) Time-Out Error Position */ -#define HSTPIPERR_TIMEOUT (_U_(0x1) << HSTPIPERR_TIMEOUT_Pos) /**< (HSTPIPERR) Time-Out Error Mask */ -#define HSTPIPERR_CRC16_Pos 4 /**< (HSTPIPERR) CRC16 Error Position */ -#define HSTPIPERR_CRC16 (_U_(0x1) << HSTPIPERR_CRC16_Pos) /**< (HSTPIPERR) CRC16 Error Mask */ -#define HSTPIPERR_COUNTER_Pos 5 /**< (HSTPIPERR) Error Counter Position */ -#define HSTPIPERR_COUNTER (_U_(0x3) << HSTPIPERR_COUNTER_Pos) /**< (HSTPIPERR) Error Counter Mask */ -#define HSTPIPERR_Msk _U_(0x7F) /**< (HSTPIPERR) Register Mask */ - -#define HSTPIPERR_CRC_Pos 4 /**< (HSTPIPERR Position) CRCx6 Error */ -#define HSTPIPERR_CRC (_U_(0x1) << HSTPIPERR_CRC_Pos) /**< (HSTPIPERR Mask) CRC */ - -/* -------- CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ - -#define CTRL_OFFSET (0x800) /**< (CTRL) General Control Register Offset */ - -#define CTRL_RDERRE_Pos 4 /**< (CTRL) Remote Device Connection Error Interrupt Enable Position */ -#define CTRL_RDERRE (_U_(0x1) << CTRL_RDERRE_Pos) /**< (CTRL) Remote Device Connection Error Interrupt Enable Mask */ -#define CTRL_VBUSHWC_Pos 8 /**< (CTRL) VBUS Hardware Control Position */ -#define CTRL_VBUSHWC (_U_(0x1) << CTRL_VBUSHWC_Pos) /**< (CTRL) VBUS Hardware Control Mask */ -#define CTRL_FRZCLK_Pos 14 /**< (CTRL) Freeze USB Clock Position */ -#define CTRL_FRZCLK (_U_(0x1) << CTRL_FRZCLK_Pos) /**< (CTRL) Freeze USB Clock Mask */ -#define CTRL_USBE_Pos 15 /**< (CTRL) USBHS Enable Position */ -#define CTRL_USBE (_U_(0x1) << CTRL_USBE_Pos) /**< (CTRL) USBHS Enable Mask */ -#define CTRL_UID_Pos 24 /**< (CTRL) UID Pin Enable Position */ -#define CTRL_UID (_U_(0x1) << CTRL_UID_Pos) /**< (CTRL) UID Pin Enable Mask */ -#define CTRL_UIMOD_Pos 25 /**< (CTRL) USBHS Mode Position */ -#define CTRL_UIMOD (_U_(0x1) << CTRL_UIMOD_Pos) /**< (CTRL) USBHS Mode Mask */ -#define CTRL_UIMOD_HOST_Val _U_(0x0) /**< (CTRL) The module is in USB Host mode. */ -#define CTRL_UIMOD_DEVICE_Val _U_(0x1) /**< (CTRL) The module is in USB Device mode. */ -#define CTRL_UIMOD_HOST (CTRL_UIMOD_HOST_Val << CTRL_UIMOD_Pos) /**< (CTRL) The module is in USB Host mode. Position */ -#define CTRL_UIMOD_DEVICE (CTRL_UIMOD_DEVICE_Val << CTRL_UIMOD_Pos) /**< (CTRL) The module is in USB Device mode. Position */ -#define CTRL_Msk _U_(0x300C110) /**< (CTRL) Register Mask */ - - -/* -------- SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */ - -#define SR_OFFSET (0x804) /**< (SR) General Status Register Offset */ - -#define SR_RDERRI_Pos 4 /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Position */ -#define SR_RDERRI (_U_(0x1) << SR_RDERRI_Pos) /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ -#define SR_SPEED_Pos 12 /**< (SR) Speed Status (Device mode only) Position */ -#define SR_SPEED (_U_(0x3) << SR_SPEED_Pos) /**< (SR) Speed Status (Device mode only) Mask */ -#define SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (SR) Full-Speed mode */ -#define SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (SR) High-Speed mode */ -#define SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (SR) Low-Speed mode */ -#define SR_SPEED_FULL_SPEED (SR_SPEED_FULL_SPEED_Val << SR_SPEED_Pos) /**< (SR) Full-Speed mode Position */ -#define SR_SPEED_HIGH_SPEED (SR_SPEED_HIGH_SPEED_Val << SR_SPEED_Pos) /**< (SR) High-Speed mode Position */ -#define SR_SPEED_LOW_SPEED (SR_SPEED_LOW_SPEED_Val << SR_SPEED_Pos) /**< (SR) Low-Speed mode Position */ -#define SR_CLKUSABLE_Pos 14 /**< (SR) UTMI Clock Usable Position */ -#define SR_CLKUSABLE (_U_(0x1) << SR_CLKUSABLE_Pos) /**< (SR) UTMI Clock Usable Mask */ -#define SR_Msk _U_(0x7010) /**< (SR) Register Mask */ - - -/* -------- SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */ - -#define SCR_OFFSET (0x808) /**< (SCR) General Status Clear Register Offset */ - -#define SCR_RDERRIC_Pos 4 /**< (SCR) Remote Device Connection Error Interrupt Clear Position */ -#define SCR_RDERRIC (_U_(0x1) << SCR_RDERRIC_Pos) /**< (SCR) Remote Device Connection Error Interrupt Clear Mask */ -#define SCR_Msk _U_(0x10) /**< (SCR) Register Mask */ - - -/* -------- SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */ - -#define SFR_OFFSET (0x80C) /**< (SFR) General Status Set Register Offset */ - -#define SFR_RDERRIS_Pos 4 /**< (SFR) Remote Device Connection Error Interrupt Set Position */ -#define SFR_RDERRIS (_U_(0x1) << SFR_RDERRIS_Pos) /**< (SFR) Remote Device Connection Error Interrupt Set Mask */ -#define SFR_VBUSRQS_Pos 9 /**< (SFR) VBUS Request Set Position */ -#define SFR_VBUSRQS (_U_(0x1) << SFR_VBUSRQS_Pos) /**< (SFR) VBUS Request Set Mask */ -#define SFR_Msk _U_(0x210) /**< (SFR) Register Mask */ - - -/** \brief DEVDMA hardware registers */ -typedef struct -{ - __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */ - __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */ - __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */ - __IO uint32_t DEVDMASTATUS; /**< (DEVDMA Offset: 0x0C) Device DMA Channel Status Register */ -} devdma_t; - -/** \brief HSTDMA hardware registers */ -typedef struct -{ - __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */ - __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */ - __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */ - __IO uint32_t HSTDMASTATUS; /**< (HSTDMA Offset: 0x0C) Host DMA Channel Status Register */ -} hstdma_t; - -/** \brief USBHS hardware registers */ -typedef struct -{ - __IO uint32_t DEVCTRL; /**< (USBHS Offset: 0x00) Device General Control Register */ - __I uint32_t DEVISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */ - __O uint32_t DEVICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */ - __O uint32_t DEVIFR; /**< (USBHS Offset: 0x0C) Device Global Interrupt Set Register */ - __I uint32_t DEVIMR; /**< (USBHS Offset: 0x10) Device Global Interrupt Mask Register */ - __O uint32_t DEVIDR; /**< (USBHS Offset: 0x14) Device Global Interrupt Disable Register */ - __O uint32_t DEVIER; /**< (USBHS Offset: 0x18) Device Global Interrupt Enable Register */ - __IO uint32_t DEVEPT; /**< (USBHS Offset: 0x1C) Device Endpoint Register */ - __I uint32_t DEVFNUM; /**< (USBHS Offset: 0x20) Device Frame Number Register */ - __I uint8_t Reserved1[220]; - __IO uint32_t DEVEPTCFG[10]; /**< (USBHS Offset: 0x100) Device Endpoint Configuration Register */ - __I uint8_t Reserved2[8]; - __I uint32_t DEVEPTISR[10]; /**< (USBHS Offset: 0x130) Device Endpoint Interrupt Status Register */ - __I uint8_t Reserved3[8]; - __O uint32_t DEVEPTICR[10]; /**< (USBHS Offset: 0x160) Device Endpoint Interrupt Clear Register */ - __I uint8_t Reserved4[8]; - __O uint32_t DEVEPTIFR[10]; /**< (USBHS Offset: 0x190) Device Endpoint Interrupt Set Register */ - __I uint8_t Reserved5[8]; - __I uint32_t DEVEPTIMR[10]; /**< (USBHS Offset: 0x1C0) Device Endpoint Interrupt Mask Register */ - __I uint8_t Reserved6[8]; - __O uint32_t DEVEPTIER[10]; /**< (USBHS Offset: 0x1F0) Device Endpoint Interrupt Enable Register */ - __I uint8_t Reserved7[8]; - __O uint32_t DEVEPTIDR[10]; /**< (USBHS Offset: 0x220) Device Endpoint Interrupt Disable Register */ - __I uint8_t Reserved8[200]; - devdma_t DEVDMA[7]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ - __I uint8_t Reserved9[128]; - __IO uint32_t HSTCTRL; /**< (USBHS Offset: 0x400) Host General Control Register */ - __I uint32_t HSTISR; /**< (USBHS Offset: 0x404) Host Global Interrupt Status Register */ - __O uint32_t HSTICR; /**< (USBHS Offset: 0x408) Host Global Interrupt Clear Register */ - __O uint32_t HSTIFR; /**< (USBHS Offset: 0x40C) Host Global Interrupt Set Register */ - __I uint32_t HSTIMR; /**< (USBHS Offset: 0x410) Host Global Interrupt Mask Register */ - __O uint32_t HSTIDR; /**< (USBHS Offset: 0x414) Host Global Interrupt Disable Register */ - __O uint32_t HSTIER; /**< (USBHS Offset: 0x418) Host Global Interrupt Enable Register */ - __IO uint32_t HSTPIP; /**< (USBHS Offset: 0x41C) Host Pipe Register */ - __IO uint32_t HSTFNUM; /**< (USBHS Offset: 0x420) Host Frame Number Register */ - __IO uint32_t HSTADDR1; /**< (USBHS Offset: 0x424) Host Address 1 Register */ - __IO uint32_t HSTADDR2; /**< (USBHS Offset: 0x428) Host Address 2 Register */ - __IO uint32_t HSTADDR3; /**< (USBHS Offset: 0x42C) Host Address 3 Register */ - __I uint8_t Reserved10[208]; - __IO uint32_t HSTPIPCFG[10]; /**< (USBHS Offset: 0x500) Host Pipe Configuration Register */ - __I uint8_t Reserved11[8]; - __I uint32_t HSTPIPISR[10]; /**< (USBHS Offset: 0x530) Host Pipe Status Register */ - __I uint8_t Reserved12[8]; - __O uint32_t HSTPIPICR[10]; /**< (USBHS Offset: 0x560) Host Pipe Clear Register */ - __I uint8_t Reserved13[8]; - __O uint32_t HSTPIPIFR[10]; /**< (USBHS Offset: 0x590) Host Pipe Set Register */ - __I uint8_t Reserved14[8]; - __I uint32_t HSTPIPIMR[10]; /**< (USBHS Offset: 0x5C0) Host Pipe Mask Register */ - __I uint8_t Reserved15[8]; - __O uint32_t HSTPIPIER[10]; /**< (USBHS Offset: 0x5F0) Host Pipe Enable Register */ - __I uint8_t Reserved16[8]; - __O uint32_t HSTPIPIDR[10]; /**< (USBHS Offset: 0x620) Host Pipe Disable Register */ - __I uint8_t Reserved17[8]; - __IO uint32_t HSTPIPINRQ[10]; /**< (USBHS Offset: 0x650) Host Pipe IN Request Register */ - __I uint8_t Reserved18[8]; - __IO uint32_t HSTPIPERR[10]; /**< (USBHS Offset: 0x680) Host Pipe Error Register */ - __I uint8_t Reserved19[104]; - hstdma_t HSTDMA[7]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ - __I uint8_t Reserved20[128]; - __IO uint32_t CTRL; /**< (USBHS Offset: 0x800) General Control Register */ - __I uint32_t SR; /**< (USBHS Offset: 0x804) General Status Register */ - __O uint32_t SCR; /**< (USBHS Offset: 0x808) General Status Clear Register */ - __O uint32_t SFR; /**< (USBHS Offset: 0x80C) General Status Set Register */ -} dcd_registers_t; - -#define USB_REG ((dcd_registers_t *)0x40038000U) /**< \brief (USBHS) Base Address */ - -#define EP_MAX 10 - -#define FIFO_RAM_ADDR 0xA0100000u - -// Errata: The DMA feature is not available for Pipe/Endpoint 7 -#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6) - -#else // TODO : SAM3U - - -#endif - -#endif /* _COMMON_USB_REGS_H_ */ diff --git a/src/tusb_option.h b/src/tusb_option.h index 206d23e72c..ce115281c2 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -69,6 +69,7 @@ typedef int make_iso_compilers_happy; #define OPT_MCU_SAML22 205 ///< MicroChip SAML22 #define OPT_MCU_SAML21 206 ///< MicroChip SAML21 #define OPT_MCU_SAMX7X 207 ///< MicroChip SAME70, S70, V70, V71 family +#define OPT_MCU_SAM3U 208 ///< MicroChip SAM3U // STM32 #define OPT_MCU_STM32F0 300 ///< ST F0 diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf index ba54fe0578..3f8c024340 100644 --- a/tools/iar_template.ipcf +++ b/tools/iar_template.ipcf @@ -80,8 +80,8 @@ $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + $TUSB_DIR$/src/portable/microchip/samhs/dcd_samhs.c $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c