yosys-plugin segfaults on multi-module designs #466
Comments
cknizek
changed the title
// RUN: outfile=$(mktemp)
// RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \
// RUN: read_verilog %s; \
// RUN: hierarchy -top in_module; \
// RUN: lakeroad in_module; \
// RUN: rename in_module out_module; \
// RUN: write_verilog $outfile"
// RUN: FileCheck %s < $outfile
(* template = "dsp" *)
(* architecture = "xilinx-ultrascale-plus" *)
(* pipeline_depth = 0 *)
module in_module(
(* data *)
input [15:0] a,
(* data *)
input [15:0] b,
(* out *)
output [15:0] p);
impl m(.a(a), .b(b), .o(p));
endmodule
// CHECK: module out_module(a, b, p);
results in the following output when colinknizek@colins-macbook-pro lakeroad % lit -a /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv -- Testing: 1 tests, 1 workers -- FAIL: Lakeroad tests :: example_test_using_include.sv (1 of 1) ******************** TEST 'Lakeroad tests :: example_test_using_include.sv' FAILED ******************** Exit Code: 1 Command Output (stdout): -- /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) -- Running command ` read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.yx17yWGjId' -- 1. Executing Verilog-2005 frontend: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv Parsing Verilog input from `/Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv' to AST representation. Generating RTLIL representation for module `\in_module'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \in_module 2.2. Analyzing design hierarchy.. Top module: \in_module Removed 0 unused modules. 3. Executing Lakeroad pass (technology mapping using Lakeroad). 3.1. Executing Verilog backend. 3.1.1. Executing BMUXMAP pass. 3.1.2. Executing DEMUXMAP pass. -- Command Output (stderr): -- RUN: at line 1: outfile=$(mktemp) ++ mktemp + outfile=/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.yx17yWGjId RUN: at line 2: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog $outfile" + yosys -m /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/yosys-plugin/lakeroad.so -p ' read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.yx17yWGjId' ERROR: Lakeroad execution failed. -- ******************** ******************** Failed Tests (1): Lakeroad tests :: example_test_using_include.sv Testing Time: 30.54s Total Discovered Tests: 1 Failed: 1 (100.00%) |
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// RUN: outfile=$(mktemp)
// RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \
// RUN: read_verilog %s; \
// RUN: hierarchy -top in_module; \
// RUN: lakeroad in_module; \
// RUN: rename in_module out_module; \
// RUN: write_verilog $outfile"
// RUN: FileCheck %s < $outfile
`include "example_test_using_include/impl.sv"
module in_module(
(* data *)
input [15:0] a,
(* data *)
input [15:0] b,
(* out *)
output [15:0] p);
impl m(.a(a), .b(b), .o(p));
endmodule
// CHECK: module out_module(a, b, p);
module impl( (* data *) input [15:0] a, (* data *) input [15:0] b, (* out *) output [15:0] o); assign o = a * b; endmodule results in: colinknizek@colins-macbook-pro lakeroad % lit -a /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv -- Testing: 1 tests, 1 workers -- FAIL: Lakeroad tests :: example_test_using_include.sv (1 of 1) ******************** TEST 'Lakeroad tests :: example_test_using_include.sv' FAILED ******************** Exit Code: 1 Command Output (stdout): -- /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) -- Running command ` read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.LFLSIe3DKZ' -- 1. Executing Verilog-2005 frontend: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv Parsing Verilog input from `/Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv' to AST representation. Generating RTLIL representation for module `\impl'. Generating RTLIL representation for module `\in_module'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \in_module Used module: \impl 2.2. Analyzing design hierarchy.. Top module: \in_module Used module: \impl Removed 0 unused modules. 3. Executing Lakeroad pass (technology mapping using Lakeroad). 3.1. Executing Verilog backend. 3.1.1. Executing BMUXMAP pass. 3.1.2. Executing DEMUXMAP pass. -- Command Output (stderr): -- RUN: at line 1: outfile=$(mktemp) ++ mktemp + outfile=/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.LFLSIe3DKZ RUN: at line 2: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog $outfile" + yosys -m /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/yosys-plugin/lakeroad.so -p ' read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.LFLSIe3DKZ' Unsupported architecture --template. context...: /Applications/Racket v8.13/collects/racket/cmdline.rkt:479:10: call-handler body of "/Users/colinknizek/dev/lakeroad_bitbit/lakeroad/bin/main.rkt" ERROR: Lakeroad execution failed. -- ******************** ******************** Failed Tests (1): Lakeroad tests :: example_test_using_include.sv Testing Time: 30.71s Total Discovered Tests: 1 Failed: 1 (100.00%) |
// RUN: outfile=$(mktemp)
// RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \
// RUN: read_verilog %s; \
// RUN: hierarchy -top in_module; \
// RUN: lakeroad in_module; \
// RUN: rename in_module out_module; \
// RUN: write_verilog $outfile"
// RUN: FileCheck %s < $outfile
(* template = "dsp" *)
(* architecture = "xilinx-ultrascale-plus" *)
(* pipeline_depth = 0 *)
module in_module(
(* data *)
input [15:0] a,
(* data *)
input [15:0] b,
(* out *)
output [15:0] p);
assign p = a * b;
endmodule
// CHECK: module out_module(a, b, p);
results in: colinknizek@colins-macbook-pro lakeroad % lit -a /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv -- Testing: 1 tests, 1 workers -- PASS: Lakeroad tests :: example_test_using_include.sv (1 of 1) Exit Code: 0 Command Output (stdout): -- /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) -- Running command ` read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.LjjXr1BOuU' -- 1. Executing Verilog-2005 frontend: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv Parsing Verilog input from `/Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv' to AST representation. Generating RTLIL representation for module `\in_module'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \in_module 2.2. Analyzing design hierarchy.. Top module: \in_module Removed 0 unused modules. 3. Executing Lakeroad pass (technology mapping using Lakeroad). 3.1. Executing Verilog backend. 3.1.1. Executing BMUXMAP pass. 3.1.2. Executing DEMUXMAP pass. Dumping module `\in_module'. Executing Lakeroad: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/bin/main.rkt --verilog-module-filepath /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-b5yz721a/0501-4b05-dc87-29a5.v --top-module-name in_module --out-filepath /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-b5yz721a/f552-7725-6b84-b148.v --out-format verilog --verilog-module-out-signal p:16 --architecture xilinx-ultrascale-plus --template dsp --module-name in_module_temp_output_from_lakeroad --input-signal a:16 --input-signal b:16 3.2. Executing Verilog-2005 frontend: /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-b5yz721a/f552-7725-6b84-b148.v Parsing Verilog input from `/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-b5yz721a/f552-7725-6b84-b148.v' to AST representation. Generating RTLIL representation for module `\in_module_temp_output_from_lakeroad'. Successfully finished Verilog frontend. Replacing module in_module with the output of Lakeroad Renaming module \in_module to \out_module. 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\out_module'. End of script. Logfile hash: a3e6fe6039, CPU: user 0.00s system 0.01s Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) Time spent: 99% 1x lakeroad (31 sec), 0% 4x read_verilog (0 sec), ... -- Command Output (stderr): -- RUN: at line 1: outfile=$(mktemp) ++ mktemp + outfile=/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.LjjXr1BOuU RUN: at line 2: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog $outfile" + yosys -m /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/yosys-plugin/lakeroad.so -p ' read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.LjjXr1BOuU' RUN: at line 8: FileCheck /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv < $outfile + FileCheck /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv -- ******************** Testing Time: 32.13s Total Discovered Tests: 1 Passed: 1 (100.00%) |
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// RUN: outfile=$(mktemp)
// RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \
// RUN: read_verilog %s; \
// RUN: hierarchy -top in_module; \
// RUN: lakeroad in_module; \
// RUN: rename in_module out_module; \
// RUN: write_verilog $outfile"
// RUN: FileCheck %s < $outfile
`include "example_test_using_include/impl.sv"
(* template = "dsp" *)
(* architecture = "xilinx-ultrascale-plus" *)
(* pipeline_depth = 0 *)
module in_module(
(* data *)
input [15:0] a,
(* data *)
input [15:0] b,
(* out *)
output [15:0] p);
impl m(.a(a), .b(b), .o(p));
endmodule
// CHECK: module out_module(a, b, p);
(* template = "dsp" *) (* architecture = "xilinx-ultrascale-plus" *) (* pipeline_depth = 0 *) module impl( (* data *) input [15:0] a, (* data *) input [15:0] b, (* out *) output [15:0] o); assign o = a * b; endmodule results in: colinknizek@colins-macbook-pro lakeroad % lit -a /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv -- Testing: 1 tests, 1 workers -- PASS: Lakeroad tests :: example_test_using_include.sv (1 of 1) Exit Code: 0 Command Output (stdout): -- /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) -- Running command ` read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.cMlCQ6td7B' -- 1. Executing Verilog-2005 frontend: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv Parsing Verilog input from `/Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv' to AST representation. Generating RTLIL representation for module `\impl'. Generating RTLIL representation for module `\in_module'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \in_module Used module: \impl 2.2. Analyzing design hierarchy.. Top module: \in_module Used module: \impl Removed 0 unused modules. 3. Executing Lakeroad pass (technology mapping using Lakeroad). 3.1. Executing Verilog backend. 3.1.1. Executing BMUXMAP pass. 3.1.2. Executing DEMUXMAP pass. Dumping module `\impl'. Dumping module `\in_module'. Executing Lakeroad: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/bin/main.rkt --verilog-module-filepath /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/dd44-047b-ce49-9464.v --top-module-name in_module --out-filepath /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/37ce-b3d2-0b92-4b8f.v --out-format verilog --verilog-module-out-signal p:16 --architecture xilinx-ultrascale-plus --template dsp --module-name in_module_temp_output_from_lakeroad --input-signal a:16 --input-signal b:16 3.2. Executing Verilog-2005 frontend: /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/37ce-b3d2-0b92-4b8f.v Parsing Verilog input from `/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/37ce-b3d2-0b92-4b8f.v' to AST representation. Generating RTLIL representation for module `\in_module_temp_output_from_lakeroad'. Successfully finished Verilog frontend. Replacing module in_module with the output of Lakeroad 3.3. Executing Verilog backend. 3.3.1. Executing BMUXMAP pass. 3.3.2. Executing DEMUXMAP pass. Dumping module `\impl'. Dumping module `\in_module'. Executing Lakeroad: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/bin/main.rkt --verilog-module-filepath /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/223a-2adb-ae89-3f7d.v --top-module-name impl --out-filepath /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/98ef-e08d-2601-a583.v --out-format verilog --verilog-module-out-signal o:16 --architecture xilinx-ultrascale-plus --template dsp --module-name impl_temp_output_from_lakeroad --input-signal a:16 --input-signal b:16 3.4. Executing Verilog-2005 frontend: /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/98ef-e08d-2601-a583.v Parsing Verilog input from `/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/lit-tmp-zxqaxbor/98ef-e08d-2601-a583.v' to AST representation. Generating RTLIL representation for module `\impl_temp_output_from_lakeroad'. Successfully finished Verilog frontend. Replacing module impl with the output of Lakeroad Renaming module \in_module to \out_module. 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\impl'. Dumping module `\out_module'. End of script. Logfile hash: d9bc07cc59, CPU: user 0.00s system 0.01s Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) Time spent: 99% 1x lakeroad (61 sec), 0% 6x read_verilog (0 sec), ... -- Command Output (stderr): -- RUN: at line 1: outfile=$(mktemp) ++ mktemp + outfile=/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.cMlCQ6td7B RUN: at line 2: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog $outfile" + yosys -m /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/yosys-plugin/lakeroad.so -p ' read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.cMlCQ6td7B' RUN: at line 8: FileCheck /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv < $outfile + FileCheck /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/example_test_using_include.sv -- ******************** Testing Time: 63.18s Total Discovered Tests: 1 Passed: 1 (100.00%) |
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// RUN: outfile=$(mktemp)
// RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \
// RUN: read_verilog %s; \
// RUN: hierarchy -top in_module; \
// RUN: lakeroad in_module; \
// RUN: rename in_module out_module; \
// RUN: write_verilog $outfile"
// RUN: FileCheck %s < $outfile
`include "bsg_dff_chain.sv"
`include "bsg_defines.sv"
(* template = "dsp" *)
(* architecture = "xilinx-ultrascale-plus" *)
(* pipeline_depth = 1 *)
module in_module #(
parameter width_a_p = 13
,parameter width_b_p = 13
,parameter width_c_p = 26
,parameter width_o_p = 27
,parameter pipeline_p = 1
) (
(* data *)
input [width_a_p-1 : 0] a_i,
(* data *)
input [width_b_p-1 : 0] b_i,
(* data *)
input [width_c_p-1 : 0] c_i,
input clk_i,
(* out *)
output [width_o_p-1 : 0] o);
localparam pre_pipeline_lp = pipeline_p > 2 ? 1 : 0;
localparam post_pipeline_lp = pipeline_p > 2 ? pipeline_p -1 : pipeline_p;
wire [width_a_p-1:0] a_r;
wire [width_b_p-1:0] b_r;
wire [width_c_p-1:0] c_r;
bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp)
pre_mul_add (
.clk_i(clk_i)
,.data_i({a_i, b_i, c_i})
,.data_o({a_r, b_r, c_r})
);
wire [width_o_p-1:0] o_r = a_r * b_r + c_r;
bsg_dff_chain #(width_o_p, post_pipeline_lp)
post_mul_add (
.clk_i(clk_i)
,.data_i(o_r)
,.data_o(o)
);
endmodule
// CHECK: module out_module(a_i, b_i, c_i, clk_i, o);
`include "bsg_dff.sv"
`include "bsg_defines.sv"
(* template = "dsp" *)
(* architecture = "xilinx-ultrascale-plus" *)
(* pipeline_depth = 0 *)
module bsg_dff_chain #(
parameter width_p = 27
,parameter num_stages_p = 1
)
(
(* data *)
input clk_i,
(* data *)
input [width_p-1:0] data_i,
(* out *)
output[width_p-1:0] data_o
);
reg [1:0] data_delayed [26:0];
if( num_stages_p == 0) begin:pass_through
wire unused = clk_i;
assign data_o = data_i;
end:pass_through
else begin:chained
assign data_delayed[0] = data_i ;
assign data_o = data_delayed[num_stages_p] ;
genvar i;
for(i=1; i<= 1; i++) begin
bsg_dff #( .width_p ( width_p ) )
ch_reg (
.clk_i ( clk_i )
,.data_i ( data_delayed[ i-1 ] )
,.data_o ( data_delayed[ i ] )
);
end
end:chained
endmodule
(* template = "dsp" *)
(* architecture = "xilinx-ultrascale-plus" *)
(* pipeline_depth = 0 *)
module bsg_dff #(
parameter width_p = 27
,harden_p=0
,strength_p=1 // set drive strength
)
(
(* data *)
input clk_i,
(* data *)
input [width_p-1:0] data_i,
(* out *)
output [width_p-1:0] data_o
);
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
data_r <= data_i;
endmodule
`ifndef BSG_DEFINES_V
`define BSG_DEFINES_V
`define BSG_MAX(x,y) (((x)>(y)) ? (x) : (y))
`define BSG_MIN(x,y) (((x)<(y)) ? (x) : (y))
`define BSG_SIGN_EXTEND(sig, width) \
({{`BSG_MAX(width-$bits(sig),0){sig[$bits(sig)-1]}}, sig[0+:`BSG_MIN(width, $bits(sig))]})
`define BSG_ZERO_EXTEND(sig, width) \
({{`BSG_MAX(width-$bits(sig),0){1'b0}}, sig[0+:`BSG_MIN(width, $bits(sig))]})
// place this macro at the end of a verilog module file if that module has invalid parameters
// that must be specified by the user. this will prevent that module from becoming a top-level
// module per the discussion here: https://github.com/SymbiFlow/sv-tests/issues/1160 and the
// SystemVerilog Standard
// "Top-level modules are modules that are included in the SystemVerilog
// source text, but do not appear in any module instantiation statement, as
// described in 23.3.2. This applies even if the module instantiation appears
// in a generate block that is not itself instantiated (see 27.3). A design
// shall contain at least one top-level module. A top-level module is
// implicitly instantiated once, and its instance name is the same as the
// module name. Such an instance is called a top-level instance."
//
`define BSG_ABSTRACT_MODULE(fn) \
/*verilator lint_off DECLFILENAME*/ \
/*verilator lint_off PINMISSING*/ \
module fn``__abstract(); if (0) fn not_used(); endmodule \
/*verilator lint_on PINMISSING*/ \
/*verilator lint_on DECLFILENAME*/
// macro for defining invalid parameter; with the abstract module declaration
// it should be sufficient to omit the "inv" but we include this for tool portability
// if later we find that all tools are compatible, we can remove the use of this from BaseJump STL
`ifdef XCELIUM // Bare default parameters are incompatible as of 20.09.012
// = "inv" causes type inference mismatch as of 20.09.012
`define BSG_INV_PARAM(param) param = -1
`elsif YOSYS // Bare default parameters are incompatible as of 0.9
`define BSG_INV_PARAM(param) param = "inv"
`else // VIVADO, DC, VERILATOR, GENUS, SURELOG
`define BSG_INV_PARAM(param) param
`endif
// maps 1 --> 1 instead of to 0
`define BSG_SAFE_CLOG2(x) ( (((x)==1) || ((x)==0))? 1 : $clog2((x)))
`define BSG_IS_POW2(x) ( (1 << $clog2(x)) == (x))
`define BSG_WIDTH(x) ($clog2(x+1))
`define BSG_SAFE_MINUS(x, y) (((x)<(y))) ? 0 : ((x)-(y))
// calculate ceil(x/y)
`define BSG_CDIV(x,y) (((x)+(y)-1)/(y))
`ifdef SYNTHESIS
`define BSG_UNDEFINED_IN_SIM(val) (val)
`else
`define BSG_UNDEFINED_IN_SIM(val) ('X)
`endif
`ifdef VERILATOR
`define BSG_HIDE_FROM_VERILATOR(val)
`else
`define BSG_HIDE_FROM_VERILATOR(val) val
`endif
`ifdef SYNTHESIS
`define BSG_DISCONNECTED_IN_SIM(val) (val)
`elsif VERILATOR
`define BSG_DISCONNECTED_IN_SIM(val) (val)
`else
`define BSG_DISCONNECTED_IN_SIM(val) ('z)
`endif
// Ufortunately per the Xilinx forums, Xilinx does not define
// any variable that indicates that Vivado Synthesis is running
// so as a result we identify Vivado merely as the exclusion of
// Synopsys Design Compiler (DC). Support beyond DC and Vivado
// will require modification of this macro.
`ifdef SYNTHESIS
`ifdef DC
`define BSG_VIVADO_SYNTH_FAILS
`elsif CDS_TOOL_DEFINE
`define BSG_VIVADO_SYNTH_FAILS
`elsif SURELOG
`define BSG_VIVADO_SYNTH_FAILS
`elsif YOSYS
`define BSG_VIVADO_SYNTH_FAILS
`else
`define BSG_VIVADO_SYNTH_FAILS this_module_is_not_synthesizeable_in_vivado
`endif
`else
`define BSG_VIVADO_SYNTH_FAILS
`endif
`define BSG_STRINGIFY(x) `"x`"
// For the modules that must be hardened, add this macro at the top.
`ifdef SYNTHESIS
`define BSG_SYNTH_MUST_HARDEN this_module_must_be_hardened
`else
`define BSG_SYNTH_MUST_HARDEN
`endif
// using C-style shifts instead of a[i] allows the parameter of BSG_GET_BIT to be a parameter subrange
// e.g., parameter[4:1][1], which DC 2016.12 does not allow
`define BSG_GET_BIT(X,NUM) (((X)>>(NUM))&1'b1)
// This version of countones works in synthesis, but only up to 64 bits
// we do a funny thing where we propagate X's in simulation if it is more than 64 bits
// and in synthesis, go ahead and ignore the high bits
`define BSG_COUNTONES_SYNTH(y) (($bits(y) < 65) ? 1'b0 : `BSG_UNDEFINED_IN_SIM(1'b0)) + (`BSG_GET_BIT(y,0) +`BSG_GET_BIT(y,1) +`BSG_GET_BIT(y,2) +`BSG_GET_BIT(y,3) +`BSG_GET_BIT(y,4) +`BSG_GET_BIT(y,5) +`BSG_GET_BIT(y,6)+`BSG_GET_BIT(y,7) +`BSG_GET_BIT(y,8)+`BSG_GET_BIT(y,9) \
+`BSG_GET_BIT(y,10)+`BSG_GET_BIT(y,11)+`BSG_GET_BIT(y,12)+`BSG_GET_BIT(y,13)+`BSG_GET_BIT(y,14)+`BSG_GET_BIT(y,15)+`BSG_GET_BIT(y,16)+`BSG_GET_BIT(y,17)+`BSG_GET_BIT(y,18)+`BSG_GET_BIT(y,19) \
+`BSG_GET_BIT(y,20)+`BSG_GET_BIT(y,21)+`BSG_GET_BIT(y,22)+`BSG_GET_BIT(y,23)+`BSG_GET_BIT(y,24)+`BSG_GET_BIT(y,25)+`BSG_GET_BIT(y,26)+`BSG_GET_BIT(y,27)+`BSG_GET_BIT(y,28)+`BSG_GET_BIT(y,29) \
+`BSG_GET_BIT(y,30)+`BSG_GET_BIT(y,31)+`BSG_GET_BIT(y,32)+`BSG_GET_BIT(y,33)+`BSG_GET_BIT(y,34)+`BSG_GET_BIT(y,35)+`BSG_GET_BIT(y,36)+`BSG_GET_BIT(y,37)+`BSG_GET_BIT(y,38)+`BSG_GET_BIT(y,39) \
+`BSG_GET_BIT(y,40)+`BSG_GET_BIT(y,41)+`BSG_GET_BIT(y,42)+`BSG_GET_BIT(y,43)+`BSG_GET_BIT(y,44)+`BSG_GET_BIT(y,45)+`BSG_GET_BIT(y,46)+`BSG_GET_BIT(y,47)+`BSG_GET_BIT(y,48)+`BSG_GET_BIT(y,49) \
+`BSG_GET_BIT(y,50)+`BSG_GET_BIT(y,51)+`BSG_GET_BIT(y,52)+`BSG_GET_BIT(y,53)+`BSG_GET_BIT(y,54)+`BSG_GET_BIT(y,55)+`BSG_GET_BIT(y,56)+`BSG_GET_BIT(y,57)+`BSG_GET_BIT(y,58)+`BSG_GET_BIT(y,59) \
+`BSG_GET_BIT(y,60)+`BSG_GET_BIT(y,61)+`BSG_GET_BIT(y,62)+`BSG_GET_BIT(y,63))
// nullify rpgroups
`ifndef rpgroup
`define rpgroup(x)
`endif
// verilog preprocessing -> if defined(A) && defined(B) then define C
`define BSG_DEFIF_A_AND_B(A,B,C) \
`undef C \
`ifdef A \
`ifdef B \
`define C \
`endif \
`endif
// verilog preprocessing -> if defined(A) && !defined(B) then define C
`define BSG_DEFIF_A_AND_NOT_B(A,B,C) \
`undef C \
`ifdef A \
`ifndef B \
`define C \
`endif \
`endif
// verilog preprocessing -> if !defined(A) && defined(B) then define C
`define BSG_DEFIF_NOT_A_AND_B(A,B,C) `BSG_DEFIF_A_AND_NOT_B(B,A,C)
// verilog preprocessing -> if !defined(A) && !defined(B) then define C
`define BSG_DEFIF_NOT_A_AND_NOT_B(A,B,C) \
`undef C \
`ifndef A \
`ifndef B \
`define C \
`endif \
`endif
// verilog preprocessing -> if defined(A) || defined(B) then define C
`define BSG_DEFIF_A_OR_B(A,B,C) \
`undef C \
`ifdef A \
`define C \
`endif \
`ifdef B \
`define C \
`endif
// verilog preprocessing -> if defined(A) || !defined(B) then define C
`define BSG_DEFIF_A_OR_NOT_B(A,B,C) \
`undef C \
`ifdef A \
`define C \
`endif \
`ifndef B \
`define C \
`endif
// verilog preprocessing -> if !defined(A) || defined(B) then define C
`define BSG_DEFIF_NOT_A_OR_B(A,B,C) `BSG_DEFIF_A_OR_NOT_B(B,A,C)
// verilog preprocessing -> if !defined(A) || !defined(B) then define C
`define BSG_DEFIF_NOT_A_OR_NOT_B(A,B,C) \
`undef C \
`ifndef A \
`define C \
`endif \
`ifndef B \
`define C \
`endif
`endif
results in: colinknizek@colins-macbook-pro lakeroad % lit -a /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/bsg_mul_add.sv -- Testing: 1 tests, 1 workers -- FAIL: Lakeroad tests :: bsg_mul_add.sv (1 of 1) ******************** TEST 'Lakeroad tests :: bsg_mul_add.sv' FAILED ******************** Exit Code: 1 Command Output (stdout): -- /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f, clang++ 15.0.0 -fPIC -Os) -- Running command ` read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/bsg_mul_add.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.fw8ykAH2VQ' -- 1. Executing Verilog-2005 frontend: /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/bsg_mul_add.sv Parsing Verilog input from `/Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/bsg_mul_add.sv' to AST representation. Generating RTLIL representation for module `\bsg_dff'. Generating RTLIL representation for module `\bsg_dff_chain'. Warning: reg '\data_delayed' is assigned in a continuous assignment at bsg_dff_chain.sv:33.24-33.49. Warning: Replacing memory \data_delayed with list of registers. See bsg_dff_chain.sv:33 Generating RTLIL representation for module `\in_module'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \in_module Used module: \bsg_dff_chain Used module: \bsg_dff Parameter \width_p = 27 2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\bsg_dff'. Parameter \width_p = 27 Generating RTLIL representation for module `$paramod\bsg_dff\width_p=s32'00000000000000000000000000011011'. Reprocessing module bsg_dff_chain because instantiated module $paramod\bsg_dff\width_p=s32'00000000000000000000000000011011 has become available. Generating RTLIL representation for module `\bsg_dff_chain'. Warning: reg '\data_delayed' is assigned in a continuous assignment at bsg_dff_chain.sv:33.24-33.49. Warning: reg '\data_delayed' is assigned in a continuous assignment at bsg_dff_chain.sv:0.0-0.0. Warning: Replacing memory \data_delayed with list of registers. See bsg_dff_chain.sv:33 Parameter 1 (\width_p) = 27 Parameter 2 (\num_stages_p) = 1 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\bsg_dff_chain'. Parameter 1 (\width_p) = 27 Parameter 2 (\num_stages_p) = 1 Generating RTLIL representation for module `$paramod$fbbfd766ffebd65a066ca57f2e47cd4227591125\bsg_dff_chain'. Warning: reg '\data_delayed' is assigned in a continuous assignment at bsg_dff_chain.sv:33.24-33.49. Warning: reg '\data_delayed' is assigned in a continuous assignment at bsg_dff_chain.sv:0.0-0.0. Warning: Replacing memory \data_delayed with list of registers. See bsg_dff_chain.sv:33 Parameter 1 (\width_p) = 52 Parameter 2 (\num_stages_p) = 0 2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\bsg_dff_chain'. Parameter 1 (\width_p) = 52 Parameter 2 (\num_stages_p) = 0 Generating RTLIL representation for module `$paramod$171e8baada6630a6b17606ff4996a28a7711b116\bsg_dff_chain'. 2.5. Analyzing design hierarchy.. Top module: \in_module Used module: $paramod$fbbfd766ffebd65a066ca57f2e47cd4227591125\bsg_dff_chain Used module: \bsg_dff Used module: $paramod$171e8baada6630a6b17606ff4996a28a7711b116\bsg_dff_chain Parameter \width_p = 27 Found cached RTLIL representation for module `$paramod\bsg_dff\width_p=s32'00000000000000000000000000011011'. 2.6. Analyzing design hierarchy.. Top module: \in_module Used module: $paramod$fbbfd766ffebd65a066ca57f2e47cd4227591125\bsg_dff_chain Used module: $paramod\bsg_dff\width_p=s32'00000000000000000000000000011011 Used module: $paramod$171e8baada6630a6b17606ff4996a28a7711b116\bsg_dff_chain 2.7. Analyzing design hierarchy.. Top module: \in_module Used module: $paramod$fbbfd766ffebd65a066ca57f2e47cd4227591125\bsg_dff_chain Used module: $paramod\bsg_dff\width_p=s32'00000000000000000000000000011011 Used module: $paramod$171e8baada6630a6b17606ff4996a28a7711b116\bsg_dff_chain Removing unused module `\bsg_dff_chain'. Removing unused module `\bsg_dff'. Removed 2 unused modules. 3. Executing Lakeroad pass (technology mapping using Lakeroad). 3.1. Executing Verilog backend. 3.1.1. Executing BMUXMAP pass. 3.1.2. Executing DEMUXMAP pass. Dumping module `$paramod$171e8baada6630a6b17606ff4996a28a7711b116\bsg_dff_chain'. Dumping module `$paramod$fbbfd766ffebd65a066ca57f2e47cd4227591125\bsg_dff_chain'. Warning: Module $paramod$fbbfd766ffebd65a066ca57f2e47cd4227591125\bsg_dff_chain contains RTLIL processes with sync rules. Such RTLIL processes can't always be mapped directly to Verilog always blocks. unintended changes in simulation behavior are possible! Use "proc" to convert processes to logic networks and registers. Dumping module `$paramod\bsg_dff\width_p=s32'00000000000000000000000000011011'. Warning: Module $paramod\bsg_dff\width_p=s32'00000000000000000000000000011011 contains RTLIL processes with sync rules. Such RTLIL processes can't always be mapped directly to Verilog always blocks. unintended changes in simulation behavior are possible! Use "proc" to convert processes to logic networks and registers. -- Command Output (stderr): -- RUN: at line 1: outfile=$(mktemp) ++ mktemp + outfile=/var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.fw8ykAH2VQ RUN: at line 2: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/bsg_mul_add.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog $outfile" + yosys -m /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/yosys-plugin/lakeroad.so -p ' read_verilog /Users/colinknizek/dev/lakeroad_bitbit/lakeroad/integration_tests/lakeroad/bsg_mul_add.sv; hierarchy -top in_module; lakeroad in_module; rename in_module out_module; write_verilog /var/folders/rg/jq5symwd1cnc731n43t_4dd00000gn/T/tmp.fw8ykAH2VQ' ERROR: Lakeroad execution failed. -- ******************** ******************** Failed Tests (1): Lakeroad tests :: bsg_mul_add.sv Testing Time: 31.32s Total Discovered Tests: 1 Failed: 1 (100.00%) |
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When Lakeroad is used to synthesize a design with multiple modules,
lakeroad.soexperiences a segmentation fault.The issue seems to be some logic in either
lakeroad.ccor possibly in Yosys.This is particularly problematic when non-synthesizable modules are included in a design.
I think the fix is to re-write
lakeroad.ccsuch that it doesn't expect only a single module to be present in the Lakeroad design. Here's a log of the error occuring when manually usingyosys:Here is the file that Lakeroad is being applied to (variant 1 / modules directly inserted into file)
bsg_muladd_synth.sv// RUN: outfile=$(mktemp) // RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \ // RUN: read_verilog -sv %s; \ // RUN: hierarchy -top in_module; \ // RUN: lakeroad in_module; \ // RUN: rename in_module out_module; \ // RUN: write_verilog $outfile" // RUN: FileCheck %s < $outfile module bsg_dff #( parameter width_p = 27 ) (input clk_i ,input [width_p-1:0] data_i ,output [width_p-1:0] data_o ); reg [width_p-1:0] data_r; assign data_o = data_r; always @(posedge clk_i) data_r <= data_i; endmodule module bsg_dff_chain #( parameter width_p = 27 ,parameter num_stages_p = 1 ) ( input clk_i ,input [width_p-1:0] data_i ,output[width_p-1:0] data_o ); logic [1:0][27-1:0] data_delayed; if( num_stages_p == 0) begin:pass_through wire unused = clk_i; assign data_o = data_i; end:pass_through else begin:chained assign data_delayed[0] = data_i ; assign data_o = data_delayed[num_stages_p] ; genvar i; for(i=1; i<= 1; i++) begin bsg_dff #( .width_p ( width_p ) ) ch_reg ( .clk_i ( clk_i ) ,.data_i ( data_delayed[ i-1 ] ) ,.data_o ( data_delayed[ i ] ) ); end end:chained endmodule (* template = "dsp" *) (* architecture = "xilinx-ultrascale-plus" *) (* pipeline_depth = 0 *) module in_module #( parameter width_a_p = 13 ,parameter width_b_p = 13 ,parameter width_c_p = 26 ,parameter width_o_p = 27 ,parameter pipeline_p = 1 ) ( input [width_a_p-1 : 0] a_i ,input [width_b_p-1 : 0] b_i ,input [width_c_p-1 : 0] c_i ,input clk_i ,output [width_o_p-1 : 0] o ); localparam pre_pipeline_lp = pipeline_p > 2 ? 1 : 0; localparam post_pipeline_lp = pipeline_p > 2 ? pipeline_p -1 : pipeline_p; wire [width_a_p-1:0] a_r; wire [width_b_p-1:0] b_r; wire [width_c_p-1:0] c_r; bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp) pre_mul_add ( .clk_i(clk_i) ,.data_i({a_i, b_i, c_i}) ,.data_o({a_r, b_r, c_r}) ); wire [width_o_p-1:0] o_r = a_r * b_r + c_r; bsg_dff_chain #(width_o_p, post_pipeline_lp) post_mul_add ( .clk_i(clk_i) ,.data_i(o_r) ,.data_o(o) ); endmodule // CHECK: module out_module(a_i, b_i, c_i, clk_i, o); // CHECK: DSP48E2 #( // CHECK: endmoduleHere is the 2nd variant (include statements used, modules in separate files)
bsg_muladd_synth.sv// RUN: outfile=$(mktemp) // RUN: yosys -m "$LAKEROAD_DIR/yosys-plugin/lakeroad.so" -p " \ // RUN: read_verilog -sv %s; \ // RUN: hierarchy -top top; \ // RUN: lakeroad top; \ // RUN: rename top test_module; \ // RUN: write_verilog $outfile" // RUN: FileCheck %s < $outfile // RUN: if [ -z ${LAKEROAD_PRIVATE_DIR+x} ]; then \ // RUN: echo "Warning: LAKEROAD_PRIVATE_DIR is not set. Skipping simulation."; \ // RUN: exit 0; \ // RUN: else \ // RUN: python3 $LAKEROAD_DIR/bin/simulate_with_verilator.py \ // RUN: --test_module_name test_module \ // RUN: --ground_truth_module_name top \ // RUN: --max_num_tests=10000 \ // RUN: --verilog_filepath $outfile \ // RUN: --verilog_filepath %s \ // RUN: --clock_name clk_i \ // RUN: --pipeline_depth 1 \ // RUN: --output_signal o:27 \ // RUN: --input_signal a_i:13 \ // RUN: --input_signal b_i:13 \ // RUN: --input_signal c_i:26 \ // RUN: --verilator_include_dir "$LAKEROAD_PRIVATE_DIR/DSP48E2/" \ // RUN: --testbench_stdout_log_filepath "tmp.log" \ // RUN: --verilator_extra_arg='-DXIL_XECLIB' \ // RUN: --verilator_extra_arg='-Wno-UNOPTFLAT' \ // RUN: --verilator_extra_arg='-Wno-LATCH' \ // RUN: --verilator_extra_arg='-Wno-WIDTH' \ // RUN: --verilator_extra_arg='-Wno-STMTDLY' \ // RUN: --verilator_extra_arg='-Wno-CASEX' \ // RUN: --verilator_extra_arg='-Wno-TIMESCALEMOD' \ // RUN: --verilator_extra_arg='-Wno-PINMISSING'; \ // RUN: fi `include "bsg_defines.sv" `include "bsg_dff_chain.sv" (* use_dsp = "yes" *) module top #( parameter width_a_p = 13 ,parameter width_b_p = 13 ,parameter width_c_p = 26 ,parameter width_o_p = 27 ,parameter pipeline_p = 1 ) ( input [width_a_p-1 : 0] a_i ,input [width_b_p-1 : 0] b_i ,input [width_c_p-1 : 0] c_i ,input clk_i ,output [width_o_p-1 : 0] o ); localparam pre_pipeline_lp = pipeline_p > 2 ? 1 : 0; localparam post_pipeline_lp = pipeline_p > 2 ? pipeline_p -1 : pipeline_p; //for excess wire [width_a_p-1:0] a_r; wire [width_b_p-1:0] b_r; wire [width_c_p-1:0] c_r; bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp) pre_mul_add ( .clk_i(clk_i) ,.data_i({a_i, b_i, c_i}) ,.data_o({a_r, b_r, c_r}) ); wire [width_o_p-1:0] o_r = a_r * b_r + c_r; bsg_dff_chain #(width_o_p, post_pipeline_lp) post_mul_add ( .clk_i(clk_i) ,.data_i(o_r) ,.data_o(o) ); endmodule // CHECK: module test_module(a_i, b_i, c_i, clk_i, o); // CHECK: DSP48E2 #( // CHECK: endmoduleThe text was updated successfully, but these errors were encountered: