[fuzzer]: Seemingly spurious assertion firing #1933
Comments
grebe
changed the title
copybara-service bot
pushed a commit
that referenced
this issue
Feb 19, 2025
This is probably paranoia, but it seems useful to be sure that if an assertion references a signal multiple times the reference should be resolved to the same value. Also, assertion predicates are referenced multiple times, so inline expressions can make assertions long and unreadable. While we're in here, we refactor the assertion logic a bit so that op overrides cause assertions to be emitted for Verilog. They were previously unconditionally disabled, but now we only disable assertions if we're not using SystemVerilog AND we don't have a format string for assertions. Ref: #1933. PiperOrigin-RevId: 728423377
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
The fuzzer found a scenario with a continuous assertion seems to be spuriously firing. I thought it might be related to inlining expressions causing weird simulator event-ordering things to happen, but addressing that didn't seem to fix it. I'm going to add the crasher and file this issue to track the problem.
The text was updated successfully, but these errors were encountered: