modules: zstd: axi_ram_writer: move proc-local const outside

laudominik · rw1nkler · commit 60484a930d10 · 2025-03-27T07:28:32.000+01:00
diff --git a/xls/modules/zstd/memory/axi_ram_writer.x b/xls/modules/zstd/memory/axi_ram_writer.x
@@ -212,6 +212,7 @@ proc AxiRamWriterResponder<
     }
 }
 
+const SYNC_FIFO_DEPTH=u32:1;
 pub proc AxiRamWriter<
     ADDR_W: u32, DATA_W: u32,ID_W: u32, RAM_SIZE: u32,
     RAM_ADDR_W: u32 = {std::clog2(RAM_SIZE)},
@@ -223,7 +224,6 @@ pub proc AxiRamWriter<
     type WriteReq = ram::WriteReq<RAM_ADDR_W, DATA_W, NUM_PARTITIONS>;
     type WriteResp = ram::WriteResp<DATA_W>;
     type Sync = AxiRamWriterSync<ID_W>;
-    const SYNC_FIFO_DEPTH=u32:1;
 
     init { }
 

Original file line number	Diff line number	Diff line change
`@@ -212,6 +212,7 @@ proc AxiRamWriterResponder<`
`212`	`212`	`}`
`213`	`213`	`}`
`214`	`214`
	`215`	`+const SYNC_FIFO_DEPTH=u32:1;`
`215`	`216`	`pub proc AxiRamWriter<`
`216`	`217`	`ADDR_W: u32, DATA_W: u32,ID_W: u32, RAM_SIZE: u32,`
`217`	`218`	`RAM_ADDR_W: u32 = {std::clog2(RAM_SIZE)},`
`@@ -223,7 +224,6 @@ pub proc AxiRamWriter<`
`223`	`224`	`type WriteReq = ram::WriteReq<RAM_ADDR_W, DATA_W, NUM_PARTITIONS>;`
`224`	`225`	`type WriteResp = ram::WriteResp<DATA_W>;`
`225`	`226`	`type Sync = AxiRamWriterSync<ID_W>;`
`226`		`- const SYNC_FIFO_DEPTH=u32:1;`
`227`	`227`
`228`	`228`	`init { }`
`229`	`229`