Replies: 2 comments
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The short asnwer is that the You're correct that the code is nearly identical. Perhaps some factory methods defined on a single class would provide an alternative. Inheritance from a type parameter (which defaults to an empty class) is done to allow wrapping existing classes. It's quite common in UVM environments to have an environment-specific base class for certain sequences. I wanted to ensure that these could easily be accessed. Let's assume we have a sequence base class: class my_seq_base extends uvm_sequence;
endclass We can create a new sequence that can interact with Python as follows: class my_my_seq extends WishboneInitiator #(my_seq_base);
virtual task write();
// Implement write for our environment
endtask
endclass |
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Ok. Currently, only the initiator class is used in the example. If I understand correctly, a SV object from the implementation class ( Could you maybe provide an example where the As always, thanks for your answers! |
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I have a question regarding the generated SystemVerilog header file
hdl_call_if_api.svh
in thecall_sv_bfm
example provided.In this header file there are three classes, the
interface
initiator class which extends the API base class, thevirtual
Initiator, and thevirtual
wrapper class.I am kinda confused about the last two because they are somehow identical. Why are both needed?
The second question is why do these two classes inherit from an empty base class, why not directly from the interface class
ICallApi
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