uart suffer from timing errors, on burst recieving

[Thonner]

https://github.com/freechipsproject/ip-contributions/tree/master/src/main/scala/chisel/lib/uart

The UART fails to read longer bursts of bytes. I Assume the reason is that the sampling frequency match the baud rate, which means a slight mismatch between the two ends of the communication leads to the sample time drifting into adjacent data frames. I suggest doing oversampling in the rx component. This is what I ended up doing in my implementation of a UART.