From be2e52d595d837135044bb75926f266dd01c7f1e Mon Sep 17 00:00:00 2001 From: chick Date: Wed, 25 Nov 2020 11:49:44 -0800 Subject: [PATCH 1/2] Bump chisel repos to 3.5-SNAPSHOTS Fix changes to running diagrammer due to diagrammer changes --- source/load-ivy.sc | 85 ++++++++++++++++++++-------------------------- 1 file changed, 36 insertions(+), 49 deletions(-) diff --git a/source/load-ivy.sc b/source/load-ivy.sc index 1669177..b6c889d 100644 --- a/source/load-ivy.sc +++ b/source/load-ivy.sc @@ -10,13 +10,15 @@ interp.configureCompiler(x => x.settings.source.value = scala.tools.nsc.settings // System.setProperty("https.proxyHost", "proxy.example.com") // System.setProperty("https.proxyPort", "3128") -import $ivy.`edu.berkeley.cs::chisel3:3.2.0` -import $ivy.`edu.berkeley.cs::chisel-iotesters:1.3.0` -import $ivy.`edu.berkeley.cs::chisel-testers2:0.1.0` -import $ivy.`edu.berkeley.cs::dsptools:1.2.0` +import $ivy.`edu.berkeley.cs::chisel3:3.4-SNAPSHOT` +import $ivy.`edu.berkeley.cs::chisel-iotesters:1.5-SNAPSHOT` +import $ivy.`edu.berkeley.cs::chiseltest:0.3-SNAPSHOT` +import $ivy.`edu.berkeley.cs::dsptools:1.4-SNAPSHOT` import $ivy.`org.scalanlp::breeze:0.13.2` import $ivy.`edu.berkeley.cs::rocket-dsptools:1.2.0` -import $ivy.`edu.berkeley.cs::firrtl-diagrammer:1.1.0` +import $ivy.`edu.berkeley.cs::firrtl-diagrammer:1.3-SNAPSHOT` + +import $ivy.`org.scalatest::scalatest:3.2.2` // Convenience function to invoke Chisel and grab emitted Verilog. def getVerilog(dut: => chisel3.core.UserModule): String = { @@ -103,72 +105,57 @@ def generateVisualizations(gen: () => chisel3.RawModule): (String, String) = { import almond.api.helpers.Display import chisel3._ + import chisel3.stage._ import chisel3.experimental._ import firrtl.ir.Module import sys.process._ - - val targetDir = "build" - val chiselIR = chisel3.Driver.elaborate(gen) - val firrtlIR = chisel3.Driver.emit(chiselIR) - val config = Config(targetDir = "build", firrtlSource = firrtlIR) - - val sourceFirrtl = { - if(config.firrtlSource.nonEmpty) { - config.firrtlSource - } - else { - scala.io.Source.fromFile(config.firrtlSourceFile).getLines().mkString("\n") - } - } + val sourceFirrtl = scala.Console.withOut(new PrintStream(new ByteArrayOutputStream())) { + (new ChiselStage).emitChirrtl(gen()) + } val ast = Parser.parse(sourceFirrtl) - val uniqueTop = ast.main + ast.hashCode().toHexString + + val uniqueTopName = ast.main + ast.hashCode().toHexString + + val targetDir = s"diagrams/$uniqueTopName/" + val cmdRegex = "cmd[0-9]+([A-Za-z]+.*)".r val readableTop = ast.main match { case cmdRegex(n) => n case other => other } val newTop = readableTop - + + // Console hack prevents unnecessary chatter appearing in cell + scala.Console.withOut(new PrintStream(new ByteArrayOutputStream())) { + val sourceFirrtl = (new ChiselStage).emitChirrtl(gen()) + val newModules: Seq[firrtl.ir.DefModule] = ast.modules.map { - case m: Module if m.name == ast.main => m.copy(name = newTop) - case other => other + case m: Module if m.name == ast.main => m.copy(name = newTop) + case other => other } - val newAst = ast.copy(main = newTop, modules = newModules) - - val controlAnnotations: Seq[Annotation] = config.toAnnotations - - val loweredAst = ToLoFirrtl.lower(newAst) - - FileUtils.makeDirectory(targetDir) - - FirrtlDiagrammer.addCss(targetDir) - val circuitState = CircuitState(loweredAst, LowForm, controlAnnotations) + val controlAnnotations: Seq[Annotation] = Seq( + firrtl.stage.FirrtlSourceAnnotation(sourceFirrtl), + firrtl.options.TargetDirAnnotation(targetDir), + dotvisualizer.stage.OpenCommandAnnotation("") + ) - if(config.justTopLevel) { - val justTopLevelTransform = new ModuleLevelDiagrammer - justTopLevelTransform.execute(circuitState) - } else { - val x = new MakeDiagramGroup - x.execute(circuitState) + (new dotvisualizer.stage.DiagrammerStage).execute(Array.empty, controlAnnotations) } + val moduleView = s"""$targetDir/$newTop.dot.svg""" + val instanceView = s"""$targetDir/${newTop}_hierarchy.dot.svg""" - s"cp build/${readableTop}.dot.svg build/${uniqueTop}.dot.svg"!! + val svgModuleText = FileUtils.getText(moduleView) + val svgInstanceText = FileUtils.getText(instanceView) - s"cp build/${readableTop}_hierarchy.dot.svg build/${uniqueTop}_hierarchy.dot.svg"!! - - val moduleView = targetDir + "/" + uniqueTop + ".dot.svg" - val x = """Module View""" - - val instanceView = targetDir + "/" + uniqueTop + "_hierarchy.dot.svg" - val y = """Hierarchy View""" - (x, y) + val x = s"""
$svgModuleText
""" + val y = s"""
width="100%" height="100%" overflow="scroll">$svgInstanceText
""" + (x, y) } - def visualize(gen: () => chisel3.RawModule): Unit = { val (moduleView, instanceView) = generateVisualizations(gen) html(moduleView) From 9d3a3dfd882c87d0807c3af5dd8d53939a94cbfb Mon Sep 17 00:00:00 2001 From: chick Date: Mon, 30 Nov 2020 13:17:29 -0800 Subject: [PATCH 2/2] Separate out the Diagrammer PR 67 changes Will but those in another PR --- source/load-ivy.sc | 67 ++++++++++++++++++++++++++++------------------ 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/source/load-ivy.sc b/source/load-ivy.sc index b6c889d..8806df2 100644 --- a/source/load-ivy.sc +++ b/source/load-ivy.sc @@ -105,20 +105,26 @@ def generateVisualizations(gen: () => chisel3.RawModule): (String, String) = { import almond.api.helpers.Display import chisel3._ - import chisel3.stage._ import chisel3.experimental._ import firrtl.ir.Module import sys.process._ - val sourceFirrtl = scala.Console.withOut(new PrintStream(new ByteArrayOutputStream())) { - (new ChiselStage).emitChirrtl(gen()) + val targetDir = "build" + val chiselIR = chisel3.Driver.elaborate(gen) + val firrtlIR = chisel3.Driver.emit(chiselIR) + val config = Config(targetDir = "build", firrtlSource = firrtlIR) + + val sourceFirrtl = { + if(config.firrtlSource.nonEmpty) { + config.firrtlSource + } + else { + scala.io.Source.fromFile(config.firrtlSourceFile).getLines().mkString("\n") + } } - val ast = Parser.parse(sourceFirrtl) - - val uniqueTopName = ast.main + ast.hashCode().toHexString - - val targetDir = s"diagrams/$uniqueTopName/" + val ast = Parser.parse(sourceFirrtl) + val uniqueTop = ast.main + ast.hashCode().toHexString val cmdRegex = "cmd[0-9]+([A-Za-z]+.*)".r val readableTop = ast.main match { case cmdRegex(n) => n @@ -126,36 +132,45 @@ def generateVisualizations(gen: () => chisel3.RawModule): (String, String) = { } val newTop = readableTop - // Console hack prevents unnecessary chatter appearing in cell - scala.Console.withOut(new PrintStream(new ByteArrayOutputStream())) { - val sourceFirrtl = (new ChiselStage).emitChirrtl(gen()) - val newModules: Seq[firrtl.ir.DefModule] = ast.modules.map { - case m: Module if m.name == ast.main => m.copy(name = newTop) - case other => other + case m: Module if m.name == ast.main => m.copy(name = newTop) + case other => other } + val newAst = ast.copy(main = newTop, modules = newModules) - val controlAnnotations: Seq[Annotation] = Seq( - firrtl.stage.FirrtlSourceAnnotation(sourceFirrtl), - firrtl.options.TargetDirAnnotation(targetDir), - dotvisualizer.stage.OpenCommandAnnotation("") - ) + val controlAnnotations: Seq[Annotation] = config.toAnnotations - (new dotvisualizer.stage.DiagrammerStage).execute(Array.empty, controlAnnotations) + val loweredAst = ToLoFirrtl.lower(newAst) + + FileUtils.makeDirectory(targetDir) + + FirrtlDiagrammer.addCss(targetDir) + + val circuitState = CircuitState(loweredAst, LowForm, controlAnnotations) + + if(config.justTopLevel) { + val justTopLevelTransform = new ModuleLevelDiagrammer + justTopLevelTransform.execute(circuitState) + } else { + val x = new MakeDiagramGroup + x.execute(circuitState) } - val moduleView = s"""$targetDir/$newTop.dot.svg""" - val instanceView = s"""$targetDir/${newTop}_hierarchy.dot.svg""" - val svgModuleText = FileUtils.getText(moduleView) - val svgInstanceText = FileUtils.getText(instanceView) + s"cp build/${readableTop}.dot.svg build/${uniqueTop}.dot.svg"!! - val x = s"""
$svgModuleText
""" - val y = s"""
width="100%" height="100%" overflow="scroll">$svgInstanceText
""" + s"cp build/${readableTop}_hierarchy.dot.svg build/${uniqueTop}_hierarchy.dot.svg"!! + val moduleView = targetDir + "/" + uniqueTop + ".dot.svg" + val x = """Module View""" + + val instanceView = targetDir + "/" + uniqueTop + "_hierarchy.dot.svg" + val y = """Hierarchy View""" (x, y) + } + def visualize(gen: () => chisel3.RawModule): Unit = { val (moduleView, instanceView) = generateVisualizations(gen) html(moduleView)